Prior to this commit the USB CDC used the USB start-of-frame (SOF) IRQ to
regularly check if buffered data needed to be sent out to the USB host.
This wasted resources (CPU, power) if no data needed to be sent.
This commit changes how the USB CDC transmits buffered data:
- When new data is first available to send the data is queued immediately
on the USB IN endpoint, ready to be sent as soon as possible.
- Subsequent additions to the buffer (via usbd_cdc_try_tx()) will wait.
- When the low-level USB driver has finished sending out the data queued
in the USB IN endpoint it calls usbd_cdc_tx_ready() which immediately
queues any outstanding data, waiting for the next IN frame.
The benefits on this new approach are:
- SOF IRQ does not need to run continuously so device has a better chance
to sleep for longer, and be more responsive to other IRQs.
- Because SOF IRQ is off, current consumption is reduced by a small amount,
roughly 200uA when USB is connected (measured on PYBv1.0).
- CDC tx throughput (USB IN) on PYBv1.0 is about 2.3 faster (USB OUT is
unchanged).
- When USB is connected, Python code that is executing is slightly faster
because SOF IRQ no longer interrupts continuously.
- On F733 with USB HS, CDC tx throughput is about the same as prior to this
commit.
- On F733 with USB HS, Python code is about 5% faster because of no SOF.
As part of this refactor, the serial port should no longer echo initial
characters when the serial port is first opened (this only used to happen
rarely on USB FS, but on USB HS is was more evident).
The macros are MICROPY_HEAP_START and MICROPY_HEAP_END, and if not defined
by a board then the default values will be used (maximum heap from SRAM as
defined by linker symbols).
As part of this commit the SDRAM initialisation is moved to much earlier in
main() to potentially make it available to other peripherals and avoid
re-initialisation on soft-reboot. On boards with SDRAM enabled the heap
has been set to use that.
Configuring clocks is a critical operation and is best to avoid when
possible. If the clocks really need to be reset to the same values then
one can pass in a slightly higher value, eg 168000001 Hz to get 168MHz.
This ensures that on first boot the most optimal settings are used for the
voltage scaling and flash latency (for F7 MCUs).
This commit also provides more fine-grained control for the flash latency
settings.
Power and clock control is low-level functionality and it makes sense to
have it in a dedicated file, at least so it can be reused by other parts of
the code.
On F7s PLLSAI is used as a 48MHz clock source if the main PLL cannot
provide such a frequency, and on L4s PLLSAI1 is always used as a clock
source for the peripherals. This commit makes sure these PLLs are
re-enabled upon waking from stop mode so the peripherals work.
See issues #4022 and #4178 (L4 specific).
This part is functionally similar to STM32F767xx (they share a datasheet)
so support is generally comparable. When adding board support the
stm32f767_af.csv and stm32f767.ld should be used.
The HAL DMA functions enable SDMMC interrupts before fully resetting the
peripheral, and this can lead to a DTIMEOUT IRQ during the initialisation
of the DMA transfer, which then clears out the DMA state and leads to the
read/write not working at all. The DTIMEOUT is there from previous SDMMC
DMA transfers, even those that succeeded, and is of duration ~180 seconds,
which is 0xffffffff / 24MHz (default DTIMER value, and clock of
peripheral).
To work around this issue, fully reset the SDMMC peripheral before calling
the HAL SD DMA functions.
Fixes issue #4110.
The flash-IRQ handler is used to flush the storage cache, ie write
outstanding block data from RAM to flash. This is triggered by a timeout,
or by a direct call to flush all storage caches.
Prior to this commit, a timeout could trigger the cache flushing to occur
during the execution of a read/write to external SPI flash storage. In
such a case the storage subsystem would break down.
SPI storage transfers are already protected against USB IRQs, so by
changing the priority of the flash IRQ to that of the USB IRQ (what is
done in this commit) the SPI transfers can be protected against any
timeouts triggering a cache flush (the cache flush would be postponed until
after the transfer finished, but note that in the case of SPI writes the
timeout is rescheduled after the transfer finishes).
The handling of internal flash sync'ing needs to be changed to directly
call flash_bdev_irq_handler() sync may be called with the IRQ priority
already raised (eg when called from a USB MSC IRQ handler).
MCUs that have a PLLSAI can use it to generate a 48MHz clock for USB, SDIO
and RNG peripherals. In such cases the SYSCLK is not restricted to values
that allow the system PLL to generate 48MHz, but can be any frequency.
This patch allows such configurability for F7 MCUs, allowing the SYSCLK to
be set in 2MHz increments via machine.freq(). PLLSAI will only be enabled
if needed, and consumes about 1mA extra. This fine grained control of
frequency is useful to get accurate SPI baudrates, for example.
A recent version of arm-none-eabi-gcc (8.2.0) will warn about unused packed
attributes in USB_WritePacket and USB_ReadPacket. This patch suppresses
such warnings for this file only.
The aim here is to have spi.c contain the low-level SPI driver which is
independent (not fully but close) of MicroPython objects and methods, and
the higher-level bindings are separated out to pyb_spi.c and machine_spi.c.
- Allow configuration by a board of autorefresh number and burst length.
- Increase MPU region size to 8MiB.
- Make SDRAM region cacheable and executable.
Requesting a baudrate of X should never configure the peripheral to have a
baudrate greater than X because connected hardware may not be able to
handle higher speeds. This patch makes sure to round the prescaler up so
that the actual baudrate is rounded down.
Prior to this patch, if VBAT was read via ADC.read() or
ADCAll.read_channel(), then it would remain enabled and subsequent reads
of TEMPSENSOR or VREFINT would not work. This patch makes sure that VBAT
is disabled for all cases that it could be read.
When waking from stop mode most of the system is still in the same state as
before entering stop, so only minimal configuration is needed to bring the
system clock back online.
A recent version of arm-none-eabi-gcc (8.2.0) will warn about unused packed
attributes in USB_WritePacket and USB_ReadPacket. This patch suppresses
such warnings for this file only.
Works with pins declared normally in mpconfigboard.h, eg. (pin_XX), as well
as (pyb_pin_XX).
Provides new mp_hal_pin_config_alt_static(pin_obj, mode, pull, fn_type)
function declared in pin_static_af.h to allow configuring pin alternate
functions by name at compile time.
The code was dereferencing 0x800 and loading a value from there, trying to
use a literal value (not address) defined in the linker script
(_ram_fs_cache_block_size) which was 0x800.
The period of the timer can now be specified using the "period" and
"tick_hz" args. The period in seconds will be: period/tick_hz. tick_hz
defaults to 1000, so if period is specified on its own then it will be in
units of milliseconds.
Prior to this patch, get_fattime() was calling a HAL RTC function with the
HW instance pointer as null because rtc_init_start() was never called.
Also marked it as a weak function, to allow a board to override it.
With this and previous patches the stm32 port can now be compiled using
object representation D (nan boxing). Note that native code and frozen mpy
files with float constants are currently not supported with this object
representation.
Prior to this patch, if both USB FS and HS were enabled via the
configuration file then code was included to handle both of their IRQs.
But mboot only supports listening on a single USB peripheral, so this patch
excludes the code for the USB that is not used.
Only one of pcd_fs_handle/pcd_hs_handle is ever initialised, so if both of
these USB peripherals are enabled then one of these if-statements will
access invalid memory pointed to by an uninitialised Instance. This patch
fixes this bug by explicitly referencing the peripheral struct.
This patch adds support to mboot for programming external SPI flash. It
allows SPI flash to be programmed via a USB DFU utility in the same way
that internal MCU flash is programmed.
Prior to this patch the QSPI driver assumed that the length of all data
reads and writes was a multiple of 4. This patch allows any length. Reads
are optimised for speed by using 32-bit transfers when possible, but writes
always use a byte transfer because they only use a single data IO line and
are relatively slow.
The DMA peripheral is limited to transferring 65535 elements at a time so
in order to send more than that the SPI driver must split the transfers up.
The user must be aware of this limit if they are relying on precise timing
of the entire SPI transfer, because there might be a small delay between
the split transfers.
Fixes issue #3851, and thanks to @kwagyeman for the original fix.
If the user button is held down indefinitely (eg unintenionally, or because
the GPIO signal of the user button is connected to some external device)
then it makes sense to end the reset mode cycle with the default mode of
1, which executes code as normal.
It's possible (at least on F4 MCU's) to have RXNE and STOPF set at the same
time during a call to the slave IRQ handler. In such cases RXNE should be
handled before STOPF so that all bytes are processed before
i2c_slave_process_rx_end() is called.
Due to buffering of outgoing bytes on the I2C bus, detection of a NACK
using the ISR_NACKF flag needs to account for the case where ISR_NACKF
corresponds to the previous-to-previous byte.
This patch renames the existing SPI flash API functions to reflect the fact
that the go through the cache:
mp_spiflash_flush -> mp_spiflash_cache_flush
mp_spiflash_read -> mp_spiflash_cached_read
mp_spiflash_write -> mp_spiflash_cached_write
The DFU USB config descriptor returns 0x0800=2048 for the supported
transfer size, and this applies to both TX (IN) and RX (OUT). So increase
the rx_buf to support this size without having a buffer overflow on
received data.
With this patch mboot in USB DFU mode now works with dfu-util.
MICROPY_PY_DELATTR_SETATTR can now be enabled without a performance hit for
classes that don't use this feature.
MICROPY_PY_BUILTINS_NOTIMPLEMENTED is a minor addition that improves
compatibility with CPython.
They are now efficient (in runtime performance) and provide a useful
feature that's hard to obtain without them enabled.
See issue #3644 and PR #3826 for background.
The Wiznet5k series of chips support a MACRAW mode which allows the host to
send and receive Ethernet frames directly. This can be hooked into the
lwIP stack to provide a full "socket" implementation using this Wiznet
Ethernet device. This patch adds support for this feature.
To enable the feature one must add the following to mpconfigboard.mk, or
mpconfigport.mk:
MICROPY_PY_WIZNET5K = 5500
and the following to mpconfigboard.h, or mpconfigport.h:
#define MICROPY_PY_LWIP (1)
After wiring up the module (X5=CS, X4=RST), usage on a pyboard is:
import time, network
nic = network.WIZNET5K(pyb.SPI(1), pyb.Pin.board.X5, pyb.Pin.board.X4)
nic.active(1)
while not nic.isconnected():
time.sleep_ms(50) # needed to poll the NIC
print(nic.ifconfig())
Then use the socket module as usual.
Compared to using the built-in TCP/IP stack on the Wiznet module, some
performance is lost in MACRAW mode: with a lot of memory allocated to lwIP
buffers, lwIP gives Around 750,000 bytes/sec max TCP download, compared
with 1M/sec when using the TCP/IP stack on the Wiznet module.
It should be up to the NIC itself to decide if the network interface is
removed upon soft reset. Some NICs can keep the interface up over a soft
reset, which improves usability of the network.
Pins with multiple alt-funcs for the same peripheral (eg USART_CTS_NSS)
need to be split into individual alt-funcs for make-pins.py to work
correctly.
This patch changes the following:
- Split `..._CTS_NSS` into `..._CTS/..._NSS`
- Split `..._RTS_DE` into `..._RTS/..._DE`
- Split `JTDO_SWO` into `JTDO/TRACESWO` for consistency
- Fixed `TRACECK` to `TRACECLK` for consistency
If no block devices are defined by a board then storage support will be
disabled. This means there is no filesystem provided by either the
internal flash or external SPI flash. But the VFS system can still be
enabled and filesystems provided on external devices like an SD card.
Mboot is a custom bootloader for STM32 MCUs. It can provide a USB DFU
interface on either the FS or HS peripherals, as well as a custom I2C
bootloader interface.
These files provide no additional information, all the version and license
information is captured in the relevant files in these subdirectories.
Thanks to @JoeSc for the original patch.
This patch allows to use lwIP as the implementation of the usocket module,
instead of the existing socket-multiplexer that delegates the entire TCP/IP
layer to the NIC itself.
This is disabled by default, and enabled by defining MICROPY_PY_LWIP to 1.
When enabled, the lwIP TCP/IP stack will be included in the build with
default settings for memory usage and performance (see
lwip_inc/lwipopts.h). It is then up to a particular NIC to register itself
with lwIP using the standard lwIP netif API.
This patch adds the configuration MICROPY_HW_USB_ENABLE_CDC2 which enables
a new USB device configuration at runtime: VCP+VCP+MSC. It will give two
independent VCP interfaces available via pyb.USB_VCP(0) and pyb.USB_VCP(1).
The first one is the usual one and has the REPL on it. The second one is
available for general use.
This configuration is disabled by default because if the mode is not used
then it takes up about 2200 bytes of RAM. Also, F4 MCUs can't support this
mode on their USB FS peripheral (eg PYBv1.x) because they don't have enough
endpoints. The USB HS peripheral of an F4 supports it, as well as both the
USB FS and USB HS peripherals of F7 MCUs.
The documentation (including the examples) for elapsed_millis and
elapsed_micros can be found in docs/library/pyb.rst so doesn't need to be
written in full in the source code.
When disabled, the pyb.I2C class saves around 8k of code space and 172
bytes of RAM. The same functionality is now available in machine.I2C
(for F4 and F7 MCUs).
It is still enabled by default.
This driver uses low-level register access to control the I2C peripheral
(ie it doesn't rely on the ST HAL) and provides the same C-level API as the
existing F7 hardware driver.
On this 32-bit arch there's no need to use the long version of the format
specifier. It's only there to appease the compiler which checks the type
of the args passed to printf. Removing the "l" saves a bit of code space.
For a given IRQn (eg UART) there's no need to carry around both a PRI and
SUBPRI value (eg IRQ_PRI_UART, IRQ_SUBPRI_UART). Instead, the IRQ_PRI_UART
value has been changed in this patch to be the encoded hardware value,
using NVIC_EncodePriority. This way the NVIC_SetPriority function can be
used directly, instead of going through HAL_NVIC_SetPriority which must do
extra processing to encode the PRI+SUBPRI.
For a priority grouping of 4 (4 bits for preempt priority, 0 bits for the
sub-priority), which is used in the stm32 port, the IRQ_PRI_xxx constants
remain unchanged in their value.
This patch also "fixes" the use of raise_irq_pri() which should be passed
the encoded value (but as mentioned above the unencoded value is the same
as the encoded value for priority grouping 4, so there was no bug from this
error).
The problem is the existing code which tries to optimise the
reinitialisation of the DMA breaks the abstraction of the HAL. For the
STM32L4 the HAL's DMA setup code maintains two private vars (ChannelIndex,
DmaBaseAddress) and updates a hardware register (CCR).
In HAL_DMA_Init(), the CCR is updated to set the direction of the DMA.
This is a problem because, when using the SD Card interface, the same DMA
channel is used in both directions, so the direction bit in the CCR must
follow that.
A quick and effective fix for the L4 is to simply call HAL_DMA_DeInit() and
HAL_DMA_Init() every time.
ADC3 is used because the H7's internal ADC channels are connected to ADC3
and the uPy driver doesn't support more than one ADC.
Only 12-bit resolution is supported because 12 is hard-coded and 14/16 bits
are not recommended on some ADC3 pins (see errata).
Values from internal ADC channels are known to give wrong values at
present.
After calling HAL_SYSTICK_Config the SysTick IRQ priority is set to 15, the
lowest priority. This commit reconfigures the IRQ priority to the desired
TICK_INT_PRIORITY value.
By default the stm module is included in the build, but a board can now
define MICROPY_PY_STM to 0 to not include this module. This reduces the
firmware by about 7k.
To use HSE bypass mode the board should define:
#define MICROPY_HW_CLK_USE_BYPASS (1)
If this is not defined, or is defined to 0, then HSE oscillator mode is
used.
This patch allows a given board to configure which pins are used for the
CAN peripherals, in a similar way to all the other bus peripherals (I2C,
UART, SPI). To enable CAN on a board the mpconfigboard.h file should
define (for example):
#define MICROPY_HW_CAN1_TX (pin_B9)
#define MICROPY_HW_CAN1_RX (pin_B8)
#define MICROPY_HW_CAN2_TX (pin_B13)
#define MICROPY_HW_CAN2_RX (pin_B12)
And the board config file should no longer define MICROPY_HW_ENABLE_CAN.
The individual union members (like SPI, I2C) are never used, only the
generic "reg" entry is. And the union names can clash with macro
definitions in the HAL so better to remove them.
The only configuration that changes with this patch is that on L4 MCUs the
clock prescaler changed from ADC_CLOCK_ASYNC_DIV2 to ADC_CLOCK_ASYNC_DIV1
for the ADCAll object. This should be ok.
A value of DISABLE for EOCSelection is invalid. This would have been
interpreted instead as ADC_EOC_SEQ_CONV, but really it should be
ADC_EOC_SINGLE_CONV for the uses in this code. So this has been fixed.
ExternalTrigConv should be ADC_SOFTWARE_START because all ADC
conversions are started by software. This is now fixed.
This can be used to select the output buffer behaviour of the DAC. The
default values are chosen to retain backwards compatibility with existing
behaviour.
Thanks to @peterhinch for the initial idea to add this feature.
This patch moves the implementation of stream closure from a dedicated
method to the ioctl of the stream protocol, for each type that implements
closing. The benefits of this are:
1. Rounds out the stream ioctl function, which already includes flush,
seek and poll (among other things).
2. Makes calling mp_stream_close() on an object slightly more efficient
because it now no longer needs to lookup the close method and call it,
rather it just delegates straight to the ioctl function (if it exists).
3. Reduces code size and allows future types that implement the stream
protocol to be smaller because they don't need a dedicated close method.
Code size reduction is around 200 bytes smaller for x86 archs and around
30 bytes smaller for the bare-metal archs.
The main() function has a predefined type in C which is not so useful for
embedded contexts. This patch renames main() to stm32_main() so we can
define our own type signature for this function. The type signature is
defined to have a single argument which is the "reset_mode" and is passed
through as r0 from Reset_Handler. This allows, for example, a bootloader
to pass through information into the main application.
The Reset_Handler needs to copy the data section and zero the BSS, and
these operations should be as optimised as possible to reduce start up
time. The versions provided in this patch are about 2x faster (on a Cortex
M4) than the previous implementations.
Rather than pin objects themselves. The actual object is now pin_X_obj and
defines are provided so that pin_X is &pin_X_obj. This makes it so that
code that uses pin objects doesn't need to know if they are literals or
objects (that need pointers taken) or something else. They are just
entities that can be passed to the map_hal_pin_xxx functions. This mirrors
how the core handles constant objects (eg mp_const_none which is
&mp_const_none_obj) and allows for the possibility of different
implementations of the pin layer.
For example, prior to this patch there was the following:
extern const pin_obj_t pin_A0;
#define pyb_pin_X1 pin_A0
...
mp_hal_pin_high(&pin_A0);
and now there is:
extern const pin_obj_t pin_A0_obj;
#define pin_A0 (&pin_A0_obj)
#define pyb_pin_X1 pin_A0
...
mp_hal_pin_high(pin_A0);
This patch should have minimal effect on board configuration files. The
only change that may be needed is if a board has .c files that configure
pins.
This patch forces a board to explicitly define TEXT1_ADDR in order to
split the firmware into two separate pieces. Otherwise the default is now
to produce only a single continuous firmware image with all ISR, text and
data together.
This patch allows a particular board to independently specify the linker
scripts for 1) the MCU memory layout; 2) how the different firmware
sections are arranged in memory. Right now all boards follow the same
layout with two separate firmware section, one for the ISR and one for the
text and data. This leaves room for storage (filesystem data) to live
between the firmware sections.
The idea with this patch is to accommodate boards that don't have internal
flash storage and only need to have one continuous firmware section. Thus
the common.ld script is renamed to common_ifs.ld to make explicit that it
is used for cases where the board has internal flash storage.
Explicitly writing out the implementation of sys_tick_has_passed makes
these bdev files independent of systick.c and more reusable as a general
component. It also reduces the code size slightly.
The irq.h header is added to spibdev.c because it uses declarations in that
file (irq.h is usually included implicitly via mphalport.h but not always).
Taking the address assumes that the pin is an object (eg a struct), but it
could be a literal (eg an int). Not taking the address makes this driver
more general for other uses.
genhdr/pins.h is an internal header file that defines all of the pin
objects and it's cleaner to have pin.h include it (where the struct's for
these objects are defined) rather than an explicit include by every user.
The HAL requires strict aliasing optimisation to be turned on to function
correctly (at least for the SD card driver on F4 MCUs). This optimisation
was recently disabled with the addition of H7 support due to the H7 HAL
having errors with the strict aliasing optimisation enabled. But this is
now fixed in the latest stm32lib and so the optimisation can now be
re-enabled.
Thanks to @chuckbook for finding that there was a problem with the SD card
on F4 MCUs with the strict aliasing optimisation disabled.
The CMSIS files for the STM32 range provide macros to distinguish between
the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer
to use these instead of custom ones.
This patch provides a custom (and simple) function to receive data on the
CAN bus, instead of the HAL function. This custom version calls
mp_handle_pending() while waiting for messages, which, among other things,
allows to interrupt the recv() method via KeyboardInterrupt.
This config variable controls whether to support storage on the internal
flash of the MCU. It is enabled by default and should be explicitly
disabled by boards that don't want internal flash storage.
It makes it cleaner, and simpler to support multiple different block
devices. It also allows to easily extend a given block device with new
ioctl operations.
This patch alters the SPI-flash memory driver so that it uses the new
low-level C SPI protocol (from drivers/bus/spi.h) instead of the uPy SPI
protocol (from extmod/machine_spi.h). This allows the SPI-flash driver to
be used independently from the uPy runtime.
This patch takes the software SPI implementation from extmod/machine_spi.c
and moves it to a dedicated file in drivers/bus/softspi.c. This allows the
SPI driver to be used independently of the uPy runtime, making it a more
general component.
Damien George
Michael Paul Coder
Tobias Badertscher
roland
iabdalkader
Andrew Leech
Andrew Leech
forester3
David Lechner
Peter D. Gray
Tobias Badertscher
Ryan Shaw
Peter Hinch
Tom Collins