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stm32/system_stm32: Introduce configuration defines for PLL3 settings.

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A board must be able to set the PLL3 values based on the HSE that it uses.
This commit is contained in:
roland 2018-10-24 22:52:36 +02:00 committed by Damien George
parent 06643a0df4
commit 30ed2b3cab
2 changed files with 12 additions and 5 deletions
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7
ports/stm32/boards/NUCLEO_H743ZI/mpconfigboard.h
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@ -20,6 +20,13 @@ void NUCLEO_H743ZI_board_early_init(void);
#define MICROPY_HW_CLK_PLLQ (4)
#define MICROPY_HW_CLK_PLLR (2)
// The USB clock is set using PLL3
#define MICROPY_HW_CLK_PLL3M (4)
#define MICROPY_HW_CLK_PLL3N (120)
#define MICROPY_HW_CLK_PLL3P (2)
#define MICROPY_HW_CLK_PLL3Q (5)
#define MICROPY_HW_CLK_PLL3R (2)
// 4 wait states
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_4

10
ports/stm32/system_stm32.c
View File

@ -517,11 +517,11 @@ void SystemClock_Config(void)
/* PLL3 for USB Clock */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
PeriphClkInitStruct.PLL3.PLL3M = 4;
PeriphClkInitStruct.PLL3.PLL3N = 120;
PeriphClkInitStruct.PLL3.PLL3P = 2;
PeriphClkInitStruct.PLL3.PLL3Q = 5;
PeriphClkInitStruct.PLL3.PLL3R = 2;
PeriphClkInitStruct.PLL3.PLL3M = MICROPY_HW_CLK_PLL3M;
PeriphClkInitStruct.PLL3.PLL3N = MICROPY_HW_CLK_PLL3N;
PeriphClkInitStruct.PLL3.PLL3P = MICROPY_HW_CLK_PLL3P;
PeriphClkInitStruct.PLL3.PLL3Q = MICROPY_HW_CLK_PLL3Q;
PeriphClkInitStruct.PLL3.PLL3R = MICROPY_HW_CLK_PLL3R;
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;