stm32/boards: Add startup_stm32f0.s for STM32F0 MCUs.
Sourced from STM32Cube_FW_F0_V1.9.0.
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Damien George
parent
191e2cf90a
commit
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303
ports/stm32/boards/startup_stm32f0.s
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303
ports/stm32/boards/startup_stm32f0.s
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/**
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******************************************************************************
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* @file startup_stm32f091xc.s
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* @author MCD Application Team
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* @brief STM32F091xC devices vector table for GCC toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M0 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m0
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =_estack
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mov sp, r0 /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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ldr r0, =_sdata
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ldr r1, =_edata
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ldr r2, =_sidata
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movs r3, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r4, [r2, r3]
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str r4, [r0, r3]
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adds r3, r3, #4
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LoopCopyDataInit:
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adds r4, r0, r3
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cmp r4, r1
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bcc CopyDataInit
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/* Zero fill the bss segment. */
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ldr r2, =_sbss
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ldr r4, =_ebss
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movs r3, #0
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b LoopFillZerobss
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FillZerobss:
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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cmp r2, r4
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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/*bl __libc_init_array*/
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/* Call the application's entry point.*/
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bl main
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M0. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word 0
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word WWDG_IRQHandler /* Window WatchDog */
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.word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */
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.word RTC_IRQHandler /* RTC through the EXTI line */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_CRS_IRQHandler /* RCC and CRS */
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.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
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.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
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.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
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.word TSC_IRQHandler /* TSC */
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.word DMA1_Ch1_IRQHandler /* DMA1 Channel 1 */
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.word DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler /* DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 */
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.word DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler /* DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 */
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.word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
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.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word TIM3_IRQHandler /* TIM3 */
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.word TIM6_DAC_IRQHandler /* TIM6 and DAC */
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.word TIM7_IRQHandler /* TIM7 */
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.word TIM14_IRQHandler /* TIM14 */
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.word TIM15_IRQHandler /* TIM15 */
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.word TIM16_IRQHandler /* TIM16 */
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.word TIM17_IRQHandler /* TIM17 */
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.word I2C1_IRQHandler /* I2C1 */
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.word I2C2_IRQHandler /* I2C2 */
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.word SPI1_IRQHandler /* SPI1 */
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.word SPI2_IRQHandler /* SPI2 */
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.word USART1_IRQHandler /* USART1 */
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.word USART2_IRQHandler /* USART2 */
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.word USART3_8_IRQHandler /* USART3, USART4, USART5, USART6, USART7, USART8 */
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.word CEC_CAN_IRQHandler /* CEC and CAN */
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler,Default_Handler
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.weak PVD_VDDIO2_IRQHandler
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.thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
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.weak RTC_IRQHandler
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.thumb_set RTC_IRQHandler,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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.weak RCC_CRS_IRQHandler
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.thumb_set RCC_CRS_IRQHandler,Default_Handler
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.weak EXTI0_1_IRQHandler
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.thumb_set EXTI0_1_IRQHandler,Default_Handler
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.weak EXTI2_3_IRQHandler
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.thumb_set EXTI2_3_IRQHandler,Default_Handler
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.weak EXTI4_15_IRQHandler
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.thumb_set EXTI4_15_IRQHandler,Default_Handler
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.weak TSC_IRQHandler
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.thumb_set TSC_IRQHandler,Default_Handler
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.weak DMA1_Ch1_IRQHandler
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.thumb_set DMA1_Ch1_IRQHandler,Default_Handler
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.weak DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
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.thumb_set DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler,Default_Handler
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.weak DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
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.thumb_set DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler,Default_Handler
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.weak ADC1_COMP_IRQHandler
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.thumb_set ADC1_COMP_IRQHandler,Default_Handler
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.weak TIM1_BRK_UP_TRG_COM_IRQHandler
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.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
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.weak TIM1_CC_IRQHandler
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.thumb_set TIM1_CC_IRQHandler,Default_Handler
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.weak TIM2_IRQHandler
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.thumb_set TIM2_IRQHandler,Default_Handler
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.weak TIM3_IRQHandler
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.thumb_set TIM3_IRQHandler,Default_Handler
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.weak TIM6_DAC_IRQHandler
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.thumb_set TIM6_DAC_IRQHandler,Default_Handler
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.weak TIM7_IRQHandler
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.thumb_set TIM7_IRQHandler,Default_Handler
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.weak TIM14_IRQHandler
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.thumb_set TIM14_IRQHandler,Default_Handler
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.weak TIM15_IRQHandler
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.thumb_set TIM15_IRQHandler,Default_Handler
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.weak TIM16_IRQHandler
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.thumb_set TIM16_IRQHandler,Default_Handler
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.weak TIM17_IRQHandler
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.thumb_set TIM17_IRQHandler,Default_Handler
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.weak I2C1_IRQHandler
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.thumb_set I2C1_IRQHandler,Default_Handler
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.weak I2C2_IRQHandler
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.thumb_set I2C2_IRQHandler,Default_Handler
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler,Default_Handler
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.weak SPI2_IRQHandler
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.thumb_set SPI2_IRQHandler,Default_Handler
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.weak USART1_IRQHandler
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.thumb_set USART1_IRQHandler,Default_Handler
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.weak USART2_IRQHandler
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.thumb_set USART2_IRQHandler,Default_Handler
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.weak USART3_8_IRQHandler
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.thumb_set USART3_8_IRQHandler,Default_Handler
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.weak CEC_CAN_IRQHandler
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.thumb_set CEC_CAN_IRQHandler,Default_Handler
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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