stm32/machine_i2c: Use new F4 hardware I2C driver for machine.I2C class.
And remove the old one based on ST code.
This commit is contained in:
Damien George
parent
b21415ed4f
commit
ce824bb67e
@ -3,7 +3,7 @@
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016 Damien P. George
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* Copyright (c) 2016-2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -37,386 +37,7 @@
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STATIC const mp_obj_type_t machine_hard_i2c_type;
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#if defined(STM32F4)
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// F4xx specific driver for I2C hardware peripheral
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// The hardware-specific I2C code below is based heavily on the code from
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// V1.5.2 of the STM32 CUBE F4 HAL. Its copyright notice is given here.
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/*
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* COPYRIGHT(c) 2016 STMicroelectronics
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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typedef struct _machine_hard_i2c_obj_t {
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mp_obj_base_t base;
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const pyb_i2c_obj_t *pyb;
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uint32_t *timeout;
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} machine_hard_i2c_obj_t;
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STATIC uint32_t machine_hard_i2c_timeout[4];
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STATIC const machine_hard_i2c_obj_t machine_hard_i2c_obj[] = {
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{{&machine_hard_i2c_type}, &pyb_i2c_obj[0], &machine_hard_i2c_timeout[0]},
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{{&machine_hard_i2c_type}, &pyb_i2c_obj[1], &machine_hard_i2c_timeout[1]},
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{{&machine_hard_i2c_type}, &pyb_i2c_obj[2], &machine_hard_i2c_timeout[2]},
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{{&machine_hard_i2c_type}, &pyb_i2c_obj[3], &machine_hard_i2c_timeout[3]},
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};
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STATIC void machine_hard_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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machine_hard_i2c_obj_t *self = MP_OBJ_TO_PTR(self_in);
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mp_printf(print, "I2C(%u, freq=%u, timeout=%u)",
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self - &machine_hard_i2c_obj[0] + 1,
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pyb_i2c_get_baudrate(self->pyb->i2c),
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*self->timeout);
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}
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STATIC void machine_hard_i2c_init(const machine_hard_i2c_obj_t *self, uint32_t freq, uint32_t timeout) {
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*self->timeout = timeout;
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pyb_i2c_init_freq(self->pyb, freq);
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}
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// this function is based on STM code
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STATIC bool I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) {
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if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) {
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/* Clear NACKF Flag */
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__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
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return true;
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}
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return false;
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}
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// this function is based on STM code
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STATIC bool I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) {
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/* Wait until flag is set */
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while ((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) {
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if (Timeout != HAL_MAX_DELAY) {
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if ((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) {
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return false;
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}
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}
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}
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return true;
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}
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// this function is based on STM code
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STATIC int I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) {
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while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) {
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/* Check if a STOPF is detected */
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if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) {
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/* Clear STOP Flag */
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__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
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return -MP_EBUSY;
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}
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/* Check for the Timeout */
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if ((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) {
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return -MP_ETIMEDOUT;
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}
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}
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return 0;
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}
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// this function is based on STM code
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STATIC int send_addr_byte(I2C_HandleTypeDef *hi2c, uint8_t addr_byte, uint32_t Timeout, uint32_t Tickstart) {
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/* Generate Start */
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hi2c->Instance->CR1 |= I2C_CR1_START;
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/* Wait until SB flag is set */
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if (!I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart)) {
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return -MP_ETIMEDOUT;
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}
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/* Send slave address */
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hi2c->Instance->DR = addr_byte;
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/* Wait until ADDR flag is set */
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while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET) {
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if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) {
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// nack received for addr, release the bus cleanly
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hi2c->Instance->CR1 |= I2C_CR1_STOP;
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__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
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return -MP_ENODEV;
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}
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/* Check for the Timeout */
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if (Timeout != HAL_MAX_DELAY) {
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if ((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) {
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return -MP_ETIMEDOUT;
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}
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}
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}
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return 0;
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}
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// this function is based on STM code
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int machine_hard_i2c_readfrom(mp_obj_base_t *self_in, uint16_t addr, uint8_t *dest, size_t len, bool stop) {
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machine_hard_i2c_obj_t *self = (machine_hard_i2c_obj_t*)self_in;
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I2C_HandleTypeDef *hi2c = self->pyb->i2c;
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uint32_t Timeout = *self->timeout;
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/* Init tickstart for timeout management*/
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uint32_t tickstart = HAL_GetTick();
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#if 0
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// TODO: for multi-master, here we could wait for the bus to be free
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// we'd need a flag to tell if we were in the middle of a set of transactions
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// (ie didn't send a stop bit in the last call)
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/* Wait until BUSY flag is reset */
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if (!I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart)) {
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return -MP_EBUSY;
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}
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#endif
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/* Check if the I2C is already enabled */
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if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
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/* Enable I2C peripheral */
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__HAL_I2C_ENABLE(hi2c);
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}
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/* Disable Pos */
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hi2c->Instance->CR1 &= ~I2C_CR1_POS;
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/* Enable Acknowledge */
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hi2c->Instance->CR1 |= I2C_CR1_ACK;
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/* Send Slave Address */
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int ret = send_addr_byte(hi2c, I2C_7BIT_ADD_READ(addr << 1), Timeout, tickstart);
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if (ret != 0) {
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return ret;
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}
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if (len == 0U) {
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/* Clear ADDR flag */
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__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
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/* Generate Stop */
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if (stop) {
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hi2c->Instance->CR1 |= I2C_CR1_STOP;
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}
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} else if (len == 1U) {
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/* Disable Acknowledge */
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hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
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/* Clear ADDR flag */
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__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
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/* Generate Stop */
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if (stop) {
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hi2c->Instance->CR1 |= I2C_CR1_STOP;
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}
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} else if (len == 2U) {
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/* Disable Acknowledge */
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hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
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/* Enable Pos */
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hi2c->Instance->CR1 |= I2C_CR1_POS;
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/* Clear ADDR flag */
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__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
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} else {
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/* Enable Acknowledge */
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hi2c->Instance->CR1 |= I2C_CR1_ACK;
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/* Clear ADDR flag */
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__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
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}
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while (len > 0U) {
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if (len <= 3U) {
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if (len == 1U) {
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/* Wait until RXNE flag is set */
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int ret = I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart);
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if (ret != 0) {
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return ret;
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}
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/* Read data from DR */
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*dest++ = hi2c->Instance->DR;
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len--;
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} else if (len == 2U) {
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/* Wait until BTF flag is set */
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if (!I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart)) {
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return -MP_ETIMEDOUT;
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}
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/* Generate Stop */
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if (stop) {
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hi2c->Instance->CR1 |= I2C_CR1_STOP;
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}
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/* Read data from DR */
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*dest++ = hi2c->Instance->DR;
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len--;
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/* Read data from DR */
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*dest++ = hi2c->Instance->DR;
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len--;
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} else {
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/* Wait until BTF flag is set */
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if (!I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart)) {
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return -MP_ETIMEDOUT;
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}
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/* Disable Acknowledge */
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hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
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/* Read data from DR */
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*dest++ = hi2c->Instance->DR;
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len--;
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/* Wait until BTF flag is set */
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if (!I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart)) {
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return -MP_ETIMEDOUT;
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}
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/* Generate Stop */
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if (stop) {
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hi2c->Instance->CR1 |= I2C_CR1_STOP;
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}
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/* Read data from DR */
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*dest++ = hi2c->Instance->DR;
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len--;
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/* Read data from DR */
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*dest++ = hi2c->Instance->DR;
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len--;
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}
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} else {
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/* Wait until RXNE flag is set */
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int ret = I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart);
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if (ret != 0) {
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return ret;
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}
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/* Read data from DR */
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*dest++ = hi2c->Instance->DR;
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len--;
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if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) {
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/* Read data from DR */
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*dest++ = hi2c->Instance->DR;
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len--;
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}
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}
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}
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return 0;
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}
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// this function is based on STM code
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int machine_hard_i2c_writeto(mp_obj_base_t *self_in, uint16_t addr, const uint8_t *src, size_t len, bool stop) {
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machine_hard_i2c_obj_t *self = (machine_hard_i2c_obj_t*)self_in;
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I2C_HandleTypeDef *hi2c = self->pyb->i2c;
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uint32_t Timeout = *self->timeout;
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/* Init tickstart for timeout management*/
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uint32_t tickstart = HAL_GetTick();
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#if 0
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// TODO: for multi-master, here we could wait for the bus to be free
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// we'd need a flag to tell if we were in the middle of a set of transactions
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// (ie didn't send a stop bit in the last call)
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/* Wait until BUSY flag is reset */
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if (!I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart)) {
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return -MP_EBUSY;
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}
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#endif
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/* Check if the I2C is already enabled */
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if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
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/* Enable I2C peripheral */
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__HAL_I2C_ENABLE(hi2c);
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}
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/* Disable Pos */
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hi2c->Instance->CR1 &= ~I2C_CR1_POS;
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/* Send Slave Address */
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int ret = send_addr_byte(hi2c, I2C_7BIT_ADD_WRITE(addr << 1), Timeout, tickstart);
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if (ret != 0) {
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return ret;
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}
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/* Clear ADDR flag */
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__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
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int num_acks = 0;
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while (len > 0U) {
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/* Wait until TXE flag is set */
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while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) {
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/* Check if a NACK is detected */
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if (I2C_IsAcknowledgeFailed(hi2c)) {
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goto nack;
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}
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/* Check for the Timeout */
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if (Timeout != HAL_MAX_DELAY) {
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if ((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) {
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goto timeout;
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}
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}
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}
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/* Write data to DR */
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hi2c->Instance->DR = *src++;
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len--;
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/* Wait until BTF flag is set */
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while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) {
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/* Check if a NACK is detected */
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if (I2C_IsAcknowledgeFailed(hi2c)) {
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goto nack;
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}
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/* Check for the Timeout */
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if (Timeout != HAL_MAX_DELAY) {
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if ((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) {
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goto timeout;
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}
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}
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}
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++num_acks;
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}
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nack:
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/* Generate Stop */
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if (stop) {
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hi2c->Instance->CR1 |= I2C_CR1_STOP;
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}
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return num_acks;
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timeout:
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// timeout, release the bus cleanly
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hi2c->Instance->CR1 |= I2C_CR1_STOP;
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return -MP_ETIMEDOUT;
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}
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#elif defined(STM32F7)
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#if defined(STM32F4) || defined(STM32F7)
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typedef struct _machine_hard_i2c_obj_t {
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mp_obj_base_t base;
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@ -450,6 +71,26 @@ STATIC const machine_hard_i2c_obj_t machine_hard_i2c_obj[] = {
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STATIC void machine_hard_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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machine_hard_i2c_obj_t *self = MP_OBJ_TO_PTR(self_in);
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#if defined(STM32F4)
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uint32_t freq = self->i2c->CR2 & 0x3f;
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uint32_t ccr = self->i2c->CCR;
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if (ccr & 0x8000) {
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// Fast mode, assume duty cycle of 16/9
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freq = freq * 40000 / (ccr & 0xfff);
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} else {
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// Standard mode
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freq = freq * 500000 / (ccr & 0xfff);
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}
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mp_printf(print, "I2C(%u, scl=%q, sda=%q, freq=%u)",
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self - &machine_hard_i2c_obj[0] + 1,
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mp_hal_pin_name(self->scl), mp_hal_pin_name(self->sda),
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freq);
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#else
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uint32_t timingr = self->i2c->TIMINGR;
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uint32_t presc = timingr >> 28;
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uint32_t sclh = timingr >> 8 & 0xff;
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@ -459,6 +100,8 @@ STATIC void machine_hard_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp
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self - &machine_hard_i2c_obj[0] + 1,
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mp_hal_pin_name(self->scl), mp_hal_pin_name(self->sda),
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freq, timingr);
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#endif
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}
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void machine_hard_i2c_init(machine_hard_i2c_obj_t *self, uint32_t freq, uint32_t timeout) {
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