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stm32/powerctrl: Optimise passing of default values to set_sysclk.

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This commit is contained in:
Damien George 2018-09-24 17:06:42 +10:00
parent dae1635c71
commit bc54c57590
2 changed files with 7 additions and 19 deletions
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6
ports/stm32/modmachine.c
View File

@ -298,9 +298,9 @@ STATIC mp_obj_t machine_freq(size_t n_args, const mp_obj_t *args) {
mp_raise_NotImplementedError("machine.freq set not supported yet");
#else
mp_int_t sysclk = mp_obj_get_int(args[0]);
mp_int_t ahb = 0;
mp_int_t apb1 = 0;
mp_int_t apb2 = 0;
mp_int_t ahb = sysclk;
mp_int_t apb1 = ahb / 4;
mp_int_t apb2 = ahb / 2;
if (n_args > 1) {
ahb = mp_obj_get_int(args[1]);
if (n_args > 2) {

20
ports/stm32/powerctrl.c
View File

@ -178,25 +178,13 @@ set_clk:
}
// Determine the bus clock dividers
if (ahb != 0) {
// Note: AHB freq required to be >= 14.2MHz for USB operation
RCC_ClkInitStruct.AHBCLKDivider = calc_ahb_div(sysclk / ahb);
} else {
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
}
// Note: AHB freq required to be >= 14.2MHz for USB operation
RCC_ClkInitStruct.AHBCLKDivider = calc_ahb_div(sysclk / ahb);
#if !defined(STM32H7)
ahb = sysclk >> AHBPrescTable[RCC_ClkInitStruct.AHBCLKDivider >> RCC_CFGR_HPRE_Pos];
#endif
if (apb1 != 0) {
RCC_ClkInitStruct.APB1CLKDivider = calc_apb_div(ahb / apb1);
} else {
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
}
if (apb2 != 0) {
RCC_ClkInitStruct.APB2CLKDivider = calc_apb_div(ahb / apb2);
} else {
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
}
RCC_ClkInitStruct.APB1CLKDivider = calc_apb_div(ahb / apb1);
RCC_ClkInitStruct.APB2CLKDivider = calc_apb_div(ahb / apb2);
#if MICROPY_HW_CLK_LAST_FREQ
// Save the bus dividers for use later