stm32/powerctrl: Move (deep)sleep funcs from modmachine.c to powerctrl.c
This commit is contained in:
Damien George
parent
3a723ad2fe
commit
66ca8e9b2c
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@ -324,131 +324,17 @@ STATIC mp_obj_t machine_freq(size_t n_args, const mp_obj_t *args) {
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MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_freq_obj, 0, 4, machine_freq);
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STATIC mp_obj_t machine_sleep(void) {
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#if defined(STM32L4)
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// Configure the MSI as the clock source after waking up
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__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI);
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#endif
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#if !defined(STM32F0) && !defined(STM32L4)
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// takes longer to wake but reduces stop current
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HAL_PWREx_EnableFlashPowerDown();
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#endif
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# if defined(STM32F7)
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HAL_PWR_EnterSTOPMode((PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS | PWR_CR1_UDEN), PWR_STOPENTRY_WFI);
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# else
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HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
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#endif
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// reconfigure the system clock after waking up
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#if defined(STM32F0)
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// Enable HSI48
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__HAL_RCC_HSI48_ENABLE();
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while (!__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY)) {
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}
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// Select HSI48 as system clock source
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_HSI48);
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI48) {
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}
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#else
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#if !defined(STM32L4)
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// enable HSE
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__HAL_RCC_HSE_CONFIG(MICROPY_HW_CLK_HSE_STATE);
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while (!__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY)) {
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}
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#endif
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// enable PLL
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__HAL_RCC_PLL_ENABLE();
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while (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)) {
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}
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// select PLL as system clock source
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK);
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#if defined(STM32H7)
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) {
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#else
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) {
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#endif
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}
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#if defined(STM32F7)
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if (RCC->DCKCFGR2 & RCC_DCKCFGR2_CK48MSEL) {
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// Enable PLLSAI if it is selected as 48MHz source
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RCC->CR |= RCC_CR_PLLSAION;
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while (!(RCC->CR & RCC_CR_PLLSAIRDY)) {
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}
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}
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#endif
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#if defined(STM32L4)
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// Enable PLLSAI1 for peripherals that use it
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RCC->CR |= RCC_CR_PLLSAI1ON;
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while (!(RCC->CR & RCC_CR_PLLSAI1RDY)) {
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}
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#endif
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#endif
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powerctrl_enter_stop_mode();
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_0(machine_sleep_obj, machine_sleep);
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STATIC mp_obj_t machine_deepsleep(void) {
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rtc_init_finalise();
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#if defined(STM32L4)
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#if defined(STM32L4)
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printf("machine.deepsleep not supported yet\n");
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#else
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// We need to clear the PWR wake-up-flag before entering standby, since
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// the flag may have been set by a previous wake-up event. Furthermore,
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// we need to disable the wake-up sources while clearing this flag, so
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// that if a source is active it does actually wake the device.
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// See section 5.3.7 of RM0090.
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// Note: we only support RTC ALRA, ALRB, WUT and TS.
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// TODO support TAMP and WKUP (PA0 external pin).
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#if defined(STM32F0)
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#define CR_BITS (RTC_CR_ALRAIE | RTC_CR_WUTIE | RTC_CR_TSIE)
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#define ISR_BITS (RTC_ISR_ALRAF | RTC_ISR_WUTF | RTC_ISR_TSF)
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#else
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#define CR_BITS (RTC_CR_ALRAIE | RTC_CR_ALRBIE | RTC_CR_WUTIE | RTC_CR_TSIE)
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#define ISR_BITS (RTC_ISR_ALRAF | RTC_ISR_ALRBF | RTC_ISR_WUTF | RTC_ISR_TSF)
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powerctrl_enter_standby_mode();
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#endif
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// save RTC interrupts
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uint32_t save_irq_bits = RTC->CR & CR_BITS;
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// disable RTC interrupts
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RTC->CR &= ~CR_BITS;
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// clear RTC wake-up flags
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RTC->ISR &= ~ISR_BITS;
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#if defined(STM32F7)
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// disable wake-up flags
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PWR->CSR2 &= ~(PWR_CSR2_EWUP6 | PWR_CSR2_EWUP5 | PWR_CSR2_EWUP4 | PWR_CSR2_EWUP3 | PWR_CSR2_EWUP2 | PWR_CSR2_EWUP1);
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// clear global wake-up flag
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PWR->CR2 |= PWR_CR2_CWUPF6 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF1;
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#elif defined(STM32H7)
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// TODO
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#else
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// clear global wake-up flag
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PWR->CR |= PWR_CR_CWUF;
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#endif
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// enable previously-enabled RTC interrupts
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RTC->CR |= save_irq_bits;
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// enter standby mode
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HAL_PWR_EnterSTANDBYMode();
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// we never return; MCU is reset on exit from standby
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#endif
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return mp_const_none;
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}
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MP_DEFINE_CONST_FUN_OBJ_0(machine_deepsleep_obj, machine_deepsleep);
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@ -27,6 +27,7 @@
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "powerctrl.h"
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#include "rtc.h"
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#include "genhdr/pllfreqtable.h"
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#if !defined(STM32F0)
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@ -257,3 +258,127 @@ set_clk:
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}
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#endif
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void powerctrl_enter_stop_mode(void) {
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#if defined(STM32L4)
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// Configure the MSI as the clock source after waking up
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__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI);
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#endif
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#if !defined(STM32F0) && !defined(STM32L4)
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// takes longer to wake but reduces stop current
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HAL_PWREx_EnableFlashPowerDown();
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#endif
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# if defined(STM32F7)
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HAL_PWR_EnterSTOPMode((PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS | PWR_CR1_UDEN), PWR_STOPENTRY_WFI);
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# else
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HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
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#endif
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// reconfigure the system clock after waking up
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#if defined(STM32F0)
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// Enable HSI48
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__HAL_RCC_HSI48_ENABLE();
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while (!__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY)) {
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}
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// Select HSI48 as system clock source
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_HSI48);
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI48) {
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}
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#else
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#if !defined(STM32L4)
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// enable HSE
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__HAL_RCC_HSE_CONFIG(MICROPY_HW_CLK_HSE_STATE);
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while (!__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY)) {
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}
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#endif
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// enable PLL
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__HAL_RCC_PLL_ENABLE();
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while (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)) {
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}
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// select PLL as system clock source
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK);
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#if defined(STM32H7)
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) {
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}
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#else
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) {
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}
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#endif
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#if defined(STM32F7)
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if (RCC->DCKCFGR2 & RCC_DCKCFGR2_CK48MSEL) {
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// Enable PLLSAI if it is selected as 48MHz source
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RCC->CR |= RCC_CR_PLLSAION;
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while (!(RCC->CR & RCC_CR_PLLSAIRDY)) {
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}
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}
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#endif
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#if defined(STM32L4)
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// Enable PLLSAI1 for peripherals that use it
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RCC->CR |= RCC_CR_PLLSAI1ON;
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while (!(RCC->CR & RCC_CR_PLLSAI1RDY)) {
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}
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#endif
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#endif
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}
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#if !defined(STM32L4)
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void powerctrl_enter_standby_mode(void) {
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rtc_init_finalise();
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// We need to clear the PWR wake-up-flag before entering standby, since
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// the flag may have been set by a previous wake-up event. Furthermore,
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// we need to disable the wake-up sources while clearing this flag, so
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// that if a source is active it does actually wake the device.
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// See section 5.3.7 of RM0090.
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// Note: we only support RTC ALRA, ALRB, WUT and TS.
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// TODO support TAMP and WKUP (PA0 external pin).
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#if defined(STM32F0)
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#define CR_BITS (RTC_CR_ALRAIE | RTC_CR_WUTIE | RTC_CR_TSIE)
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#define ISR_BITS (RTC_ISR_ALRAF | RTC_ISR_WUTF | RTC_ISR_TSF)
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#else
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#define CR_BITS (RTC_CR_ALRAIE | RTC_CR_ALRBIE | RTC_CR_WUTIE | RTC_CR_TSIE)
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#define ISR_BITS (RTC_ISR_ALRAF | RTC_ISR_ALRBF | RTC_ISR_WUTF | RTC_ISR_TSF)
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#endif
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// save RTC interrupts
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uint32_t save_irq_bits = RTC->CR & CR_BITS;
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// disable RTC interrupts
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RTC->CR &= ~CR_BITS;
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// clear RTC wake-up flags
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RTC->ISR &= ~ISR_BITS;
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#if defined(STM32F7)
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// disable wake-up flags
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PWR->CSR2 &= ~(PWR_CSR2_EWUP6 | PWR_CSR2_EWUP5 | PWR_CSR2_EWUP4 | PWR_CSR2_EWUP3 | PWR_CSR2_EWUP2 | PWR_CSR2_EWUP1);
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// clear global wake-up flag
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PWR->CR2 |= PWR_CR2_CWUPF6 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF1;
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#elif defined(STM32H7)
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// TODO
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#else
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// clear global wake-up flag
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PWR->CR |= PWR_CR_CWUF;
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#endif
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// enable previously-enabled RTC interrupts
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RTC->CR |= save_irq_bits;
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// enter standby mode
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HAL_PWR_EnterSTANDBYMode();
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// we never return; MCU is reset on exit from standby
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}
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#endif
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@ -30,5 +30,7 @@
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int powerctrl_rcc_clock_config_pll(RCC_ClkInitTypeDef *rcc_init, uint32_t sysclk_mhz, bool need_pllsai);
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int powerctrl_set_sysclk(uint32_t sysclk, uint32_t ahb, uint32_t apb1, uint32_t apb2);
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void powerctrl_enter_stop_mode(void);
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void powerctrl_enter_standby_mode(void);
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#endif // MICROPY_INCLUDED_STM32_POWERCTRL_H
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