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stm32: Add support for Cortex-M0 CPUs.

This commit is contained in:
Damien George 2018-05-28 11:23:33 +10:00
parent f497723802
commit 070937fe93
7 changed files with 183 additions and 0 deletions
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61
ports/stm32/gchelper_m0.s Normal file
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@ -0,0 +1,61 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2018 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
.syntax unified
.cpu cortex-m0
.thumb
.section .text
.align 2
.global gc_helper_get_regs_and_sp
.type gc_helper_get_regs_and_sp, %function
@ uint gc_helper_get_regs_and_sp(r0=uint regs[10])
gc_helper_get_regs_and_sp:
@ store registers into given array
str r4, [r0, #0]
str r5, [r0, #4]
str r6, [r0, #8]
str r7, [r0, #12]
mov r1, r8
str r1, [r0, #16]
mov r1, r9
str r1, [r0, #20]
mov r1, r10
str r1, [r0, #24]
mov r1, r11
str r1, [r0, #28]
mov r1, r12
str r1, [r0, #32]
mov r1, r13
str r1, [r0, #36]
@ return the sp
mov r0, sp
bx lr
.size gc_helper_get_regs_and_sp, .-gc_helper_get_regs_and_sp

20
ports/stm32/irq.h
View File

@ -102,6 +102,24 @@ MP_DECLARE_CONST_FUN_OBJ_0(pyb_irq_stats_obj);
// The following interrupts are arranged from highest priority to lowest
// priority to make it a bit easier to figure out.
#if __CORTEX_M == 0
//#def IRQ_PRI_SYSTICK 0
#define IRQ_PRI_UART 1
#define IRQ_PRI_FLASH 1
#define IRQ_PRI_SDIO 1
#define IRQ_PRI_DMA 1
#define IRQ_PRI_OTG_FS 2
#define IRQ_PRI_OTG_HS 2
#define IRQ_PRI_TIM5 2
#define IRQ_PRI_CAN 2
#define IRQ_PRI_TIMX 2
#define IRQ_PRI_EXTINT 2
#define IRQ_PRI_PENDSV 3
#define IRQ_PRI_RTC_WKUP 3
#else
//#def IRQ_PRI_SYSTICK NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 0, 0)
// The UARTs have no FIFOs, so if they don't get serviced quickly then characters
@ -135,4 +153,6 @@ MP_DECLARE_CONST_FUN_OBJ_0(pyb_irq_stats_obj);
#define IRQ_PRI_PENDSV NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0)
#define IRQ_PRI_RTC_WKUP NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0)
#endif
#endif // MICROPY_INCLUDED_STM32_IRQ_H

2
ports/stm32/main.c
View File

@ -458,8 +458,10 @@ void stm32_main(uint32_t reset_mode) {
#endif
#if __CORTEX_M >= 0x03
// Set the priority grouping
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
#endif
// SysTick is needed by HAL_RCC_ClockConfig (called in SystemClock_Config)
HAL_InitTick(TICK_INT_PRIORITY);

2
ports/stm32/mphalport.c
View File

@ -87,6 +87,7 @@ void mp_hal_stdout_tx_strn_cooked(const char *str, size_t len) {
}
}
#if __CORTEX_M >= 0x03
void mp_hal_ticks_cpu_enable(void) {
if (!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) {
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
@ -98,6 +99,7 @@ void mp_hal_ticks_cpu_enable(void) {
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
}
}
#endif
void mp_hal_gpio_clock_enable(GPIO_TypeDef *gpio) {
#if defined(STM32L476xx) || defined(STM32L496xx)

10
ports/stm32/mphalport.h
View File

@ -11,16 +11,26 @@ void mp_hal_set_interrupt_char(int c); // -1 to disable
#include "irq.h"
#if __CORTEX_M == 0
// Don't have raise_irq_pri on Cortex-M0 so keep IRQs enabled to have SysTick timing
#define mp_hal_quiet_timing_enter() (1)
#define mp_hal_quiet_timing_exit(irq_state) (void)(irq_state)
#else
#define mp_hal_quiet_timing_enter() raise_irq_pri(1)
#define mp_hal_quiet_timing_exit(irq_state) restore_irq_pri(irq_state)
#endif
#define mp_hal_delay_us_fast(us) mp_hal_delay_us(us)
void mp_hal_ticks_cpu_enable(void);
static inline mp_uint_t mp_hal_ticks_cpu(void) {
#if __CORTEX_M == 0
return 0;
#else
if (!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) {
mp_hal_ticks_cpu_enable();
}
return DWT->CYCCNT;
#endif
}
// C-level pin HAL

74
ports/stm32/resethandler_m0.s Normal file
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@ -0,0 +1,74 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2018 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
.syntax unified
.cpu cortex-m0
.thumb
.section .text.Reset_Handler
.global Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Save the first argument to pass through to stm32_main */
mov r4, r0
/* Load the stack pointer */
ldr r0, =_estack
mov sp, r0
/* Initialise the data section */
ldr r1, =_sidata
ldr r2, =_sdata
ldr r3, =_edata
b .data_copy_entry
.data_copy_loop:
ldr r0, [r1]
adds r1, #4
str r0, [r2]
adds r2, #4
.data_copy_entry:
cmp r2, r3
bcc .data_copy_loop
/* Zero out the BSS section */
movs r0, #0
ldr r1, =_sbss
ldr r2, =_ebss
b .bss_zero_entry
.bss_zero_loop:
str r0, [r1]
adds r1, #4
.bss_zero_entry:
cmp r1, r2
bcc .bss_zero_loop
/* Initialise the system and jump to the main code */
bl SystemInit
mov r0, r4
bl stm32_main
.size Reset_Handler, .-Reset_Handler

14
ports/stm32/stm32_it.c
View File

@ -165,6 +165,7 @@ void HardFault_C_Handler(ExceptionRegisters_t *regs) {
print_reg("PC ", regs->pc);
print_reg("XPSR ", regs->xpsr);
#if __CORTEX_M >= 3
uint32_t cfsr = SCB->CFSR;
print_reg("HFSR ", SCB->HFSR);
@ -175,6 +176,7 @@ void HardFault_C_Handler(ExceptionRegisters_t *regs) {
if (cfsr & 0x8000) {
print_reg("BFAR ", SCB->BFAR);
}
#endif
if ((void*)&_ram_start <= (void*)regs && (void*)regs < (void*)&_ram_end) {
mp_hal_stdout_tx_str("Stack:\r\n");
@ -207,6 +209,17 @@ void HardFault_Handler(void) {
// main stack pointer (aka MSP). If CONTROL.SPSEL is 1, then the exception
// was stacked up using the process stack pointer (aka PSP).
#if __CORTEX_M == 0
__asm volatile(
" mov r0, lr \n"
" lsr r0, r0, #3 \n" // Shift Bit 3 into carry to see which stack pointer we should use.
" mrs r0, msp \n" // Make R0 point to main stack pointer
" bcc .use_msp \n" // Keep MSP in R0 if SPSEL (carry) is 0
" mrs r0, psp \n" // Make R0 point to process stack pointer
" .use_msp: \n"
" b HardFault_C_Handler \n" // Off to C land
);
#else
__asm volatile(
" tst lr, #4 \n" // Test Bit 3 to see which stack pointer we should use.
" ite eq \n" // Tell the assembler that the nest 2 instructions are if-then-else
@ -214,6 +227,7 @@ void HardFault_Handler(void) {
" mrsne r0, psp \n" // Make R0 point to process stack pointer
" b HardFault_C_Handler \n" // Off to C land
);
#endif
}
/**