The following error occurs when building with gcc 5.4.1 (debian stretch):
common-hal/busio/UART.c:104:83: error: 'sercom_index' may be used uninitialized in this function [-Werror=maybe-uninitialized]
sercom_insts[rx->sercom[j].index]->USART.CTRLA.bit.ENABLE == 0) ||
It may be related to the addition of rx-only UARTs; gcc is unable
to infer the intended relationship between have_tx and sercom_index
being set (I am still not entirely confident of it myself)
Having the `active_read = false` in the background function left
a chance that a new_write occurs before active_read is set to false.
In that case, we'll read the appropriate data rather than write it
and never clear the active write.
Hopefully fixes#655.
1. UART: ported to ASF4. Allow rx-only and tx-only. Add .baudrate r/w property.
2. Make NeoPixel timing deterministic by turning off caches during NeoPixel writes.
3. Incorporate asf4 updates:
a. async USART driver
b. bringing Atmel START configuration closer to what we use
c. Clock initialization order now specified by CIRCUITPY_GCLK_INIT_1ST and _LAST.
4. supervisor/port.c: Move commented-out clock-test pin setting to correct location.
This introduces a new spi_flash_api.h that works for both SPI and
QSPI. The previous spi_flash functions are now called external_flash
to minimize confusion.
1. Make _extext and _sidata coincide. Old _etext location did not include
.ARM.exidx sections, which were usually absent but not always. So flash
data was copied to RAM in wrong place.
2. Use decimal constants with "K" and "M" suffixes in .ld files instead
of hex constants, to make them easier to read and check for accuracy.
all: Add .frequency read-only property for busio.SPI to return actual frequency.
Fix esp8266/posix_helpers.c, which was not up to date for the new
long-lived/short-lived heap allocation scheme.
There have been multiple uGame prototypes with differences in the pins
and other details. This updates the board definition to fit the final
uGame 10 design.
shared_bindings/index.rst: updated Support Matrix format as discussed in PR #503 & Issue #448.
shared-bindings/microcontroller/Processor.c & .h: added UID lookup functionality for use with all ports. Fixes#462.
1. Turn off MICROPY_CPYTHON_COMPAT, which includes a number of minor CPython compatibility features,
most of which have workarounds, but uses up significant flash.
2. Turn on MICROPY_PY_SYS_MAXSIZE, which implements sys.maxsize.
3. Turn on MICROPY_CAN_OVERRIDE_BUILTINS, which implements "_" as the most recent value in the REPL,
and also enables redefining builtins.
- Added D4 and moved associated SD_CS so that they are paired within list
- Added D7 and SD_CD which is the SD Card Detect pin
- Added D8 and GREEN_LED
- Added RED_LED associated with D13
- Added Setup information regarding arm complier packages
- README - Updated to reflect that feather_m0_adalogger microSD is supported
- Added D4 and moved associated SD_CS so that they are paired within list
- Added D7 and SD_CD which is the SD Card Detect pin
- Added D8 and GREEN_LED
- Added RED_LED associated with D13
Also, fixed pin mappings for rev B Metro M4:
swap PA12 and PA13 on SPI 2x3 header
swap A3 and A5
Comment out all frozen modules in CPX again to make room while waiting
for SPI flash.
* Be more liberal with critical sections to ensure ordering.
* Correct usb_busy so that it is busy when no errors occur on
transfer. I believe it worked before because it would be false
momentarily until a second transfer was attempted and a busy
error was returned, therefore setting usb_busy to true. That
risks the first "failed" transfer completing before a second one
is attempted.
* Added asf4_conf/samd*/hpl_sercom_config.h
* Adjusted clocks in peripheral_clk_config.h.
* Put some frozen libs back in CPX for testing.
* Implement common-hal I2C
* Add samd*_peripherals.h in parallel with samd*_pins.h for common
functions and data.
* Store SERCOM index in pins table for convenience.
* Canonicalize some #include guard names in various .h files.
simpler reset of SERCOMs; remove unused routine
This explicit zero length xfer leads to a second CSW packet. If
another read was started between the two CSWs then the host gets
confused and resets the device.
On reads, the CSW is automatically sent when we reply with the
total length. Writes must do it manually so they can wait for the
disk to flush the data.
