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non-DMA SPI working; adding this now for testing; will continue with DMA 

Also, fixed pin mappings for rev B Metro M4:
swap PA12 and PA13 on SPI 2x3 header
swap A3 and A5

Comment out all frozen modules in CPX again to make room while waiting
for SPI flash.
This commit is contained in:
Dan Halbert 2017-11-14 20:00:29 -05:00
parent 9564f7b90e
commit 312444bbd2
18 changed files with 1613 additions and 1931 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
ports/atmel-samd/Makefile
View File

@ -172,6 +172,7 @@ SRC_ASF := \
hal/src/hal_i2c_m_sync.c \
hal/src/hal_io.c \
hal/src/hal_sleep.c \
hal/src/hal_spi_m_sync.c \
hal/src/hal_timer.c \
hal/src/hal_usb_device.c \
hpl/core/hpl_init.c \
@ -252,6 +253,7 @@ SRC_COMMON_HAL = \
board/__init__.c \
busio/__init__.c \
busio/I2C.c \
busio/SPI.c \
digitalio/__init__.c \
digitalio/DigitalInOut.c \
microcontroller/__init__.c \
@ -267,7 +269,6 @@ SRC_COMMON_HAL = \
audiobusio/PDMIn.c \
audioio/__init__.c \
audioio/AudioOut.c \
busio/SPI.c \
busio/UART.c \
neopixel_write/__init__.c \
nvm/__init__.c \

2
ports/atmel-samd/asf4

@ -1 +1 @@
Subproject commit 7ffa51e117eb6d6b6679febfc77e50d03731b467
Subproject commit 72f76894ba08c9de2ec3ae231fb71daaf3eafb1e

928
ports/atmel-samd/asf4_conf/samd21/hpl_sercom_config.h
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File diff suppressed because it is too large Load Diff

4
ports/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h
View File

@ -1,7 +1,3 @@
// Derived from:
// Create START project with using six I2C, then six ...
// then merge all.
/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H

1374
ports/atmel-samd/asf4_conf/samd51/hpl_sercom_config.h
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File diff suppressed because it is too large Load Diff

913
ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h
View File

@ -1,113 +1,926 @@
// Derived from: Auto-generated config file peripheral_clk_config.h
// Boilerplate removed.
/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H
// ADC
// <<< Use Configuration Wizard in Context Menu >>>
// <y> ADC Clock Source
// <id> adc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for ADC.
#ifndef CONF_GCLK_ADC0_SRC
#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_ADC0_FREQUENCY 120000000
#endif
// DAC
/**
* \def CONF_GCLK_ADC0_FREQUENCY
* \brief ADC0's Clock frequency
*/
#ifndef CONF_GCLK_ADC0_FREQUENCY
#define CONF_GCLK_ADC0_FREQUENCY 12000000
#endif
// <y> DAC Clock Source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <id> dac_gclk_selection
// <i> Select the clock source for DAC.
#ifndef CONF_GCLK_DAC_SRC
#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_DAC_FREQUENCY 120000000
#endif
// EVSYS
/**
* \def CONF_GCLK_DAC_FREQUENCY
* \brief DAC's Clock frequency
*/
#ifndef CONF_GCLK_DAC_FREQUENCY
#define CONF_GCLK_DAC_FREQUENCY 12000000
#endif
// <y> EVSYS Channel 0 Clock Source
// <id> evsys_clk_selection_0
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 0.
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC
#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 1 Clock Source
// <id> evsys_clk_selection_1
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 1.
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC
#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 2 Clock Source
// <id> evsys_clk_selection_2
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 2.
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC
#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 3 Clock Source
// <id> evsys_clk_selection_3
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 3.
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC
#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 4 Clock Source
// <id> evsys_clk_selection_4
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 4.
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC
#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 5 Clock Source
// <id> evsys_clk_selection_5
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 5.
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC
#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 6 Clock Source
// <id> evsys_clk_selection_6
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 6.
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC
#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 7 Clock Source
// <id> evsys_clk_selection_7
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 7.
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC
#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 8 Clock Source
// <id> evsys_clk_selection_8
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 8.
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC
#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 9 Clock Source
// <id> evsys_clk_selection_9
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 9.
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC
#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 10 Clock Source
// <id> evsys_clk_selection_10
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 10.
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC
#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000.0
#endif
/**
* \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
* \brief EVSYS's Clock frequency
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 12000000.0
#endif
// <y> EVSYS Channel 11 Clock Source
// <id> evsys_clk_selection_11
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for channel 11.
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC
#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000.0
#endif
// CPU: 120 MHz
#define CONF_CPU_FREQUENCY 120000000
/**
* \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
* \brief EVSYS's Clock frequency
*/
// RTC
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 12000000.0
#endif
/**
* \def CONF_CPU_FREQUENCY
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 12000000
#endif
// <y> RTC Clock Source
// <id> rtc_clk_selection
// <RTC_CLOCK_SOURCE"> RTC source
// <i> Select the clock source for RTC.
#ifndef CONF_GCLK_RTC_SRC
#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
#endif
/**
* \def CONF_GCLK_RTC_FREQUENCY
* \brief RTC's Clock frequency
*/
#ifndef CONF_GCLK_RTC_FREQUENCY
#define CONF_GCLK_RTC_FREQUENCY 1024
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// SERCOM
// Use 48 MHz clock for CORE, and 32kHz clock for SLOW.
// 120 MHz is too fast for CORE.
// Slow is only needed for SMBus, it appears.
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM0_CORE_SRC
#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
* \brief SERCOM0's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000
#endif
/**
* \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
* \brief SERCOM0's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM1_CORE_SRC
#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
* \brief SERCOM1's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000
#endif
/**
* \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
* \brief SERCOM1's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM2_CORE_SRC
#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000
#endif
/**
* \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
* \brief SERCOM2's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
#endif
#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
// <y> TC Clock Source
// <id> tc_gclk_selection
#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
#define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 32768
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// TC
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC0_SRC
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_TC0_FREQUENCY 12000000
#endif
// USB
/**
* \def CONF_GCLK_TC0_FREQUENCY
* \brief TC0's Clock frequency
*/
#ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 12000000
#endif
// <y> USB Clock Source
// <id> usb_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
// <i> Select the clock source for USB.
#ifndef CONF_GCLK_USB_SRC
#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#endif
/**
* \def CONF_GCLK_USB_FREQUENCY
* \brief USB's Clock frequency
*/
#ifndef CONF_GCLK_USB_FREQUENCY
#define CONF_GCLK_USB_FREQUENCY 48000000
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H

6
ports/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk
View File

@ -13,7 +13,7 @@ CHIP_FAMILY = samd21
# Include these Python libraries in firmware.
### TODO(halbert): disable some of these frozen modules; they don't fit in 3.0.0 build while internalfs
### is in use
FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_BusDevice
FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_LIS3DH
FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel
###FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_BusDevice
###FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_LIS3DH
###FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel
###FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_Thermistor

8
ports/atmel-samd/boards/metro_m4_express/pins.c
View File

@ -7,9 +7,9 @@ STATIC const mp_map_elem_t board_global_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_A0), (mp_obj_t)&pin_PA02 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A1), (mp_obj_t)&pin_PA05 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A2), (mp_obj_t)&pin_PA06 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A3), (mp_obj_t)&pin_PA07 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A3), (mp_obj_t)&pin_PA04 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), (mp_obj_t)&pin_PA11 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), (mp_obj_t)&pin_PA04 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), (mp_obj_t)&pin_PA07 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D0), (mp_obj_t)&pin_PA23 },
@ -32,8 +32,8 @@ STATIC const mp_map_elem_t board_global_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), (mp_obj_t)&pin_PB17 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCK), (mp_obj_t)&pin_PA12 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), (mp_obj_t)&pin_PA13 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCK), (mp_obj_t)&pin_PA13 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), (mp_obj_t)&pin_PA12 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_MISO), (mp_obj_t)&pin_PA15 },
{ MP_OBJ_NEW_QSTR(MP_QSTR_LED_RX), (mp_obj_t)&pin_PB06 },

2
ports/atmel-samd/common-hal/busio/I2C.c
View File

@ -72,7 +72,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self,
// Set up I2C clocks on sercom.
sercom_clock_init(sercom, sercom_index);
samd_peripheral_sercom_clock_init(sercom, sercom_index);
if (i2c_m_sync_init(&self->i2c_desc, sercom) != ERR_NONE) {
mp_raise_OSError(MP_EIO);

216
ports/atmel-samd/common-hal/busio/SPI.c
View File

@ -25,25 +25,35 @@
*/
#include "shared-bindings/busio/SPI.h"
#include "py/nlr.h"
#include "py/mperrno.h"
#include "py/runtime.h"
#include "rgb_led_status.h"
#include "samd21_pins.h"
#include "hpl_sercom_config.h"
#include "peripheral_clk_config.h"
#include "hal/include/hal_gpio.h"
#include "hal/include/hal_spi_m_sync.h"
#include "hal/include/hpl_spi_m_sync.h"
#include "peripherals.h"
#include "pins.h"
#include "shared_dma.h"
// We use ENABLE registers below we don't want to treat as a macro.
#undef ENABLE
// Number of times to try to send packet if failed.
#define TIMEOUT 1
// Convert frequency to clock-speed-dependent value. Return 0 if out of range.
static uint8_t baudrate_to_baud_reg_value(const uint32_t baudrate) {
uint32_t baud_reg_value = (uint32_t) (((float) PROTOTYPE_SERCOM_SPI_M_SYNC_CLOCK_FREQUENCY /
(2 * baudrate)) + 0.5f);
if (baud_reg_value > 0xff) {
return 0;
}
return (uint8_t) baud_reg_value;
}
void common_hal_busio_spi_construct(busio_spi_obj_t *self,
const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi,
const mcu_pin_obj_t * miso) {
struct spi_config config_spi_master;
spi_get_config_defaults(&config_spi_master);
Sercom* sercom = NULL;
uint8_t sercom_index;
uint32_t clock_pinmux = 0;
bool mosi_none = mosi == mp_const_none;
bool miso_none = miso == mp_const_none;
@ -52,8 +62,10 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
uint8_t clock_pad = 0;
uint8_t mosi_pad = 0;
uint8_t miso_pad = 0;
uint8_t dopo = 255;
for (int i = 0; i < NUM_SERCOMS_PER_PIN; i++) {
Sercom* potential_sercom = clock->sercom[i].sercom;
sercom_index = clock->sercom[i].index; // 2 for SERCOM2, etc.
if (potential_sercom == NULL ||
#if defined(MICROPY_HW_APA102_SCK) && defined(MICROPY_HW_APA102_MOSI) && !defined(CIRCUITPY_BITBANG_APA102)
(potential_sercom->SPI.CTRLA.bit.ENABLE != 0 &&
@ -66,11 +78,18 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
}
clock_pinmux = PINMUX(clock->pin, (i == 0) ? MUX_C : MUX_D);
clock_pad = clock->sercom[i].pad;
if (!samd_peripheral_valid_spi_clock_pad(clock_pad)) {
continue;
}
for (int j = 0; j < NUM_SERCOMS_PER_PIN; j++) {
if (!mosi_none) {
if(potential_sercom == mosi->sercom[j].sercom) {
mosi_pinmux = PINMUX(mosi->pin, (j == 0) ? MUX_C : MUX_D);
mosi_pad = mosi->sercom[j].pad;
dopo = samd_peripheral_get_spi_dopo(clock_pad, mosi_pad);
if (dopo > 0x3) {
continue; // pad combination not possible
}
if (miso_none) {
sercom = potential_sercom;
break;
@ -101,62 +120,52 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
mp_raise_ValueError("Invalid pins");
}
// Depends on where MOSI and CLK are.
uint8_t dopo = 8;
if (clock_pad == 1) {
if (mosi_pad == 0) {
dopo = 0;
} else if (mosi_pad == 3) {
dopo = 2;
}
} else if (clock_pad == 3) {
if (mosi_pad == 0) {
dopo = 3;
} else if (mosi_pad == 2) {
dopo = 1;
}
}
if (dopo == 8) {
mp_raise_ValueError("MOSI and clock pins incompatible");
// Set up SPI clocks on SERCOM.
samd_peripheral_sercom_clock_init(sercom, sercom_index);
if (spi_m_sync_init(&self->spi_desc, sercom) != ERR_NONE) {
mp_raise_OSError(MP_EIO);
}
hri_sercomspi_write_CTRLA_DOPO_bf(sercom, dopo);
hri_sercomspi_write_CTRLA_DIPO_bf(sercom, miso_pad);
config_spi_master.mux_setting = (dopo << SERCOM_SPI_CTRLA_DOPO_Pos) |
(miso_pad << SERCOM_SPI_CTRLA_DIPO_Pos);
// Map pad to pinmux through a short array.
uint32_t *pinmuxes[4] = {&config_spi_master.pinmux_pad0,
&config_spi_master.pinmux_pad1,
&config_spi_master.pinmux_pad2,
&config_spi_master.pinmux_pad3};
// Set other pinmuxes to unused so we don't accidentally change other pin
// state.
for (uint8_t i = 0; i < 4; i++) {
*pinmuxes[i] = PINMUX_UNUSED;
// Always start at 250khz which is what SD cards need. They are sensitive to
// SPI bus noise before they are put into SPI mode.
uint8_t baud_value = baudrate_to_baud_reg_value(250000);
if (baud_value == 0) {
mp_raise_RuntimeError("SPI initial baudrate out of range.");
}
*pinmuxes[clock_pad] = clock_pinmux;
self->clock_pin = clock->pin;
if (spi_m_sync_set_baudrate(&self->spi_desc, baud_value) != ERR_NONE) {
// spi_m_sync_set_baudrate does not check for validity, just whether the device is
// busy or not
mp_raise_OSError(MP_EIO);
}
gpio_set_pin_pull_mode(clock->pin, GPIO_PULL_OFF);
gpio_set_pin_function(clock->pin, clock_pinmux);
claim_pin(clock);
self->MOSI_pin = NO_PIN;
if (!mosi_none) {
*pinmuxes[mosi_pad] = mosi_pinmux;
self->clock_pin = clock->pin;
if (mosi_none) {
self->MOSI_pin = NO_PIN;
} else {
gpio_set_pin_pull_mode(mosi->pin, GPIO_PULL_OFF);
gpio_set_pin_function(mosi->pin, mosi_pinmux);
self->MOSI_pin = mosi->pin;
claim_pin(mosi);
}
self->MISO_pin = NO_PIN;
if (!miso_none) {
*pinmuxes[miso_pad] = miso_pinmux;
if (miso_none) {
self->MISO_pin = NO_PIN;
} else {
gpio_set_pin_pull_mode(miso->pin, GPIO_PULL_OFF);
gpio_set_pin_function(miso->pin, miso_pinmux);
self->MISO_pin = miso->pin;
claim_pin(miso);
}
// Always start at 250khz which is what SD cards need. They are sensitive to
// SPI bus noise before they are put into SPI mode.
self->current_baudrate = 250000;
config_spi_master.mode_specific.master.baudrate = self->current_baudrate;
spi_init(&self->spi_master_instance, sercom, &config_spi_master);
spi_enable(&self->spi_master_instance);
spi_m_sync_enable(&self->spi_desc);
}
bool common_hal_busio_spi_deinited(busio_spi_obj_t *self) {
@ -167,7 +176,8 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
if (common_hal_busio_spi_deinited(self)) {
return;
}
spi_disable(&self->spi_master_instance);
spi_m_sync_disable(&self->spi_desc);
spi_m_sync_deinit(&self->spi_desc);
reset_pin(self->clock_pin);
reset_pin(self->MOSI_pin);
reset_pin(self->MISO_pin);
@ -176,49 +186,45 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
// TODO(tannewt): Check baudrate first before changing it.
if (baudrate != self->current_baudrate) {
enum status_code status = spi_set_baudrate(&self->spi_master_instance, baudrate);
if (status != STATUS_OK) {
return false;
}
self->current_baudrate = baudrate;
uint8_t baud_reg_value = baudrate_to_baud_reg_value(baudrate);
if (baud_reg_value == 0) {
mp_raise_ValueError("baudrate out of range");
}
SercomSpi *const spi_module = &(self->spi_master_instance.hw->SPI);
void * hw = self->spi_desc.dev.prvt;
// If the settings are already what we want then don't reset them.
if (spi_module->CTRLA.bit.CPHA == phase &&
spi_module->CTRLA.bit.CPOL == polarity &&
spi_module->CTRLB.bit.CHSIZE == (bits - 8)) {
if (hri_sercomspi_get_CTRLA_CPHA_bit(hw) == phase &&
hri_sercomspi_get_CTRLA_CPOL_bit(hw) == polarity &&
hri_sercomspi_read_CTRLB_CHSIZE_bf(hw) == ((uint32_t)bits - 8) &&
hri_sercomspi_read_BAUD_BAUD_bf(hw) == baud_reg_value) {
return true;
}
spi_disable(&self->spi_master_instance);
while (spi_is_syncing(&self->spi_master_instance)) {
/* Wait until the synchronization is complete */
}
// Disable, set values (most or all are enable-protected), and re-enable.
spi_m_sync_disable(&self->spi_desc);
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
spi_module->CTRLA.bit.CPHA = phase;
spi_module->CTRLA.bit.CPOL = polarity;
spi_module->CTRLB.bit.CHSIZE = bits - 8;
hri_sercomspi_write_CTRLA_CPHA_bit(hw, phase);
hri_sercomspi_write_CTRLA_CPOL_bit(hw, polarity);
hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, bits - 8);
hri_sercomspi_write_BAUD_BAUD_bf(hw, baud_reg_value);
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
while (spi_is_syncing(&self->spi_master_instance)) {
/* Wait until the synchronization is complete */
}
/* Enable the module */
spi_enable(&self->spi_master_instance);
while (spi_is_syncing(&self->spi_master_instance)) {
/* Wait until the synchronization is complete */
}
spi_m_sync_enable(&self->spi_desc);
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
return true;
}
bool common_hal_busio_spi_try_lock(busio_spi_obj_t *self) {
self->has_lock = spi_lock(&self->spi_master_instance) == STATUS_OK;
return self->has_lock;
bool grabbed_lock = false;
CRITICAL_SECTION_ENTER()
if (!self->has_lock) {
grabbed_lock = true;
self->has_lock = true;
}
CRITICAL_SECTION_LEAVE();
return grabbed_lock;
}
bool common_hal_busio_spi_has_lock(busio_spi_obj_t *self) {
@ -227,7 +233,6 @@ bool common_hal_busio_spi_has_lock(busio_spi_obj_t *self) {
void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
self->has_lock = false;
spi_unlock(&self->spi_master_instance);
}
bool common_hal_busio_spi_write(busio_spi_obj_t *self,
@ -235,13 +240,15 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self,
if (len == 0) {
return true;
}
enum status_code status;
if (len >= 16) {
status = shared_dma_write(self->spi_master_instance.hw, data, len);
} else {
status = spi_write_buffer_wait(&self->spi_master_instance, data, len);
}
return status == STATUS_OK;
int32_t status;
// if (len >= 16) {
// status = shared_dma_write(self->spi_desc.dev.prvt, data, len);
// } else {
struct io_descriptor *spi_io;
spi_m_sync_get_io_descriptor(&self->spi_desc, &spi_io);
status = spi_io->write(spi_io, data, len);
// }
return status > 0; // Status is number of chars read or an error code < 0.
}
bool common_hal_busio_spi_read(busio_spi_obj_t *self,
@ -249,11 +256,16 @@ bool common_hal_busio_spi_read(busio_spi_obj_t *self,
if (len == 0) {
return true;
}
enum status_code status;
if (len >= 16) {
status = shared_dma_read(self->spi_master_instance.hw, data, len, write_value);
} else {
status = spi_read_buffer_wait(&self->spi_master_instance, data, len, write_value);
}
return status == STATUS_OK;
int32_t status;
// if (len >= 16) {
// status = shared_dma_read(self->spi_desc.dev.prvt, data, len, write_value);
// } else {
self->spi_desc.dev.dummy_byte = write_value;
struct io_descriptor *spi_io;
spi_m_sync_get_io_descriptor(&self->spi_desc, &spi_io);
status = spi_io->read(spi_io, data, len);
// }
return status > 0; // Status is number of chars read or an error code < 0.
}

6
ports/atmel-samd/common-hal/busio/SPI.h
View File

@ -29,17 +29,17 @@
#include "common-hal/microcontroller/Pin.h"
#include "asf/sam0/drivers/sercom/spi/spi.h"
#include "hal/include/hal_spi_m_sync.h"
#include "py/obj.h"
typedef struct {
mp_obj_base_t base;
struct spi_module spi_master_instance;
struct spi_m_sync_descriptor spi_desc;
bool has_lock;
uint8_t clock_pin;
uint8_t MOSI_pin;
uint8_t MISO_pin;
uint32_t current_baudrate;
} busio_spi_obj_t;
#endif // MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_BUSIO_SPI_H

29
ports/atmel-samd/samd21_peripherals.c
View File

@ -58,8 +58,35 @@ static const uint8_t SERCOMx_GCLK_ID_SLOW[] = {
// Clock initialization as done in Atmel START.
void sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
void samd_peripheral_sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
_pm_enable_bus_clock(PM_BUS_APBC, sercom);
_gclk_enable_channel(SERCOMx_GCLK_ID_CORE[sercom_index], GCLK_CLKCTRL_GEN_GCLK0_Val);
_gclk_enable_channel(SERCOMx_GCLK_ID_SLOW[sercom_index], GCLK_CLKCTRL_GEN_GCLK3_Val);
}
// Figure out the DOPO value given the chosen clock pad and mosi pad.
// Return an out-of-range value (255) if the combination is not permitted.
// <0x0=>PAD[0,1]_DO_SCK
// <0x1=>PAD[2,3]_DO_SCK
// <0x2=>PAD[3,1]_DO_SCK
// <0x3=>PAD[0,3]_DO_SCK
uint8_t samd_peripheral_get_spi_dopo(uint8_t clock_pad, uint8_t mosi_pad) {
if (clock_pad == 1) {
if (mosi_pad == 0) {
return 0;
} else if (mosi_pad == 3) {
return 2;
}
} else if (clock_pad == 3) {
if (mosi_pad == 0) {
return 3;
} else if (mosi_pad == 2) {
return 1;
}
}
return 255;
}
bool samd_peripheral_valid_spi_clock_pad(uint8_t clock_pad) {
return clock_pad == 1 || clock_pad == 3;
}

4
ports/atmel-samd/samd21_peripherals.h
View File

@ -29,6 +29,8 @@
#include "include/sam.h"
void sercom_clock_init(Sercom* sercom, uint8_t sercom_index);
void samd_peripheral_sercom_clock_init(Sercom* sercom, uint8_t sercom_index);
uint8_t samd_peripheral_get_spi_dopo(uint8_t clock_pad, uint8_t mosi_pad);
bool samd_peripheral_valid_spi_clock_pad(uint8_t clock_pad);
#endif // MICROPY_INCLUDED_ATMEL_SAMD_SAMD21_PERIPHERALS_H

29
ports/atmel-samd/samd51_peripherals.c
View File

@ -62,7 +62,7 @@ static const uint8_t SERCOMx_GCLK_ID_SLOW[] = {
// Clock initialization as done in Atmel START.
void sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
void samd_peripheral_sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
hri_gclk_write_PCHCTRL_reg(GCLK,
SERCOMx_GCLK_ID_CORE[sercom_index],
GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos));
@ -102,3 +102,30 @@ void sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
#endif
}
}
// Figure out the DOPO value given the chosen clock pad and mosi pad.
// Return an out-of-range value (255) if the combination is not permitted
// The ASF4 config files list this, but the SAMD51 datasheet
// says 0x1 and 0x3 are reserved, so don't allow pad 3 SCK.
// Transmit Data Pinout
// <0x0=>PAD[0,1]_DO_SCK
// <0x1=>PAD[2,3]_DO_SCK [RESERVED]
// <0x2=>PAD[3,1]_DO_SCK
// <0x3=>PAD[0,3]_DO_SCK [RESERVED]
uint8_t samd_peripheral_get_spi_dopo(uint8_t clock_pad, uint8_t mosi_pad) {
if (clock_pad != 1) {
return 255;
}
if (mosi_pad == 0) {
return 0x1;
}
if (mosi_pad == 3) {
return 0x2;
}
return 255;
}
bool samd_peripheral_valid_spi_clock_pad(uint8_t clock_pad) {
return clock_pad == 1;
}

4
ports/atmel-samd/samd51_peripherals.h
View File

@ -29,7 +29,9 @@
#include "sam.h"
void sercom_clock_init(Sercom* sercom, uint8_t sercom_index);
void samd_peripheral_sercom_clock_init(Sercom* sercom, uint8_t sercom_index);
uint8_t samd_peripheral_get_spi_dopo(uint8_t clock_pad, uint8_t mosi_pad);
bool samd_peripheral_valid_spi_clock_pad(uint8_t clock_pad);
#endif // MICROPY_INCLUDED_ATMEL_SAMD_SAMD51_PERIPHERALS_H

8
ports/atmel-samd/shared_dma.c
View File

@ -95,7 +95,7 @@ static void dma_configure(uint8_t channel, uint8_t trigsrc, bool output_event) {
system_interrupt_leave_critical_section();
}
enum status_code shared_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_t length) {
int32_t shared_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_t length) {
if (general_dma_tx.job_status != STATUS_OK) {
return general_dma_tx.job_status;
}
@ -113,7 +113,7 @@ enum status_code shared_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_
dma_descriptor_create(general_dma_tx.descriptor, &descriptor_config);
enum status_code status = dma_start_transfer_job(&general_dma_tx);
if (status != STATUS_OK) {
if (status != ERR_NONE) {
return status;
}
@ -134,8 +134,8 @@ enum status_code shared_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_
return general_dma_tx.job_status;
}
enum status_code shared_dma_read(Sercom* sercom, uint8_t* buffer, uint32_t length, uint8_t tx) {
if (general_dma_tx.job_status != STATUS_OK) {
int32_t shared_dma_read(Sercom* sercom, uint8_t* buffer, uint32_t length, uint8_t tx) {
if (general_dma_tx.job_status != ERR_NONE) {
return general_dma_tx.job_status;
}

4
py/mkrules.mk
View File

@ -183,4 +183,8 @@ print-def:
@$(CC) -E -Wp,-dM __empty__.c
@$(RM) -f __empty__.c
tags:
ctags -e -R $(TOP)
-include $(OBJ:.o=.P)

4
shared-bindings/busio/__init__.c
View File

@ -33,7 +33,7 @@
#include "shared-bindings/busio/__init__.h"
#include "shared-bindings/busio/I2C.h"
//xxxx #include "shared-bindings/busio/OneWire.h"
//xxxx #include "shared-bindings/busio/SPI.h"
#include "shared-bindings/busio/SPI.h"
//xxxx #include "shared-bindings/busio/UART.h"
#include "shared-bindings/busio/__init__.h"
@ -88,8 +88,8 @@
STATIC const mp_rom_map_elem_t busio_module_globals_table[] = {
{ MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_busio) },
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&busio_i2c_type) },
{ MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&busio_spi_type) },
//xxxx { MP_ROM_QSTR(MP_QSTR_OneWire), MP_ROM_PTR(&busio_onewire_type) },
//xxxx { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&busio_spi_type) },
//xxxx { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&busio_uart_type) },
};