use CONF_GCLK_DAC_SRC and refactor a bit
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4895a9d1d8
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5c24023240
@ -36,6 +36,7 @@
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#include "atmel_start_pins.h"
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#include "hal/include/hal_dac_sync.h"
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#include "hpl/gclk/hpl_gclk_base.h"
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#include "peripheral_clk_config.h"
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#ifdef SAMD21
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#include "hpl/pm/hpl_pm_base.h"
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@ -65,16 +66,16 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self,
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#ifdef SAMD51
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hri_mclk_set_APBDMASK_DAC_bit(MCLK);
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// This clock should be <= 12 MHz, per datasheet section 47.6.3.
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hri_gclk_write_PCHCTRL_reg(GCLK, DAC_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK5_Val | (1 << GCLK_PCHCTRL_CHEN_Pos));
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#endif
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#ifdef SAMD21
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_pm_enable_bus_clock(PM_BUS_APBC, DAC);
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// This clock should be <= 350kHz, per datasheet table 37-6.
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_gclk_enable_channel(DAC_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK1_Val);
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#endif
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// SAMD21: This clock should be <= 12 MHz, per datasheet section 47.6.3.
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// SAMD51: This clock should be <= 350kHz, per datasheet table 37-6.
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_gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC);
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// Don't double init the DAC on the SAMD51 when both outputs are in use. We use the free state
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// of each output pin to determine DAC state.
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int32_t result = ERR_NONE;
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