Commit Graph

97 Commits

Author SHA1 Message Date
Francisco J. Manno
f938e70c69 stm32: Add compile-time option to use HSI as clock source.
To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board
configuration file.  The default is to use HSE.

HSI has been made the default for the NUCLEO_F401RE board to serve as an
example, and because early revisions of this board need a hardware
modification to get HSE working.
2019-03-05 15:49:08 +11:00
Damien George
e61862d063 stm32/boards: Update to use new build config for lwip component. 2019-03-04 23:34:03 +11:00
Damien George
84479569de stm32/boards/STM32F769DISC: Use external QSPI flash to store some code.
This demonstrates how to use external QSPI flash in XIP (execute in place)
mode.  The default configuration has all extmod/ code placed into external
QSPI flash, but other code can easily be put there by modifying the custom
f769_qspi.ld script.
2019-03-04 22:40:15 +11:00
Damien George
823b31e528 stm32/boards/NUCLEO_F429ZI: Enable lwIP and Ethernet peripheral. 2019-02-26 23:32:19 +11:00
Damien George
ed0a530614 stm32/boards/STM32F769DISC: Enable lwIP and Ethernet peripheral. 2019-02-26 23:32:19 +11:00
Damien George
b3513f54d3 stm32/boards/STM32F7DISC: Enable lwIP and Ethernet peripheral. 2019-02-26 23:32:19 +11:00
Damien George
8daec24168 stm32/boards/NUCLEO_F767ZI: Enable lwIP and Ethernet peripheral. 2019-02-26 23:32:19 +11:00
Damien George
75a35448e1 stm32/boards/NUCLEO_F767ZI: Fix up comments about HCLK computation. 2019-02-26 22:44:27 +11:00
Damien George
c65e5c88b8 stm32/boards/stm32f429.ld: Increase uPy heap size by 64k for F429 MCU.
The F429 has 256k total RAM, with 64k already set aside for flash write
cache, so the uPy heap can be increased this much.
2019-02-18 13:18:59 +11:00
Damien George
7b2dc96251 stm32/boards/make-pins.py: Add cmdline options to support use by mboot. 2019-02-14 13:35:39 +11:00
Jolatomme
d1acca3c71 stm32/boards/NUCLEO_L476RG: Add support for RNG, DAC and CAN1.
PLLQ is changed to get CAN working, and I2C1 pins are changed to those
prescribed by the board.
2019-02-14 00:28:28 +11:00
Damien George
1669e049de stm32/boards/STM32F769DISC: Configure for use with mboot by default.
This is a good board to demonstrate the use of Mboot because it only has a
USB HS port exposed so the native ST DFU mode cannot be used.  With Mboot
this port can be used.
2019-02-07 16:28:01 +11:00
Damien George
be1b1835c3 stm32/boards/STM32F769DISC: Support the use of USB HS with external PHY. 2019-02-07 16:26:46 +11:00
Damien George
b367c425e4 stm32/boards/stm32h743_af.csv: Add ADC entries to pin capability table. 2019-02-06 13:34:53 +11:00
Damien George
02682d52ce stm32/boards/make-pins.py: Add basic support for STM32H7 ADC periphs. 2019-02-06 13:34:23 +11:00
Damien George
4bed17e786 stm32/boards/stm32f429_af.csv: Fix typos in UART defs Tx->TX and Rx->RX.
Fixes issue #4445.
2019-01-31 01:02:42 +11:00
Damien George
5146e79490 stm32/boards/NUCLEO_L432KC: Specify L4 OpenOCD config file for this MCU. 2018-12-13 13:45:16 +11:00
Damien George
59f409a787 stm32/boards: Allow OpenOCD stm_flash procedure to accept single FW img.
To support deplop-openocd on target boards that use TEXT0_ADDR only and
have their firmware in a single binary image.
2018-12-13 13:43:10 +11:00
boochow
69b7b8fa12 stm32/boards: Add NUCLEO_L432KC board configuration files. 2018-12-06 13:33:29 +11:00
boochow
1a8baad7ca stm32/boards: Add STM32L432KC chip configuration files.
The pin alternate function information is derived from ST's datasheet
https://www.st.com/resource/en/datasheet/stm32l432kc.pdf
In the datasheet, the line 2 of AF4 includes I2C2 but actually the chip
does not have I2C2 so it is removed.
2018-12-06 13:32:43 +11:00
Damien George
c040961e91 stm32/boards: Add configuration for putting mboot on PYBv1.x. 2018-12-04 23:48:18 +11:00
roland
10bddc5c28 stm32/boards/STM32F429DISC: Enable UART as secondary REPL.
The board(s) feature a VCOM through the ST-LINK, this feature is something
to keep around.
2018-12-01 17:30:48 +11:00
roland
30ed2b3cab stm32/system_stm32: Introduce configuration defines for PLL3 settings.
A board must be able to set the PLL3 values based on the HSE that it uses.
2018-11-01 13:25:47 +11:00
Damien George
d2c5496894 stm32/boards/stm32h743.ld: Fix total flash size, should be 2048k.
Fixes issue #4240.
2018-10-17 15:29:56 +11:00
Andrew Leech
338635ccc6 stm32/main: Add configuration macros for board to set heap start/end.
The macros are MICROPY_HEAP_START and MICROPY_HEAP_END, and if not defined
by a board then the default values will be used (maximum heap from SRAM as
defined by linker symbols).

As part of this commit the SDRAM initialisation is moved to much earlier in
main() to potentially make it available to other peripherals and avoid
re-initialisation on soft-reboot.  On boards with SDRAM enabled the heap
has been set to use that.
2018-10-05 17:30:18 +10:00
Damien George
4df1943948 stm32/boards/NUCLEO_F091RC: Enable USART3-8 with default pins. 2018-09-21 14:04:33 +10:00
Damien George
a5b583adfd stm32/boards/STM32F769DISC: Add optional support for external SDRAM. 2018-09-20 11:42:03 +10:00
Damien George
47550ef2cd stm32: For MCUs that have PLLSAI allow to set SYSCLK at 2MHz increments.
MCUs that have a PLLSAI can use it to generate a 48MHz clock for USB, SDIO
and RNG peripherals.  In such cases the SYSCLK is not restricted to values
that allow the system PLL to generate 48MHz, but can be any frequency.
This patch allows such configurability for F7 MCUs, allowing the SYSCLK to
be set in 2MHz increments via machine.freq().  PLLSAI will only be enabled
if needed, and consumes about 1mA extra.  This fine grained control of
frequency is useful to get accurate SPI baudrates, for example.
2018-09-11 16:42:57 +10:00
roland
67ee4e2401 stm32/boards/STM32L476DISC: Enable external RTC xtal to get RTC working. 2018-09-11 15:23:19 +10:00
forester3
02fbb0a455 stm32/boards/STM32F7DISC: Enable onboard SDRAM.
The default SYSCLK frequency is reduced to 192MHz because SDRAM requires it
to be 200MHz or less.
2018-08-14 16:04:10 +10:00
forester3
502c410214 stm32/boards/STM32F429DISC: Add burst len and autorefresh to SDRAM cfg.
To align with recent changes to sdram.c.
2018-08-14 16:03:13 +10:00
Andrew Leech
434975defa stm32/boards/STM32F429DISC: Enable onboard SDRAM. 2018-07-23 23:16:32 +10:00
Andrew Leech
4343c9330e stm32: Add method for statically configuring pin alternate function.
Works with pins declared normally in mpconfigboard.h, eg. (pin_XX), as well
as (pyb_pin_XX).

Provides new mp_hal_pin_config_alt_static(pin_obj, mode, pull, fn_type)
function declared in pin_static_af.h to allow configuring pin alternate
functions by name at compile time.
2018-07-20 14:03:21 +10:00
Peter D. Gray
a8736e5c36 stm32/flashbdev: Fix bug with L4 block cache, dereferencing block size.
The code was dereferencing 0x800 and loading a value from there, trying to
use a literal value (not address) defined in the linker script
(_ram_fs_cache_block_size) which was 0x800.
2018-07-19 12:15:34 +10:00
Damien George
a2ac7e4fc9 stm32/boards: Add .ld and af.csv files for STM32F722.
These files can also be used for F723, F732 and F733 MCUs.
2018-06-22 15:39:10 +10:00
Damien George
561ae9a91b stm32/boards/NUCLEO_F091RC: Fix TICK_INT_PRIORITY so it is highest prio.
Fixes issue #3880.
2018-06-20 12:24:18 +10:00
rolandvs
ca2b1d6b36 stm32/boards/NUCLEO_F091RC: Add Arduino-named pins and rename CPU pins.
To match pin labels on other NUCLEO 64 boards.
2018-06-18 13:06:27 +10:00
rolandvs
0d3de68669 stm32/boards/stm32f091_af.csv: Split labels that are multiple funcs. 2018-06-18 13:05:24 +10:00
Damien George
335d26b27d stm32/boards/STM32L476DISC: Update SPI flash config for cache change. 2018-06-14 16:52:56 +10:00
rolandvs
958fa74521 stm32/boards: Ensure USB OTG power is off for NUCLEO_F767ZI.
And update the GPIO init for NUCLEO_H743ZI to consistently use the mphal
functions.
2018-05-30 09:51:19 +10:00
rolandvs
50bc34d4a4 stm32/boards: Split combined alt-func labels and fix some other errors.
Pins with multiple alt-funcs for the same peripheral (eg USART_CTS_NSS)
need to be split into individual alt-funcs for make-pins.py to work
correctly.

This patch changes the following:
- Split `..._CTS_NSS` into `..._CTS/..._NSS`
- Split `..._RTS_DE` into `..._RTS/..._DE`
- Split `JTDO_SWO` into `JTDO/TRACESWO` for consistency
- Fixed `TRACECK` to `TRACECLK` for consistency
2018-05-29 21:37:49 +10:00
Damien George
e681372017 stm32/boards: Add NUCLEO_F091RC board configuration files. 2018-05-28 21:49:49 +10:00
Damien George
1163400039 stm32/boards: Add alt-func CSV list and linker script for STM32F091. 2018-05-28 21:49:49 +10:00
Damien George
4a7d157a5b stm32/boards: Add startup_stm32f0.s for STM32F0 MCUs.
Sourced from STM32Cube_FW_F0_V1.9.0.
2018-05-28 21:49:49 +10:00
Tobias Badertscher
769e37b646 stm32/boards: Add config files for new board, STM32L496GDISC. 2018-05-18 22:39:49 +10:00
Tobias Badertscher
4005c63571 stm32/boards: Add board ld and af.csv files for STM32L496 MCU. 2018-05-18 22:39:44 +10:00
Tobias Badertscher
708cdb6276 stm32: Add support for STM32L496 MCU. 2018-05-18 22:37:30 +10:00
Ryan Shaw
b9ff46f1ed stm32: Enable UART7/8 on F4 series that have these peripherals. 2018-05-16 11:55:07 +10:00
Damien George
68f4cba3d2 stm32/boards: Update pins.csv to include USB pins where needed. 2018-05-01 17:38:51 +10:00
iabdalkader
28c9824c51 stm32/boards/NUCLEO_H743ZI: Enable ADC peripheral. 2018-05-01 15:39:03 +10:00