stm32/boards/STM32F769DISC: Use external QSPI flash to store some code.
This demonstrates how to use external QSPI flash in XIP (execute in place) mode. The default configuration has all extmod/ code placed into external QSPI flash, but other code can easily be put there by modifying the custom f769_qspi.ld script.
This commit is contained in:
Damien George
parent
c8bbf2c170
commit
84479569de
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@ -0,0 +1,20 @@
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#include "drivers/memory/spiflash.h"
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#include "qspi.h"
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// This configuration is needed for mboot to be able to write to the external QSPI flash
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const mp_spiflash_config_t spiflash_config = {
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.bus_kind = MP_SPIFLASH_BUS_QSPI,
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.bus.u_qspi.data = NULL,
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.bus.u_qspi.proto = &qspi_proto,
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.cache = NULL,
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};
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mp_spiflash_t spiflash_instance;
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// This init function is needed to memory map the QSPI flash early in the boot process
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void board_early_init(void) {
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qspi_init();
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qspi_memory_map();
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}
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@ -0,0 +1,108 @@
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/*
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Custom linker script for STM32F769DISC board with external memory-mapped QSPI flash
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Memory layout:
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FLASH_QSPI .text_qspi
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FLASH_APP .isr_vector
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FLASH_APP .text
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FLASH_APP .data
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RAM .data
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RAM .bss
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RAM .heap
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RAM .stack
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*/
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MEMORY
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{
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FLASH_APP (rx) : ORIGIN = 0x08020000, LENGTH = 2016K /* sectors 1-11 3x32K 1*128K 7*256K */
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FLASH_QSPI (rx) : ORIGIN = 0x90000000, LENGTH = 64M /* external QSPI flash in XIP mode */
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DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for storage cache */
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RAM (xrw) : ORIGIN = 0x20020000, LENGTH = 384K /* SRAM1 = 368K, SRAM2 = 16K */
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}
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/* Produce a link error if there is not this amount of RAM for these sections */
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_minimum_stack_size = 2K;
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_minimum_heap_size = 16K;
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/* Define tho top end of the stack */
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_estack = ORIGIN(RAM) + LENGTH(RAM);
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/* RAM extents for the garbage collector */
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_ram_start = ORIGIN(RAM);
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_ram_end = ORIGIN(RAM) + LENGTH(RAM);
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_heap_start = _ebss; /* heap starts just after statically allocated memory */
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_heap_end = 0x20078000; /* tunable */
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ENTRY(Reset_Handler)
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SECTIONS
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{
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/* Define the code that goes in QSPI flash */
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.text_qspi :
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{
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. = ALIGN(4);
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*extmod/*(.text* .rodata*)
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. = ALIGN(4);
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} >FLASH_QSPI
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/* The startup code goes first into main flash */
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector))
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. = ALIGN(4);
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} >FLASH_APP
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/* The program code and other data goes into flash */
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.text :
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{
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. = ALIGN(4);
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*(.text*)
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*(.rodata*)
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. = ALIGN(4);
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_etext = .;
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} >FLASH_APP
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/* Used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* The initialized data section */
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.data :
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{
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. = ALIGN(4);
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_sdata = .;
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*(.data*)
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. = ALIGN(4);
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_edata = .;
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} >RAM AT> FLASH_APP
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/* The uninitialized (zeroed) data section */
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.bss :
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{
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. = ALIGN(4);
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_sbss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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} >RAM
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/* Define the start of the heap, and make sure we have a minimum size */
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.heap :
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{
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. = ALIGN(4);
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. = . + _minimum_heap_size;
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. = ALIGN(4);
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} >RAM
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/* Just checks there is enough RAM for the stack */
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.stack :
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{
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. = ALIGN(4);
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. = . + _minimum_stack_size;
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. = ALIGN(4);
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} >RAM
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}
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@ -14,6 +14,9 @@
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#define MICROPY_HW_ENABLE_RTC (1)
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#define MICROPY_HW_ENABLE_USB (1)
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#define MICROPY_BOARD_EARLY_INIT board_early_init
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void board_early_init(void);
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// HSE is 25MHz
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// VCOClock = HSE * PLLN / PLLM = 25 MHz * 432 / 25 = 432 MHz
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// SYSCLK = VCOClock / PLLP = 432 MHz / 2 = 216 MHz
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@ -25,6 +28,15 @@
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#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_7 // 210-216 MHz needs 7 wait states
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// 512MBit external QSPI flash, to be memory mapped
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#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (29)
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#define MICROPY_HW_QSPIFLASH_CS (pin_B6)
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#define MICROPY_HW_QSPIFLASH_SCK (pin_B2)
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#define MICROPY_HW_QSPIFLASH_IO0 (pin_C9)
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#define MICROPY_HW_QSPIFLASH_IO1 (pin_C10)
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#define MICROPY_HW_QSPIFLASH_IO2 (pin_E2)
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#define MICROPY_HW_QSPIFLASH_IO3 (pin_D13)
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// UART config
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#define MICROPY_HW_UART1_TX (pin_A9)
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#define MICROPY_HW_UART1_RX (pin_A10)
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@ -177,3 +189,16 @@
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#define MICROPY_HW_FMC_D30 (pyb_pin_FMC_D30)
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#define MICROPY_HW_FMC_D31 (pyb_pin_FMC_D31)
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#endif
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/******************************************************************************/
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// Bootloader configuration
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// Give Mboot access to the external QSPI flash
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extern const struct _mp_spiflash_config_t spiflash_config;
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extern struct _mp_spiflash_t spiflash_instance;
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#define MBOOT_SPIFLASH_ADDR (0x90000000)
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#define MBOOT_SPIFLASH_BYTE_SIZE (512 * 128 * 1024)
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#define MBOOT_SPIFLASH_LAYOUT "/0x90000000/512*128Kg"
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#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (128 / 4) // 128k page, 4k erase block
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#define MBOOT_SPIFLASH_CONFIG (&spiflash_config)
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#define MBOOT_SPIFLASH_SPIFLASH (&spiflash_instance)
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@ -1,18 +1,38 @@
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# By default this board is configured to use mboot which must be deployed first
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USE_MBOOT ?= 1
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# By default this board puts some code into external QSPI flash set in XIP mode
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# USE_MBOOT must be enabled; see f769_qspi.ld for code that goes in QSPI flash
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USE_QSPI ?= 1
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# MCU settings
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MCU_SERIES = f7
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CMSIS_MCU = STM32F769xx
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MICROPY_FLOAT_IMPL = double
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AF_FILE = boards/stm32f767_af.csv
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ifeq ($(USE_MBOOT),1)
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# When using Mboot all the text goes together after the filesystem
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ifeq ($(USE_QSPI),1)
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# When using Mboot and QSPI the text is split between internal and external flash
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LD_FILES = boards/STM32F769DISC/f769_qspi.ld
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TEXT0_ADDR = 0x08020000
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TEXT1_ADDR = 0x90000000
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TEXT0_SECTIONS = .isr_vector .text .data
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TEXT1_SECTIONS = .text_qspi
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else
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# When using Mboot but not QSPI all the text goes together after the filesystem
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LD_FILES = boards/stm32f769.ld boards/common_blifs.ld
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TEXT0_ADDR = 0x08020000
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endif
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else
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# When not using Mboot the ISR text goes first, then the rest after the filesystem
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LD_FILES = boards/stm32f769.ld boards/common_ifs.ld
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TEXT0_ADDR = 0x08000000
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TEXT1_ADDR = 0x08020000
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endif
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@ -69,6 +69,12 @@ UART5_TX,PC12
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UART5_RX,PD2
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CAN2_TX,PB13
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CAN2_RX,PB12
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QSPI_CS,PB6
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QSPI_CLK,PB2
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QSPI_D0,PC9
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QSPI_D1,PC10
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QSPI_D2,PE2
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QSPI_D3,PD13
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ETH_REF_CLK,PA1
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ETH_MDIO,PA2
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ETH_CRS_DV,PA7
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