Commit Graph

51 Commits

Author SHA1 Message Date
Damien George a234aa44f3 stm32/powerctrl: Don't compile WB helpers on WL MCUs.
Signed-off-by: Damien George <damien@micropython.org>
2023-03-08 23:57:53 +11:00
Andrew Leech c551723914 stm32/powerctrl: Disable WB55 BLE before entering deepsleep.
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
2023-03-08 14:03:36 +11:00
Andrew Leech 2eca86e8fa stm32/powerctrl: Add sleep RCC semaphore management for WB55 MCUs.
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
2023-03-08 11:33:00 +11:00
Damien George bb77c1d5a3 stm32/powerctrl: Fix build on STM32G0xx and STM32H7Bx MCUs.
STM32G0xx doesn't have DBGMCU, and STM32H7Bx doesn't have EXTI_D2.

Signed-off-by: Damien George <damien@micropython.org>
2022-12-16 16:48:59 +11:00
iabdalkader 5b7f71882b stm32/powerctrl: Improve standby mode entry code for H7 MCUs.
Changes in this commit:
- Clear and mask D2 EXTIs.
- Set correct voltage scaling level for standby mode.
- Disable debug MCU (if debugging is disabled), for all MCU series.
2022-12-15 14:39:28 +11:00
yn386 427d72667f stm32: Add support for STM32L1 MCUs.
This change adds STM32L1 support to the STM32 port.
2022-09-25 23:56:41 +10:00
Angus Gratton 2c015375d1 stm32: Use a separate symbol name for the bootloader state pointer.
Prerequisite for enabling Link Time Optimisation.

The _bl_state address is the same as _estack, but _estack is referred to as
a uint32_t elsewhere in the code. LTO doesn't like it when the same symbol
has two different types.

Signed-off-by: Angus Gratton <gus@projectgus.com>
2022-06-28 10:25:08 +10:00
Clayton Mills 0d8d911950 stm32/powerctrl: Disable sys tick interrupt in stop mode on some STM32s.
According to ST Errata ES0206 Rev 18, Section 2.2.1, on STM32F427x,
STM32F437x, STM32F429x and STM32F439x.

If the system tick interrupt is enabled during stop mode while certain
bits are set in the DBGMCU_CR, then the system will immediately wake
from stop mode.

Suggested workaround is to disable system tick timer interrupt when
entering stop mode.

According to ST Errate ES0394 Rev 11, Section 2.2.17, on STM32WB55Cx and
STM32WB35Cx.

If the system tick interrupt is enabled during stop 0, stop 1 or stop 2
while certain bits are set in DBGMCU_CR, then system will immediately
wake from stop mode but the system remains in low power state. The CPU
therefore fetches incorrect data from inactive Flash, which can cause a
hard fault.

Suggested workaround is to disable system tick timer interrupt when
entering stop mode.
2022-06-07 18:08:02 +10:00
Asensio Lorenzo Sempere 010012c7c3 stm32: Add support for G0 MCUs.
This commit adds support for the STM32G0 series of MCUs.

Signed-off-by: Asensio Lorenzo Sempere <asensio.aerospace@gmail.com>
2022-04-28 11:56:15 +10:00
Damien George e0a0719416 stm32: Add initial support for STM32WL MCUs.
Signed-off-by: Damien George <damien@micropython.org>
2022-02-04 09:43:43 +11:00
Herwin Grobben 8f68e26f79 stm32: Add support for G4 MCUs, and add NUCLEO_G474RE board defn.
This commit adds support for the STM32G4 series of MCUs, and a board
definition for NUCLEO_G474RE.  This board has the REPL on LPUART1 which is
connected to the on-board ST-link USB-UART.
2022-02-01 16:21:01 +11:00
Damien George c99ed8d6fa stm32/powerctrl: Write bootloader-state as 64-bit word to work on H7.
H7 MCUs have ECC and writes do not go through to SRAM until 64-bits have
been written (on another location is written).  So use 64-bit writes for
the bootloader-state variable so it is committed before the system reset.

As part of this change, the lower byte of the bootloader address in
BL_STATE must now be the magic number 0x5a5 for the state to be valid
(previously this was 0x000 which is not as robust).

Signed-off-by: Damien George <damien@micropython.org>
2022-01-31 18:26:55 +11:00
Jan Staal 9e2423e730 stm32: Add support for H7A3(Q)/H7B3(Q), and STM32H73B3I_DK board defn.
This commit is based upon prior work of @dpgeorge and @koendv.

MCU support for the STM32H7A3 and B3 families MCUs:
- STM32H7A3xx
- STM32H7A3xxQ (SMPS)
- STM32H7B3xx
- STM32H7B3xxQ (SMPS)

Support has been added for the STM32H7B3I_DK board.

Signed-off-by: Jan Staal <info@janstaal.com>
2021-09-16 12:29:28 +10:00
Jan Hrudka d451dc0086 stm32: Add basic support for STM32H750. 2021-09-15 10:42:20 +10:00
Damien George f834fef6bb stm32/powerctrl: Support changing frequency on WB MCUs.
This allows changing the frequency to: 100kHz, 200kHz, 400kHz, 800kHz,
1MHz, 2MHz, 4MHz, 8MHz, 16MHz, 32MHz, 64MHz.  For frequencies 2MHz and
below, low power run (LPR) mode is enabled automatically.

Signed-off-by: Damien George <damien@micropython.org>
2021-08-07 23:41:20 +10:00
Damien George ee4ffc1804 stm32/powerctrl: Add MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET option.
When disabled the bootloader is entered via a direct jump.  When enabled
the bootloader is entered via a system reset then a jump.  It's enabled by
default to retain the existing behaviour, which is the recommended way.

Signed-off-by: Damien George <damien@micropython.org>
2021-05-12 13:44:41 +10:00
Damien George f4340b7e62 stm32/powerctrl: Support using PLLI2C on STM32F413 as USB clock source.
So SYSCLK can run at more varied frequencies, eg 100MHz.

Signed-off-by: Damien George <damien@micropython.org>
2021-04-07 12:47:21 +10:00
Damien George 00963a4e69 stm32/powerctrl: Allow a board to configure AHB and APB clock dividers.
Signed-off-by: Damien George <damien@micropython.org>
2021-04-07 12:47:09 +10:00
Peter Hinch 0facd891e7 stm32/powerctrl: Save and restore EWUP state when configuring standby.
This allows the user to enable wake-up sources using the EWUP bits, on F7
MCUs.

Disabling the wake-up sources while clearing the wake-up flags follows the
reference manual and ST examples.
2021-03-11 00:56:01 +11:00
iabdalkader 7dc2f4ed38 stm32/powerctrl: Ensure SysTick is disabled on STOP mode entry for H7.
Even though IRQs are disabled this seems to be required on H7 Rev Y,
otherwise Systick interrupt triggers and the MCU leaves the stop mode
immediately.
2020-12-07 17:00:56 +11:00
iabdalkader 7b9b6d080a stm32/powerctrl: Set H7 RTC wakeup flags. 2020-12-07 17:00:42 +11:00
iabdalkader 8add94e94e stm32/powerctrl: Disable RTC write protection before changing flags. 2020-12-07 17:00:21 +11:00
iabdalkader 463a275bc4 stm32/powerctrl: On H7, re-enable disabled OSCs/PLLs on exit from STOP.
This commit saves OSCs/PLLs state before STOP mode and restores them on
exit.  Some boards use HSI48 for USB for example, others have PLL2/3
enabled, etc.
2020-12-07 16:58:38 +11:00
iabdalkader 3e5dd2dbcc stm32/powerctrl: Fix STOP mode voltage scaling on H7 REV V devices. 2020-12-07 16:58:00 +11:00
iabdalkader e9e619fa24 stm32/powerctrl: Define RCC_SR_SFTRSTF flag for H747. 2020-12-07 16:57:29 +11:00
Damien George 68d053c66e stm32/modmachine: Allow changing AHB and APB bus frequencies on STM32WB.
For now SYSCLK cannot be changed and must remain at 64MHz.
2020-06-02 10:48:49 +10:00
Damien George 69661f3343 all: Reformat C and Python source code with tools/codeformat.py.
This is run with uncrustify 0.70.1, and black 19.10b0.
2020-02-28 10:33:03 +11:00
Damien George af88e70414 stm32/powerctrl: Reenable PLL3 on H7 MCUs when waking from stop mode.
So that USB can work.
2020-01-31 23:25:18 +11:00
Damien George 2c8c2b935e stm32/powerctrl: Improve support for changing system freq on H7 MCUs.
This commit improves pllvalues.py to generate PLL values for H7 MCUs that
are valid (VCO in and out are in range) and extend for the entire range of
SYSCLK values up to 400MHz (up to 480MHz is currently unsupported).
2020-01-31 23:25:18 +11:00
Damien George 68db7e01d8 stm32/powerctrl: Enable overdrive on F7 when waking from stop mode.
Because if the SYSCLK is set to 180MHz or higher it will require this to be
on already.
2020-01-30 16:30:03 +11:00
Damien George 29b84ea798 stm32/powerctrl: Disable HSI if not needed to save a bit of power. 2020-01-30 16:29:45 +11:00
Damien George a542c6d7e0 stm32/powerctrl: For F7, allow PLLM!=HSE when setting PLLSAI to 48MHz.
PLLM is shared among all PLL blocks on F7 MCUs, and this calculation to
configure PLLSAI to have 48MHz on the P output previously assumed that PLLM
is equal to HSE (eg PLLM=25 for HSE=25MHz).  This commit relaxes this
assumption to allow other values of PLLM.
2020-01-29 16:49:13 +11:00
Jim Mussared 06661890de stm32/powerctrl: Fix machine.bootloader() for L0 MCUs. 2019-09-04 11:36:53 +10:00
Damien George 59b7166d87 stm32: Add initial support for STM32WBxx MCUs.
This new series of MCUs is similar to the L4 series with an additional
Cortex-M0 coprocessor.  The firmware for the wireless stack must be managed
separately and MicroPython does not currently interface to it.  Supported
features so far include: RTC, UART, USB, internal flash filesystem.
2019-07-17 16:33:31 +10:00
Damien George 21ecf8be5f stm32/powerctrl: Move L0's SystemClock_Config to powerctrlboot.c file. 2019-07-08 15:23:53 +10:00
Damien George 23d9c6a0fd stm32: Add initial support for STM32L0xx MCUs. 2019-07-05 17:24:59 +10:00
Damien George ea033bf25a stm32/powerctrl: Add hooks for a board to perform actions on sleep/wake. 2019-07-03 01:27:33 +10:00
Damien George 04c7cdb668 stm32: Enter bootloader via a system reset.
Entering a bootloader (ST system bootloader, or custom mboot) from software
by directly branching to it is not reliable, and the reliability of it
working can depend on the peripherals that were enabled by the application
code.  It's also not possible to branch to a bootloader if the WDT is
enabled (unless the bootloader has specific provisions to feed the WDT).

This patch changes the way a bootloader is entered from software by first
doing a complete system reset, then branching to the desired bootloader
early on in the start-up process.  The top two words of RAM (of the stack)
are reserved to store flags indicating that the bootloader should be
entered after a reset.
2019-06-25 14:15:49 +10:00
Damien George 3fbf32b947 stm32/powerctrl: Support changing frequency when HSI is clock source.
This patch makes pllvalues.py generate two tables: one for when HSI is used
and one for when HSE is used.  The correct table is then selected at
compile time via the existing MICROPY_HW_CLK_USE_HSI.
2019-05-02 13:00:00 +10:00
Damien George 8031b7a25c stm32/powerctrl: Deselect PLLSAI as 48MHz src before turning off PLLSAI.
On the STM32F722 (at least, but STM32F767 is not affected) the CK48MSEL bit
must be deselected before PLLSAION is turned off, or else the 48MHz
peripherals (RNG, SDMMC, USB) may get stuck without a clock source.

In such "lock up" cases it seems that these peripherals are still being
clocked from the PLLSAI even though the CK48MSEL bit is turned off.  A hard
reset does not get them out of this stuck state.  Enabling the PLLSAI and
then disabling it does get them out.  A test case to see this is:

    import machine, pyb
    for i in range(100):
        machine.freq(122_000000)
        machine.freq(120_000000)
        print(i, [pyb.rng() for _ in range(4)])

On occasion the RNG will just return 0's, but will get fixed again on the
next loop (when PLLSAI is enabled by the change to a SYSCLK of 122MHz).

Fixes issue #4696.
2019-04-29 16:31:32 +10:00
Damien George 8402c26cfa stm32/powerctrl: Enable EIWUP to ensure RTC wakes device from standby. 2019-04-18 17:15:11 +10:00
Francisco J. Manno f938e70c69 stm32: Add compile-time option to use HSI as clock source.
To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board
configuration file.  The default is to use HSE.

HSI has been made the default for the NUCLEO_F401RE board to serve as an
example, and because early revisions of this board need a hardware
modification to get HSE working.
2019-03-05 15:49:08 +11:00
Damien George c6365ffb92 stm32/powerctrl: Add support for standby mode on L4 MCUs.
This maps to machine.deepsleep() which is now supported.
2018-12-05 00:40:05 +11:00
Damien George afd1ce0c15 stm32/powerctrl: Disable IRQs during stop mode to allow reconfig on wake 2018-11-28 12:44:54 +11:00
Damien George 66ca8e9b2c stm32/powerctrl: Move (deep)sleep funcs from modmachine.c to powerctrl.c 2018-11-28 12:22:20 +11:00
Damien George 6ea6c7cc9e stm32/powerctrl: Don't configure clocks if already at desired frequency.
Configuring clocks is a critical operation and is best to avoid when
possible.  If the clocks really need to be reset to the same values then
one can pass in a slightly higher value, eg 168000001 Hz to get 168MHz.
2018-09-24 17:34:05 +10:00
Damien George bc54c57590 stm32/powerctrl: Optimise passing of default values to set_sysclk. 2018-09-24 17:34:05 +10:00
Damien George dae1635c71 stm32/powerctrl: Factor code that configures PLLSAI on F7 MCUs. 2018-09-24 17:34:05 +10:00
Damien George 90ea2c63a5 stm32/powerctrl: Factor code to set RCC PLL and use it in startup.
This ensures that on first boot the most optimal settings are used for the
voltage scaling and flash latency (for F7 MCUs).

This commit also provides more fine-grained control for the flash latency
settings.
2018-09-24 17:34:05 +10:00
Damien George 9e4812771b stm32/powerctrl: Fix configuring APB1/APB2 frequency when AHB also set.
APB1/APB2 are derived from AHB, so if the user sets AHB!=SYSCLK then the
APB1/APB2 dividers must be computed from the new AHB.
2018-09-24 14:51:17 +10:00