Changes are:
- The pin-af-table-SAMDxx.csv file are moved to the mcu directories with
the name as pin-af-table.csv.
- The handling in Makefile and pin_af.c is simplified.
Two new compile flags are:
MICROPY_HW_DFLL_USB_SYNC: Effective only if DFLL48 does not run from the
crystal. It will synchronize the DFLL48M clock with the USB's SOF pulse.
If no USB is connected, it will fall back to open loop mode. The DFLL48M
clock is then pretty precise, but with a higher clock jitter at SAMD51
devices.
MICROPY_HW_MCU_OSC32KULP: Effective only if the devics uses a crystal as
clock source. Run the MCU clock from the ULP 32kHz oszillator instead of
the crystal. This flag was added to cater for a interference problem of
the crystal and Neopixel/Debug pins at Adafruit FEATHER Mx boards, which
causes the board to crash. Drawback: ticks_ms() and time.time() vs. than
ticks_us() and the peripherals like PWM run at not synchronous clocks.
Changes are:
- Set the feature level for each MCU: CORE features for SAMD21, and EXTRA
features for SAMD51.
- Remove all definitions that are included in the core feature level.
- Keep the default settings for feature level and float, to make the choice
obvious.
The SAMD21 implementation is an adaption of @jimmo's code for STM32Lxx.
The only changes are the addresses and names of the port registers and the
timing parameters.
SAMD21: The precision is about +/-25ns at 48MHz clock frequency. The first
two cycles are about 40-60 ns longer than set. But still good enough to
drive a neopixel device.
SAMD51: The precision is about +/-30ns at 120MHz clock frequency. Good
enough to drive a neopixel device.
And use mp_hal_ticks_us() for SAM21's mp_hal_ticks_cpu(). The SAMD21 has
no CYCCNT register, and the SysTick register has only a 1 ms span (== 48000
count range).
Fixes are:
- Pin definitions for ADAFRUIT_FEATHER_Mx_EXPRESS and
ADAFRUIT_ITSYBITSY_M4_EXPRESS.
- For ADAFRUIT_ITSYBITSY_M0_EXPRESS, change the MISO/MOSI name.
- For MINISAM_M4, add the default SPI pins.
- For boards with 32k crystal, add the XOSC32K setting.
It can be enabled/disabled by a configuration switch. The code size
increase is 308 bytes, but it requires RAM space for buffers, the larger
UART object and root pointers.
Allowing to set a time and retrieve the time. It is based on systick_ms()
with the precision of the MCU clock. Unless that is based on a crystal,
the error seen was about 0.5% at room temperature.
It suuports 1 channel @ 10 bit for SAMD21, 2 channels @ 12 bit for SAMD51.
Instantiation by:
dac = machine.DAC(ch) # 0 or 1
Method write:
dac.write(value)
The output voltage range is 0..Vdd.
By reducing the methods to on(), off(), toggle() and call, and using the
method implementation of the machine.Pin class.
The code size reduction is 756 byte.
All board pins that have UART's assigned can be used. Baud rate range is
75 Baud to ~2 MBaud.
No flow control yet, and only RX is buffered. TX buffer and flow control
may be added later for SAMD51 with its larger RAM and Flash.
Its API conforms to the docs. There are 16 IRQ channels available, which
will be used as assignable to the GPIO numbers. In most cases, the irq
channel is GPIO_no % 16.
Changes are:
- Have two separate tables for SAM21 and SAMD51.
- Use a short table for SAMD21.
- Add a comment to each line telling what it's for, making further use
easier.
- Add preliminary handlers/entries for PendSV, EIC and Sercom. These will
be replaced later when the respecitve modules are added.
Features are:
- 3 to 5 different frequency groups.
- Freq range of 1Hz - 24 MHz.
- Duty rate stays stable on freq change.
Keyword options to the PWM constructor:
- device=n Select a specific PWM device. If no device is specified, a free
device is chosen, if available at that pin.
- freq=nnnn
- duty_u16=nnnn
- duty_ns=nnnn
- invert=True/False Allowing two outputs on the same device/channel to have
complementary signals.
If both freq and duty are provided, PWM output will start immediately.
Pins at the same device have the same frequency. If the PWM output number
exceeds the number of channels at the PWM device, the effctive channel_no
is output_no % channel_count. So with a channel count of 4, output 7 is
assigned to channel 3. Pins at a certain channel have the same frequency
and duty rate, but may be seperately inverted.
With the method read_u16(). Keyword arguments of the constructor are:
- bits=n The resolution; default is 12.
- average=n The average of samples, which are taken and cumulated. The
default value is 16. Averaging by hw is faster than averaging
in code.
The ADC runs at a clock freq 1.5 MHz. A single 12 bit conversion takes
8 microseconds.
The pin af table is a representation of the MUX table from the data sheet.
It provides information for each pin about the supported device functions.
That information is needed by pin.irq, machine.ADC, machine.PWM,
machine.UART, machine.SPI and machine.I2C. For each of these, the table
tells for each pin, which device number, af number and pad number is
assigned. Using the table gives a straight, uniform access to the
information, where the benefit outweights the size of the table, which is
not that large.
The tables are MCU-specific. It is not required to tell for each board,
which and where each of the above devices is available. That makes addding
boards easy.
Note: The information for DAC and I2S was not included, since it affects
only a few pins.
Changes in this commit are:
- Use mphal_xx functions whenever possible.
- Remove obsolete includes.
- Clean up traces of a non-functional pin.irq() from earlier builds.
Pin.irq() will be added in further commits in a working manner.
The changes in this commit are:
- Add an interface for pin open-drain mode.
- Improve ticks_us() by using the us-counter.
- Improve ticks_cpu() by using the CPU's SysTick.
Clock settings:
- GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51).
- GCLK1: 32768 Hz for driving the PLL.
- GCLK2: 48 MHz for tzhe peripheral clock.
- GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer.
- GCLK8: 1 kHz for WDT (SAMD21 only).
If a 32 kHz crystal is present, it will be used as clock source. Otherwise
the DFLL48M in open-loop mode is used.
GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified
range is 96 MHz - 120 MHz.
These two boards are used for testing, so it is favorable to have them
added early.
The full test set is:
- ADAFRUIT_FEATHER_M4_EXPRESS: SAMD51 with 32kHz crystal.
- ADAFRUIT_ITSYBITSY_M0_EXPRESS: SAMD21 without crystal.
- ADAFRUIT_ITSYBITSY_M4_EXPRESS: SAMD51 without crystal.
- SEEED_XIAO: SAM21 with 32kHz crystal.
Auto DMA channel is supported in IDF v4.4, and is required to be used on S3
chips, so use this simpler configuration option where possible.
Fixes issue #8634.
Signed-off-by: Damien George <damien@micropython.org>
Updates all README.md and docs, and manifests to `require("mip")`.
Also extend and improve the documentation on freezing and packaging.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
