samd/machine_bitstream: Add the machine.bitstream() function.
The SAMD21 implementation is an adaption of @jimmo's code for STM32Lxx. The only changes are the addresses and names of the port registers and the timing parameters. SAMD21: The precision is about +/-25ns at 48MHz clock frequency. The first two cycles are about 40-60 ns longer than set. But still good enough to drive a neopixel device. SAMD51: The precision is about +/-30ns at 120MHz clock frequency. Good enough to drive a neopixel device.
This commit is contained in:
robert-hh
Damien George
parent
fd7b57dd22
commit
a415752173
@ -87,10 +87,11 @@ LIBSTDCPP_FILE_NAME = "$(shell $(CXX) $(CXXFLAGS) -print-file-name=libstdc++.a)"
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LDFLAGS += -L"$(shell dirname $(LIBSTDCPP_FILE_NAME))"
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endif
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SRC_C = \
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SRC_C += \
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clock_config.c \
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help.c \
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machine_adc.c \
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machine_bitstream.c \
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machine_dac.c \
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machine_i2c.c \
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machine_led.c \
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206
ports/samd/machine_bitstream.c
Normal file
206
ports/samd/machine_bitstream.c
Normal file
@ -0,0 +1,206 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Jim Mussared
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// This is a translation of the cycle counter implementation in ports/stm32/machine_bitstream.c.
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#include "py/mpconfig.h"
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#include "py/mphal.h"
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#include "clock_config.h"
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#if MICROPY_PY_MACHINE_BITSTREAM
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#if __CORTEX_M == 0
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// No cycle counter on M0, do manual cycle counting instead.
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// STM32F091 @ 48MHz
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#define NS_CYCLES_PER_ITER_HIGH (3)
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#define NS_CYCLES_PER_ITER_LOW (3)
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#define NS_OVERHEAD_CYCLES_HIGH (12)
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#define NS_OVERHEAD_CYCLES_LOW (15)
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uint32_t mp_hal_delay_ns_calc(uint32_t ns, bool high) {
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uint32_t ncycles = (get_cpu_freq() / 1000000 * ns + 500) / 1000; // + 500 for proper rounding
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uint32_t overhead = MIN(ncycles, high ? NS_OVERHEAD_CYCLES_HIGH : NS_OVERHEAD_CYCLES_LOW);
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return MAX(1, MP_ROUND_DIVIDE(ncycles - overhead, high ? NS_CYCLES_PER_ITER_HIGH : NS_CYCLES_PER_ITER_LOW));
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}
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void machine_bitstream_high_low(mp_hal_pin_obj_t pin, uint32_t *timing_ns, const uint8_t *buf, size_t len) {
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volatile const uint32_t mask = 1 << (pin % 32);
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volatile uint32_t *outclr = &PORT->Group[pin / 32].OUTCLR.reg;
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volatile uint32_t *outset = &PORT->Group[pin / 32].OUTSET.reg;
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// Convert ns to loop iterations [high_time_0, low_time_0, high_time_1, low_time_1].
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for (size_t i = 0; i < 4; ++i) {
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timing_ns[i] = mp_hal_delay_ns_calc(timing_ns[i], i % 2 == 0);
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}
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mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION();
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// Measured timing for SAMD21 at 48MHz (cycle=20.83ns)
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// timing_ns = (1,1,1,1)
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// high: 310
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// low: 375
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// high0: 375
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// low0: 400
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// timing_ns = (500, 500, 500, 500)
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// high: 500
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// low: 500
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// high0: 565
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// low0: 540
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// timing_ns = (1000, 1000, 1000, 1000)
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// high: 1000
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// low: 1000
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// high0: 1065
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// low0: 1040
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// --> high is 12 + n*3 cycles
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// low is 15 + n*3 cycles
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// NeoPixel timing (400, 850, 800, 450) (+/-150ns) gives timing_ns=(2, 9, 8, 3) which in cycles is
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// (12 + 6, 15 + 27, 15 + 24, 12 + 9) = (18, 42, 39, 21)
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// --> (375, 875, 812, 437) nanoseconds.
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// Measured output on logic analyser is (375, 875, 815, 435) (+/-5ns at 200MHz)
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// Note: the first high/low cycle is longer by 2-3 cycles (40-60ns).
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// This is slightly outside spec, but doesn't seem to cause a problem.
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__asm volatile (
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// Force consistent register assignment.
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// r6 = len
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"ldr r6, %0\n"
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// r4 = buf
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"ldr r4, %1\n"
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// r5 = timing_ms
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"ldr r5, %2\n"
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// Must align for consistent timing.
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".align 4\n"
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// Don't increment/decrement before first iteration.
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"b .outer2\n"
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".outer:\n"
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// ++buf, --len
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" add r4, #1\n"
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" sub r6, #1\n"
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// len iterations
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".outer2:\n"
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" cmp r6, #0\n"
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" beq .done\n"
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// r0 = *buf
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" ldrb r0, [r4, #0]\n"
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// 8 bits in byte
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" mov r7, #8\n"
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" .inner:\n"
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// *outset = mask
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" ldr r2, %3\n"
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" ldr r1, %5\n"
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" str r1, [r2, #0]\n"
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// r3 = (r0 >> 4) & 8 (r0 is 8 if high bit is 1 else 0)
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" mov r8, r6\n"
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" lsr r3, r0, #4\n"
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" mov r6, #8\n"
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" and r3, r6\n"
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" mov r6, r8\n"
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// r2 = timing_ns[r2]
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" ldr r2, [r5, r3]\n"
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" .loop1:\n sub r2, #1\n bne .loop1\n"
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// *outclr = mask
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" ldr r2, %4\n"
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" str r1, [r2, #0]\n"
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// r2 = timing_ns[r3 + 4]
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" add r3, #4\n"
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" ldr r2, [r5, r3]\n"
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" .loop2:\n sub r2, #1\n bne .loop2\n"
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// b >>= 1
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" lsl r0, r0, #1\n"
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" sub r7, #1\n"
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// end of inner loop
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" beq .outer\n"
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// continue inner loop
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" b .inner\n"
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".done:\n"
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:
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: "m" (len), "m" (buf), "m" (timing_ns), "m" (outset), "m" (outclr), "m" (mask)
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: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8"
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);
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MICROPY_END_ATOMIC_SECTION(atomic_state);
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}
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#else // > CORTEX_M0
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#define NS_TICKS_OVERHEAD (70)
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void machine_bitstream_high_low(mp_hal_pin_obj_t pin, uint32_t *timing_ns, const uint8_t *buf, size_t len) {
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uint32_t fcpu_mhz = get_cpu_freq() / 1000000;
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uint32_t ticks_overhead = fcpu_mhz * NS_TICKS_OVERHEAD / 1000;
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// Convert ns to us ticks [high_time_0, period_0, high_time_1, period_1].
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for (size_t i = 0; i < 4; ++i) {
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timing_ns[i] = fcpu_mhz * timing_ns[i] / 1000;
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if (timing_ns[i] > ticks_overhead) {
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timing_ns[i] -= ticks_overhead;
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}
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if (i % 2 == 1) {
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// Convert low_time to period (i.e. add high_time).
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timing_ns[i] += timing_ns[i - 1] - ticks_overhead;
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}
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}
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mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION();
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DWT->CYCCNT = 0;
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for (size_t i = 0; i < len; ++i) {
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uint8_t b = buf[i];
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for (size_t j = 0; j < 8; ++j) {
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uint32_t start_ticks = mp_hal_ticks_cpu();
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uint32_t *t = &timing_ns[b >> 6 & 2];
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mp_hal_pin_high(pin);
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while ((mp_hal_ticks_cpu() - start_ticks) < t[0]) {
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}
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b <<= 1;
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mp_hal_pin_low(pin);
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while ((mp_hal_ticks_cpu() - start_ticks) < t[1]) {
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}
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}
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}
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MICROPY_END_ATOMIC_SECTION(atomic_state);
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}
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#endif // > CORTEX_M0
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#endif // MICROPY_PY_MACHINE_BITSTREAM
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@ -25,6 +25,7 @@
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*/
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#include "py/runtime.h"
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#include "extmod/machine_bitstream.h"
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#include "extmod/machine_mem.h"
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#include "extmod/machine_pulse.h"
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#include "extmod/machine_i2c.h"
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@ -167,6 +168,7 @@ STATIC const mp_rom_map_elem_t machine_module_globals_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_disable_irq), MP_ROM_PTR(&machine_disable_irq_obj) },
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{ MP_ROM_QSTR(MP_QSTR_enable_irq), MP_ROM_PTR(&machine_enable_irq_obj) },
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{ MP_ROM_QSTR(MP_QSTR_time_pulse_us), MP_ROM_PTR(&machine_time_pulse_us_obj) },
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{ MP_ROM_QSTR(MP_QSTR_bitstream), MP_ROM_PTR(&machine_bitstream_obj) },
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};
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STATIC MP_DEFINE_CONST_DICT(machine_module_globals, machine_module_globals_table);
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@ -111,6 +111,7 @@
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#define MICROPY_PY_MACHINE_SPI (1)
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#define MICROPY_PY_MACHINE_SOFTSPI (1)
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#define MICROPY_PY_OS_DUPTERM (3)
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#define MICROPY_PY_MACHINE_BITSTREAM (1)
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#define MICROPY_PY_MACHINE_PULSE (1)
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#define MICROPY_PY_MACHINE_PWM (1)
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#define MICROPY_PY_MACHINE_PWM_INIT (0)
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@ -71,11 +71,11 @@ static inline mp_uint_t mp_hal_ticks_us(void) {
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#endif
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}
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#if defined (MCU_SAMD21)
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#if defined(MCU_SAMD21)
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#define mp_hal_ticks_cpu mp_hal_ticks_us
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#elif defined (MCU_SAMD51)
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#elif defined(MCU_SAMD51)
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static inline void mp_hal_ticks_cpu_enable(void) {
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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DWT->CYCCNT = 0;
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@ -111,7 +111,7 @@ void samd_init(void) {
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SysTick_Config(get_cpu_freq() / 1000);
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init_us_counter();
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usb_init();
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#if defined (MCU_SAMD51)
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#if defined(MCU_SAMD51)
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mp_hal_ticks_cpu_enable();
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#endif
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}
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