samd/machine_pin: Add pin.irq() to the machine.Pin class.
Its API conforms to the docs. There are 16 IRQ channels available, which will be used as assignable to the GPIO numbers. In most cases, the irq channel is GPIO_no % 16.
This commit is contained in:
robert-hh
Damien George
parent
a9eef1b276
commit
4b6f6ccf88
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@ -118,6 +118,7 @@ SRC_C = \
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lib/tinyusb/src/portable/microchip/samd/dcd_samd.c \
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lib/tinyusb/src/tusb.c \
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drivers/bus/softspi.c \
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shared/runtime/mpirq.c \
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shared/libc/printf.c \
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shared/libc/string0.c \
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shared/readline/readline.c \
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@ -148,6 +149,7 @@ SRC_QSTR += \
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modsamd.c \
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samd_flash.c \
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shared/readline/readline.c \
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shared/runtime/mpirq.c \
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SRC_QSTR += $(SRC_MOD) $(SRC_CXX)
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@ -4,6 +4,7 @@
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* The MIT License (MIT)
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*
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* Copyright (c) 2016-2021 Damien P. George
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* Copyright (c) 2022 Robert Hammelrath (pin.irq)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -29,10 +30,12 @@
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#include "string.h"
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#include "py/runtime.h"
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#include "py/mphal.h"
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#include "shared/runtime/mpirq.h"
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#include "extmod/virtpin.h"
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#include "modmachine.h"
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#include "samd_soc.h"
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#include "pins.h"
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#include "pin_af.h"
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#include "hal_gpio.h"
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@ -42,6 +45,17 @@
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#define GPIO_STRENGTH_2MA (0)
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#define GPIO_STRENGTH_8MA (1)
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#define GPIO_IRQ_EDGE_RISE (1)
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#define GPIO_IRQ_EDGE_FALL (2)
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typedef struct _machine_pin_irq_obj_t {
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mp_irq_obj_t base;
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uint32_t flags;
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uint32_t trigger;
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uint8_t pin_id;
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} machine_pin_irq_obj_t;
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STATIC const mp_irq_methods_t machine_pin_irq_methods;
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uint32_t machine_pin_open_drain_mask[4];
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@ -262,6 +276,141 @@ STATIC mp_obj_t machine_pin_drive(size_t n_args, const mp_obj_t *args) {
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}
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STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_pin_drive_obj, 1, 2, machine_pin_drive);
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// pin.irq(handler=None, trigger=IRQ_FALLING|IRQ_RISING, hard=False)
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STATIC mp_obj_t machine_pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
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enum { ARG_handler, ARG_trigger, ARG_hard };
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_handler, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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{ MP_QSTR_trigger, MP_ARG_INT, {.u_int = 3} },
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{ MP_QSTR_hard, MP_ARG_BOOL, {.u_bool = false} },
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};
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machine_pin_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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// Get the IRQ object.
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uint8_t eic_id = get_pin_af_info(self->id)->eic;
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machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[eic_id]);
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if (irq != NULL && irq->pin_id != self->id) {
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mp_raise_ValueError(MP_ERROR_TEXT("IRQ already used"));
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}
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// Allocate the IRQ object if it doesn't already exist.
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if (irq == NULL) {
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irq = m_new_obj(machine_pin_irq_obj_t);
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irq->base.base.type = &mp_irq_type;
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irq->base.methods = (mp_irq_methods_t *)&machine_pin_irq_methods;
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irq->base.parent = MP_OBJ_FROM_PTR(self);
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irq->base.handler = mp_const_none;
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irq->base.ishard = false;
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irq->pin_id = 0xff;
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MP_STATE_PORT(machine_pin_irq_objects[eic_id]) = irq;
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}
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// (Re-)configure the irq.
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if (n_args > 1 || kw_args->used != 0) {
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// set the mux config of the pin.
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mp_hal_set_pin_mux(self->id, ALT_FCT_EIC);
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// Configure IRQ.
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#if defined(MCU_SAMD21)
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uint32_t irq_num = 4;
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// Disable all IRQs from the affected source while data is updated.
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NVIC_DisableIRQ(irq_num);
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// Disable EIC
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EIC->CTRL.bit.ENABLE = 0;
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while (EIC->STATUS.bit.SYNCBUSY != 0) {
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}
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EIC->INTENCLR.reg = (1 << eic_id);
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// Enable the clocks
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PM->APBAMASK.bit.EIC_ |= 1;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | EIC_GCLK_ID;
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#elif defined(MCU_SAMD51)
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uint32_t irq_num = eic_id + 12;
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// Disable all IRQs from the affected source while data is updated.
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NVIC_DisableIRQ(irq_num);
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// Disable EIC
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EIC->CTRLA.bit.ENABLE = 0;
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while (EIC->SYNCBUSY.bit.ENABLE != 0) {
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}
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EIC->INTENCLR.reg = (1 << eic_id);
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// Enable the clocks
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MCLK->APBAMASK.bit.EIC_ |= 1;
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GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK2;
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#endif
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// Clear the pending interrupts flag
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EIC->INTENCLR.reg = (1 << eic_id);
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// Update IRQ data.
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irq->base.handler = args[ARG_handler].u_obj;
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irq->base.ishard = args[ARG_hard].u_bool;
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irq->flags = 0;
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irq->trigger = args[ARG_trigger].u_int;
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irq->pin_id = self->id;
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// Enable IRQ if a handler is given.
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if (args[ARG_handler].u_obj != mp_const_none) {
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// Set EIC channel mode
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EIC->CONFIG[eic_id / 8].reg |= irq->trigger << ((eic_id % 8) * 4);
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EIC->INTENSET.reg = (1 << eic_id);
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EIC->INTFLAG.reg |= (1 << eic_id);
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}
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// Enable EIC (again)
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#if defined(MCU_SAMD21)
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EIC->CTRL.bit.ENABLE = 1;
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while (EIC->STATUS.bit.SYNCBUSY != 0) {
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}
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#elif defined(MCU_SAMD51)
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EIC->CTRLA.bit.ENABLE = 1;
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while (EIC->SYNCBUSY.bit.ENABLE != 0) {
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}
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#endif
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// Enable interrupt again
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NVIC_EnableIRQ(irq_num);
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}
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return MP_OBJ_FROM_PTR(irq);
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}
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STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_pin_irq_obj, 1, machine_pin_irq);
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void pin_irq_deinit_all(void) {
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EIC->INTENCLR.reg = 0xffff; // Disable all interrupts from the EIC.
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for (int i = 0; i < 16; i++) { // Clear all irq object pointers
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MP_STATE_PORT(machine_pin_irq_objects[i]) = NULL;
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}
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// Disable all irq's at the NVIC controller
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#if defined(MCU_SAMD21)
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NVIC_DisableIRQ(4);
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#elif defined(MCU_SAMD51)
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for (int i = 12; i < 20; i++) {
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NVIC_DisableIRQ(i);
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}
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#endif
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}
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// Common EIC handler for all events.
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void EIC_Handler() {
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uint32_t mask = 1;
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uint32_t isr = EIC->INTFLAG.reg;
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for (int eic_id = 0; eic_id < 16; eic_id++, mask <<= 1) {
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// Did the ISR fire?
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if (isr & mask) {
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EIC->INTFLAG.reg |= mask; // clear the ISR flag
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machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[eic_id]);
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if (irq != NULL) {
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irq->flags = irq->trigger;
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mp_irq_handler(&irq->base);
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break;
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}
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}
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}
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}
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STATIC const mp_rom_map_elem_t machine_pin_locals_dict_table[] = {
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// instance methods
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{ MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_pin_init_obj) },
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@ -273,6 +422,7 @@ STATIC const mp_rom_map_elem_t machine_pin_locals_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_toggle), MP_ROM_PTR(&machine_pin_toggle_obj) },
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{ MP_ROM_QSTR(MP_QSTR_disable), MP_ROM_PTR(&machine_pin_disable_obj) },
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{ MP_ROM_QSTR(MP_QSTR_drive), MP_ROM_PTR(&machine_pin_drive_obj) },
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{ MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&machine_pin_irq_obj) },
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// class constants
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{ MP_ROM_QSTR(MP_QSTR_IN), MP_ROM_INT(GPIO_MODE_IN) },
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@ -283,6 +433,8 @@ STATIC const mp_rom_map_elem_t machine_pin_locals_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_PULL_DOWN), MP_ROM_INT(GPIO_PULL_DOWN) },
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{ MP_ROM_QSTR(MP_QSTR_LOW_POWER), MP_ROM_INT(GPIO_STRENGTH_2MA) },
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{ MP_ROM_QSTR(MP_QSTR_HIGH_POWER), MP_ROM_INT(GPIO_STRENGTH_8MA) },
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{ MP_ROM_QSTR(MP_QSTR_IRQ_RISING), MP_ROM_INT(GPIO_IRQ_EDGE_RISE) },
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{ MP_ROM_QSTR(MP_QSTR_IRQ_FALLING), MP_ROM_INT(GPIO_IRQ_EDGE_FALL) },
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};
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STATIC MP_DEFINE_CONST_DICT(machine_pin_locals_dict, machine_pin_locals_dict_table);
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@ -292,10 +444,10 @@ STATIC mp_uint_t pin_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, i
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switch (request) {
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case MP_PIN_READ: {
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return gpio_get_pin_level(self->id);
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return mp_hal_pin_read(self->id);
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}
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case MP_PIN_WRITE: {
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gpio_set_pin_level(self->id, arg);
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mp_hal_pin_write(self->id, arg);
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return 0;
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}
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}
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@ -317,6 +469,48 @@ MP_DEFINE_CONST_OBJ_TYPE(
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locals_dict, &machine_pin_locals_dict
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);
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static uint8_t find_eic_id(int pin) {
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for (int eic_id = 0; eic_id < 16; eic_id++) {
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machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[eic_id]);
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if (irq != NULL && irq->pin_id == pin) {
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return eic_id;
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}
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}
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return 0xff;
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}
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STATIC mp_uint_t machine_pin_irq_trigger(mp_obj_t self_in, mp_uint_t new_trigger) {
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machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in);
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uint8_t eic_id = find_eic_id(self->id);
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if (eic_id != 0xff) {
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machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[eic_id]);
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EIC->INTENCLR.reg |= (1 << eic_id);
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irq->flags = 0;
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irq->trigger = new_trigger;
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EIC->INTENSET.reg |= (1 << eic_id);
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}
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return 0;
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}
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STATIC mp_uint_t machine_pin_irq_info(mp_obj_t self_in, mp_uint_t info_type) {
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machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in);
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uint8_t eic_id = find_eic_id(self->id);
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if (eic_id != 0xff) {
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machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[eic_id]);
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if (info_type == MP_IRQ_INFO_FLAGS) {
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return irq->flags;
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} else if (info_type == MP_IRQ_INFO_TRIGGERS) {
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return irq->trigger;
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}
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}
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return 0;
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}
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STATIC const mp_irq_methods_t machine_pin_irq_methods = {
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.trigger = machine_pin_irq_trigger,
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.info = machine_pin_irq_info,
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};
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mp_hal_pin_obj_t mp_hal_get_pin_obj(mp_obj_t obj) {
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if (!mp_obj_is_type(obj, &machine_pin_type)) {
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mp_raise_ValueError(MP_ERROR_TEXT("expecting a Pin"));
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@ -324,3 +518,5 @@ mp_hal_pin_obj_t mp_hal_get_pin_obj(mp_obj_t obj) {
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machine_pin_obj_t *pin = MP_OBJ_TO_PTR(obj);
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return pin->id;
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}
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MP_REGISTER_ROOT_POINTER(void *machine_pin_irq_objects[16]);
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@ -34,6 +34,7 @@
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extern uint8_t _sstack, _estack, _sheap, _eheap;
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extern void adc_deinit_all(void);
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extern void pin_irq_deinit_all(void);
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extern void pwm_deinit_all(void);
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void samd_main(void) {
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@ -65,6 +66,7 @@ void samd_main(void) {
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mp_printf(MP_PYTHON_PRINTER, "MPY: soft reboot\n");
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adc_deinit_all();
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pin_irq_deinit_all();
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pwm_deinit_all();
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gc_sweep_all();
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mp_deinit();
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@ -54,7 +54,7 @@
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#define MICROPY_PY_BUILTINS_HELP (1)
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#define MICROPY_PY_BUILTINS_HELP_TEXT samd_help_text
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#define MICROPY_PY_BUILTINS_HELP_MODULES (1)
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#define MICROPY_ENABLE_SCHEDULER (1)
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// fixes sys/usys import issue
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#define MICROPY_MODULE_WEAK_LINKS (1)
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// Control over Python builtins
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@ -104,6 +104,10 @@
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#define MICROPY_PY_MACHINE_PWM_DUTY_U16_NS (1)
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#define MICROPY_PY_MACHINE_PWM_INCLUDEFILE "ports/samd/machine_pwm.c"
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// Use VfsLfs's types for fileio/textio
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#define mp_type_fileio mp_type_vfs_lfs1_fileio
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#define mp_type_textio mp_type_vfs_lfs1_textio
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#define MP_STATE_PORT MP_STATE_VM
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// Miscellaneous settings
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@ -104,9 +104,6 @@ void SysTick_Handler(void) {
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// Temporary Handlers to allow builds.
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// Will be removed when the respecitve module is added.
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void EIC_Handler(void) {
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}
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void PendSV_Handler(void) {
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}
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