Commit Graph

26 Commits

Author SHA1 Message Date
Damien George 68d053c66e stm32/modmachine: Allow changing AHB and APB bus frequencies on STM32WB.
For now SYSCLK cannot be changed and must remain at 64MHz.
2020-06-02 10:48:49 +10:00
Damien George 69661f3343 all: Reformat C and Python source code with tools/codeformat.py.
This is run with uncrustify 0.70.1, and black 19.10b0.
2020-02-28 10:33:03 +11:00
Damien George af88e70414 stm32/powerctrl: Reenable PLL3 on H7 MCUs when waking from stop mode.
So that USB can work.
2020-01-31 23:25:18 +11:00
Damien George 2c8c2b935e stm32/powerctrl: Improve support for changing system freq on H7 MCUs.
This commit improves pllvalues.py to generate PLL values for H7 MCUs that
are valid (VCO in and out are in range) and extend for the entire range of
SYSCLK values up to 400MHz (up to 480MHz is currently unsupported).
2020-01-31 23:25:18 +11:00
Damien George 68db7e01d8 stm32/powerctrl: Enable overdrive on F7 when waking from stop mode.
Because if the SYSCLK is set to 180MHz or higher it will require this to be
on already.
2020-01-30 16:30:03 +11:00
Damien George 29b84ea798 stm32/powerctrl: Disable HSI if not needed to save a bit of power. 2020-01-30 16:29:45 +11:00
Damien George a542c6d7e0 stm32/powerctrl: For F7, allow PLLM!=HSE when setting PLLSAI to 48MHz.
PLLM is shared among all PLL blocks on F7 MCUs, and this calculation to
configure PLLSAI to have 48MHz on the P output previously assumed that PLLM
is equal to HSE (eg PLLM=25 for HSE=25MHz).  This commit relaxes this
assumption to allow other values of PLLM.
2020-01-29 16:49:13 +11:00
Jim Mussared 06661890de stm32/powerctrl: Fix machine.bootloader() for L0 MCUs. 2019-09-04 11:36:53 +10:00
Damien George 59b7166d87 stm32: Add initial support for STM32WBxx MCUs.
This new series of MCUs is similar to the L4 series with an additional
Cortex-M0 coprocessor.  The firmware for the wireless stack must be managed
separately and MicroPython does not currently interface to it.  Supported
features so far include: RTC, UART, USB, internal flash filesystem.
2019-07-17 16:33:31 +10:00
Damien George 21ecf8be5f stm32/powerctrl: Move L0's SystemClock_Config to powerctrlboot.c file. 2019-07-08 15:23:53 +10:00
Damien George 23d9c6a0fd stm32: Add initial support for STM32L0xx MCUs. 2019-07-05 17:24:59 +10:00
Damien George ea033bf25a stm32/powerctrl: Add hooks for a board to perform actions on sleep/wake. 2019-07-03 01:27:33 +10:00
Damien George 04c7cdb668 stm32: Enter bootloader via a system reset.
Entering a bootloader (ST system bootloader, or custom mboot) from software
by directly branching to it is not reliable, and the reliability of it
working can depend on the peripherals that were enabled by the application
code.  It's also not possible to branch to a bootloader if the WDT is
enabled (unless the bootloader has specific provisions to feed the WDT).

This patch changes the way a bootloader is entered from software by first
doing a complete system reset, then branching to the desired bootloader
early on in the start-up process.  The top two words of RAM (of the stack)
are reserved to store flags indicating that the bootloader should be
entered after a reset.
2019-06-25 14:15:49 +10:00
Damien George 3fbf32b947 stm32/powerctrl: Support changing frequency when HSI is clock source.
This patch makes pllvalues.py generate two tables: one for when HSI is used
and one for when HSE is used.  The correct table is then selected at
compile time via the existing MICROPY_HW_CLK_USE_HSI.
2019-05-02 13:00:00 +10:00
Damien George 8031b7a25c stm32/powerctrl: Deselect PLLSAI as 48MHz src before turning off PLLSAI.
On the STM32F722 (at least, but STM32F767 is not affected) the CK48MSEL bit
must be deselected before PLLSAION is turned off, or else the 48MHz
peripherals (RNG, SDMMC, USB) may get stuck without a clock source.

In such "lock up" cases it seems that these peripherals are still being
clocked from the PLLSAI even though the CK48MSEL bit is turned off.  A hard
reset does not get them out of this stuck state.  Enabling the PLLSAI and
then disabling it does get them out.  A test case to see this is:

    import machine, pyb
    for i in range(100):
        machine.freq(122_000000)
        machine.freq(120_000000)
        print(i, [pyb.rng() for _ in range(4)])

On occasion the RNG will just return 0's, but will get fixed again on the
next loop (when PLLSAI is enabled by the change to a SYSCLK of 122MHz).

Fixes issue #4696.
2019-04-29 16:31:32 +10:00
Damien George 8402c26cfa stm32/powerctrl: Enable EIWUP to ensure RTC wakes device from standby. 2019-04-18 17:15:11 +10:00
Francisco J. Manno f938e70c69 stm32: Add compile-time option to use HSI as clock source.
To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board
configuration file.  The default is to use HSE.

HSI has been made the default for the NUCLEO_F401RE board to serve as an
example, and because early revisions of this board need a hardware
modification to get HSE working.
2019-03-05 15:49:08 +11:00
Damien George c6365ffb92 stm32/powerctrl: Add support for standby mode on L4 MCUs.
This maps to machine.deepsleep() which is now supported.
2018-12-05 00:40:05 +11:00
Damien George afd1ce0c15 stm32/powerctrl: Disable IRQs during stop mode to allow reconfig on wake 2018-11-28 12:44:54 +11:00
Damien George 66ca8e9b2c stm32/powerctrl: Move (deep)sleep funcs from modmachine.c to powerctrl.c 2018-11-28 12:22:20 +11:00
Damien George 6ea6c7cc9e stm32/powerctrl: Don't configure clocks if already at desired frequency.
Configuring clocks is a critical operation and is best to avoid when
possible.  If the clocks really need to be reset to the same values then
one can pass in a slightly higher value, eg 168000001 Hz to get 168MHz.
2018-09-24 17:34:05 +10:00
Damien George bc54c57590 stm32/powerctrl: Optimise passing of default values to set_sysclk. 2018-09-24 17:34:05 +10:00
Damien George dae1635c71 stm32/powerctrl: Factor code that configures PLLSAI on F7 MCUs. 2018-09-24 17:34:05 +10:00
Damien George 90ea2c63a5 stm32/powerctrl: Factor code to set RCC PLL and use it in startup.
This ensures that on first boot the most optimal settings are used for the
voltage scaling and flash latency (for F7 MCUs).

This commit also provides more fine-grained control for the flash latency
settings.
2018-09-24 17:34:05 +10:00
Damien George 9e4812771b stm32/powerctrl: Fix configuring APB1/APB2 frequency when AHB also set.
APB1/APB2 are derived from AHB, so if the user sets AHB!=SYSCLK then the
APB1/APB2 dividers must be computed from the new AHB.
2018-09-24 14:51:17 +10:00
Damien George dff14c740b stm32/powerctrl: Move function to set SYSCLK into new powerctrl file.
Power and clock control is low-level functionality and it makes sense to
have it in a dedicated file, at least so it can be reused by other parts of
the code.
2018-09-24 14:18:18 +10:00