Commit Graph

687 Commits

Author SHA1 Message Date
Paul Sokolovsky
b9bad7ff92 unix/moduselect: Raise OSError(ENOENT) if obj to modify is not in poller
Previously, the function silently succeeded. The new behavior is consistent
with both baremetal uselect implementation and CPython 3.
2018-10-05 16:56:43 +10:00
Damien George
bbccb0f630 esp8266: Remove scanning of GC pointers in native code block.
The native code no longer holds live GC pointers so doesn't need to be
scanned.
2018-09-27 23:46:09 +10:00
Paul Sokolovsky
af2030dec6 unix/mpconfigport.h: Enable MICROPY_PY_UHASHLIB_MD5 for uhashlib.md5.
This will allow to e.g. implement HTTP Digest authentication.

Adds 540 bytes for x86_32, 332 for arm_thumb2 (for Unix port, which already
includes axTLS library).
2018-09-26 15:12:28 +10:00
Damien George
84090edaa3 stm32/mpconfigport.h: Enable math.factorial, optimised version. 2018-09-26 15:05:19 +10:00
Christopher Swenson
8c656754aa py/modmath: Add math.factorial, optimised and non-opt implementations.
This commit adds the math.factorial function in two variants:
- squared difference, which is faster than the naive version, relatively
  compact, and non-recursive;
- a mildly optimised recursive version, faster than the above one.

There are some more optimisations that could be done, but they tend to take
more code, and more storage space.  The recursive version seems like a
sensible compromise.

The new function is disabled by default, and uses the non-optimised version
by default if it is enabled.  The options are MICROPY_PY_MATH_FACTORIAL
and MICROPY_OPT_MATH_FACTORIAL.
2018-09-26 15:03:04 +10:00
Damien George
7b452e7466 stm32/usbd_conf: Allocate enough space in USB HS TX FIFO for CDC packet.
The CDC maximum packet size is 512 bytes, or 128 32-bit words, and the TX
FIFO must be configured to have at least this size.
2018-09-26 12:00:56 +10:00
Damien George
6ea6c7cc9e stm32/powerctrl: Don't configure clocks if already at desired frequency.
Configuring clocks is a critical operation and is best to avoid when
possible.  If the clocks really need to be reset to the same values then
one can pass in a slightly higher value, eg 168000001 Hz to get 168MHz.
2018-09-24 17:34:05 +10:00
Damien George
bc54c57590 stm32/powerctrl: Optimise passing of default values to set_sysclk. 2018-09-24 17:34:05 +10:00
Damien George
dae1635c71 stm32/powerctrl: Factor code that configures PLLSAI on F7 MCUs. 2018-09-24 17:34:05 +10:00
Damien George
90ea2c63a5 stm32/powerctrl: Factor code to set RCC PLL and use it in startup.
This ensures that on first boot the most optimal settings are used for the
voltage scaling and flash latency (for F7 MCUs).

This commit also provides more fine-grained control for the flash latency
settings.
2018-09-24 17:34:05 +10:00
Damien George
9e4812771b stm32/powerctrl: Fix configuring APB1/APB2 frequency when AHB also set.
APB1/APB2 are derived from AHB, so if the user sets AHB!=SYSCLK then the
APB1/APB2 dividers must be computed from the new AHB.
2018-09-24 14:51:17 +10:00
Damien George
dff14c740b stm32/powerctrl: Move function to set SYSCLK into new powerctrl file.
Power and clock control is low-level functionality and it makes sense to
have it in a dedicated file, at least so it can be reused by other parts of
the code.
2018-09-24 14:18:18 +10:00
Damien George
1acf58c08f stm32/modmachine: Re-enable PLLSAI[1] after waking from stop mode.
On F7s PLLSAI is used as a 48MHz clock source if the main PLL cannot
provide such a frequency, and on L4s PLLSAI1 is always used as a clock
source for the peripherals.  This commit makes sure these PLLs are
re-enabled upon waking from stop mode so the peripherals work.

See issues #4022 and #4178 (L4 specific).
2018-09-24 12:55:15 +10:00
Damien George
4df1943948 stm32/boards/NUCLEO_F091RC: Enable USART3-8 with default pins. 2018-09-21 14:04:33 +10:00
Damien George
cdc01408c7 stm32/uart: Add support for USART3-8 on F0 MCUs. 2018-09-21 14:02:54 +10:00
Andrew Leech
84f4d58479 stm32/dcmi: Add F4/F7/H7 hal files and dma definitions for DCMI periph. 2018-09-21 12:12:49 +10:00
Damien George
cb3c66e793 stm32/adc: Increase sample time for internal sensors on L4 MCUs.
They need time (around 4us for VREFINT) to obtain accurate results.

Fixes issue #4022.
2018-09-20 23:51:33 +10:00
Damien George
3220cedc31 stm32/adc: Fix ADC calibration scale for L4 MCUs, they use 3.0V. 2018-09-20 23:50:54 +10:00
Damien George
185716514f esp32/machine_rtc: Fix locals dict entry, init qstr points to init meth. 2018-09-20 17:52:16 +10:00
Damien George
56f275c0a2 stm32/Makefile: Include copysign.c in double precision float builds.
This is required for DEBUG=1 builds when MICROPY_FLOAT_IMPL=double.

Thanks to Andrew Leech.
2018-09-20 16:51:20 +10:00
Damien George
6623d7a88c unix/modjni: Get building under coverage and nanbox builds.
Changes made:
- make use of MP_OBJ_TO_PTR and MP_OBJ_FROM_PTR where necessary
- fix shadowing of index variable i, renamed to j
- fix type of above variable to size_t to prevent comparison warning
- fix shadowing of res variable
- use "(void)" instead of "()" for functions that take no arguments
2018-09-20 16:04:08 +10:00
Paul Sokolovsky
11573fcabd unix/modjni: Update .getiter signature to include mp_obj_iter_buf_t* .
And thus be buildable again.
2018-09-20 16:03:53 +10:00
Andrew Leech
17f7c683d2 stm32: Add support for STM32F765xx MCUs.
This part is functionally similar to STM32F767xx (they share a datasheet)
so support is generally comparable.  When adding board support the
stm32f767_af.csv and stm32f767.ld should be used.
2018-09-20 15:16:03 +10:00
Paul Sokolovsky
2da5d41350 py/objstr: Make % (__mod__) formatting operator configurable.
Default is enabled, disabled for minimal builds. Saves 1296 bytes on x86,
976 bytes on ARM.
2018-09-20 14:41:08 +10:00
Damien George
a5b583adfd stm32/boards/STM32F769DISC: Add optional support for external SDRAM. 2018-09-20 11:42:03 +10:00
Damien George
9639e0d26f stm32/sdram: Add support for 32-bit wide data bus and 256MB in MPU cfg. 2018-09-20 11:29:37 +10:00
Damien George
7c4f98db85 stm32/dma: Get DMA working on F0 MCUs.
Changes made:
- fix DMA_SUB_INSTANCE_AS_UINT8
- fix dma_id numbers in dma_descr_t
- add F0 DMA IRQ handlers
- set DmaBaseAddress and ChannelIndex when reinit'ing
2018-09-16 23:16:10 +10:00
Siarhei Farbotka
e62f59217b esp32: Fix int overflow in machine.sleep/deepsleep functions. 2018-09-14 13:25:45 +10:00
Paul Sokolovsky
064b8e0e8d unix/modos: Include extmod/vfs.h for MP_S_IFDIR, etc.
If DTTOIF() macro is not defined, the code refers to MP_S_IFDIR, etc.
symbols defined in extmod/vfs.h, so should include it.

This fixes build for Android.
2018-09-14 13:22:50 +10:00
Paul Sokolovsky
0bce110872 zephyr/CMakeLists: Update for latest Zephyr CMake usage refactorings.
Added cmake_minimum_required and updated target_link_libraries directives.
2018-09-14 13:21:13 +10:00
Paul Sokolovsky
ed1a5bc88e zephyr/prj_base.conf: Update for net_config subsys refactor.
net_config subsystem was split off from net_app, and as a result, settings
need renaming from CONFIG_NET_APP_* to CONFIG_NET_CONFIG_*.
2018-09-14 13:21:13 +10:00
Damien George
9fb1f18cf4 stm32/sdcard: Fully reset SDMMC periph before calling HAL DMA functions.
The HAL DMA functions enable SDMMC interrupts before fully resetting the
peripheral, and this can lead to a DTIMEOUT IRQ during the initialisation
of the DMA transfer, which then clears out the DMA state and leads to the
read/write not working at all.  The DTIMEOUT is there from previous SDMMC
DMA transfers, even those that succeeded, and is of duration ~180 seconds,
which is 0xffffffff / 24MHz (default DTIMER value, and clock of
peripheral).

To work around this issue, fully reset the SDMMC peripheral before calling
the HAL SD DMA functions.

Fixes issue #4110.
2018-09-12 17:02:17 +10:00
Damien George
e6a6ded74e unix/mpconfigport_coverage.h: Enable uhashlib.md5. 2018-09-12 16:09:41 +10:00
Damien George
6b3d6da74b stm32/flashbdev: Protect flash writes from cache flushing and USB MSC. 2018-09-12 15:58:42 +10:00
Damien George
0941a467e7 stm32: Change flash IRQ priority from 2 to 6 to prevent preemption.
The flash-IRQ handler is used to flush the storage cache, ie write
outstanding block data from RAM to flash.  This is triggered by a timeout,
or by a direct call to flush all storage caches.

Prior to this commit, a timeout could trigger the cache flushing to occur
during the execution of a read/write to external SPI flash storage.  In
such a case the storage subsystem would break down.

SPI storage transfers are already protected against USB IRQs, so by
changing the priority of the flash IRQ to that of the USB IRQ (what is
done in this commit) the SPI transfers can be protected against any
timeouts triggering a cache flush (the cache flush would be postponed until
after the transfer finished, but note that in the case of SPI writes the
timeout is rescheduled after the transfer finishes).

The handling of internal flash sync'ing needs to be changed to directly
call flash_bdev_irq_handler() sync may be called with the IRQ priority
already raised (eg when called from a USB MSC IRQ handler).
2018-09-12 15:46:04 +10:00
Damien George
6f015d337d stm32/spi: Be sure to set all SPI config values in SPI proto init. 2018-09-11 17:36:11 +10:00
Damien George
c26516d40f stm32/sdcard: Move temporary DMA state from BSS to stack. 2018-09-11 17:23:27 +10:00
Damien George
e4f7001d9c stm32/sdcard: Use only a single DMA stream for both SDIO TX/RX.
No need to be wasteful on DMA resources.
2018-09-11 17:21:22 +10:00
Damien George
d7e2ac4a6a stm32/dma: Reinitialise the DMA if the direction changed on the channel. 2018-09-11 17:19:55 +10:00
Damien George
b0c8a94b41 stm32/dma: Pass DMA direction as parameter to dma_init not in cfg struct
Some DMA channels (eg for SDIO) can be used in both directions and this
patch allows such peripherals to dynamically select the DMA direction.
2018-09-11 17:18:06 +10:00
Damien George
47550ef2cd stm32: For MCUs that have PLLSAI allow to set SYSCLK at 2MHz increments.
MCUs that have a PLLSAI can use it to generate a 48MHz clock for USB, SDIO
and RNG peripherals.  In such cases the SYSCLK is not restricted to values
that allow the system PLL to generate 48MHz, but can be any frequency.
This patch allows such configurability for F7 MCUs, allowing the SYSCLK to
be set in 2MHz increments via machine.freq().  PLLSAI will only be enabled
if needed, and consumes about 1mA extra.  This fine grained control of
frequency is useful to get accurate SPI baudrates, for example.
2018-09-11 16:42:57 +10:00
roland
67ee4e2401 stm32/boards/STM32L476DISC: Enable external RTC xtal to get RTC working. 2018-09-11 15:23:19 +10:00
Andrew Leech
670a2a3396 stm32/Makefile: Allow external BOARD_DIR directory to be specified.
This makes it easy to add a custom board definition outside of the
micropython tree, keeping the micropython submodule clean and official.
2018-09-11 15:15:21 +10:00
Paul Sokolovsky
5615273bb0 unix/Makefile: Build libffi inside $BUILD.
Avoids polluting the source tree, allows to build for different (sub)archs
without intermediate cleaning.
2018-09-10 11:34:46 +03:00
Damien George
5cd2c7f2e7 esp8266/main: Increase heap by 2kb, now that axtls rodata is in ROM. 2018-09-08 00:09:03 +10:00
Damien George
eed83caf1d esp8266/Makefile: Remove build of libaxtls.a and add back tuned config. 2018-09-08 00:07:23 +10:00
Damien George
6ad5355e43 unix/Makefile: Remove building of libaxtls.a which is no longer needed. 2018-09-08 00:07:23 +10:00
Damien George
a23719e0ad stm32/mboot/main: Use correct formula for DFU download address.
As per ST's DfuSe specification, and following their example code.
2018-09-05 15:22:05 +10:00
Damien George
5f3016c663 stm32/mboot/Makefile: Use -Wno-attributes for ll_usb.c HAL source file.
A recent version of arm-none-eabi-gcc (8.2.0) will warn about unused packed
attributes in USB_WritePacket and USB_ReadPacket.  This patch suppresses
such warnings for this file only.
2018-09-05 15:21:43 +10:00
Damien George
056e0b6293 stm32/spi: Add implementation of low-level SPI protocol.
Can be used, for example, to configure external SPI flash using a hardware
SPI interface (code to be put in a board's bdev.c file):

    STATIC const spi_proto_cfg_t hard_spi_bus = {
        .spi = &spi_obj[5],
        .baudrate = 10000000,
        .polarity = 0,
        .phase = 0,
        .bits = 8,
        .firstbit = SPI_FIRSTBIT_MSB,
    };

    STATIC mp_spiflash_cache_t spi_bdev_cache;

    const mp_spiflash_config_t spiflash_config = {
        .bus_kind = MP_SPIFLASH_BUS_SPI,
        .bus.u_spi.cs = pin_A0,
        .bus.u_spi.data = (void*)&hard_spi_bus,
        .bus.u_spi.proto = &spi_proto,
        .cache = &spi_bdev_cache,
    };

    spi_bdev_t spi_bdev;
2018-08-14 22:10:43 +10:00