2019-06-28 15:36:08 -04:00
|
|
|
/*
|
|
|
|
* This file is part of the MicroPython project, http://micropython.org/
|
|
|
|
*
|
|
|
|
* The MIT License (MIT)
|
|
|
|
*
|
|
|
|
* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
|
2019-07-24 14:21:27 -04:00
|
|
|
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
|
2019-06-28 15:36:08 -04:00
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
|
|
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <stdint.h>
|
2021-08-19 15:18:13 -04:00
|
|
|
#include "supervisor/background_callback.h"
|
2020-12-02 21:05:29 -05:00
|
|
|
#include "supervisor/board.h"
|
2021-08-19 15:18:13 -04:00
|
|
|
#include "supervisor/port.h"
|
2019-07-18 17:55:57 -04:00
|
|
|
|
2019-09-12 13:47:01 -04:00
|
|
|
#include "common-hal/microcontroller/Pin.h"
|
2021-08-19 15:18:13 -04:00
|
|
|
#include "shared-bindings/microcontroller/__init__.h"
|
2020-04-13 12:03:05 -04:00
|
|
|
|
2021-03-06 02:20:16 -05:00
|
|
|
#ifdef CIRCUITPY_AUDIOPWMIO
|
|
|
|
#include "common-hal/audiopwmio/PWMAudioOut.h"
|
|
|
|
#endif
|
2020-04-13 12:03:05 -04:00
|
|
|
#if CIRCUITPY_BUSIO
|
2019-09-19 16:02:52 -04:00
|
|
|
#include "common-hal/busio/I2C.h"
|
2019-09-27 17:59:55 -04:00
|
|
|
#include "common-hal/busio/SPI.h"
|
2019-10-04 14:37:18 -04:00
|
|
|
#include "common-hal/busio/UART.h"
|
2020-04-13 12:03:05 -04:00
|
|
|
#endif
|
|
|
|
#if CIRCUITPY_PULSEIO
|
2020-02-29 14:44:33 -05:00
|
|
|
#include "common-hal/pulseio/PulseOut.h"
|
2020-03-10 17:16:31 -04:00
|
|
|
#include "common-hal/pulseio/PulseIn.h"
|
2020-08-18 16:08:33 -04:00
|
|
|
#endif
|
|
|
|
#if CIRCUITPY_PWMIO
|
|
|
|
#include "common-hal/pwmio/PWMOut.h"
|
|
|
|
#endif
|
|
|
|
#if CIRCUITPY_PULSEIO || CIRCUITPY_PWMIO
|
2021-03-11 17:50:05 -05:00
|
|
|
#include "peripherals/timers.h"
|
2020-03-17 18:26:13 -04:00
|
|
|
#endif
|
2020-06-26 11:13:02 -04:00
|
|
|
#if CIRCUITPY_SDIOIO
|
|
|
|
#include "common-hal/sdioio/SDCard.h"
|
|
|
|
#endif
|
2021-03-02 11:41:53 -05:00
|
|
|
#if CIRCUITPY_PULSEIO || CIRCUITPY_ALARM
|
2021-03-11 17:50:05 -05:00
|
|
|
#include "peripherals/exti.h"
|
2021-03-02 11:41:53 -05:00
|
|
|
#endif
|
2021-04-02 15:13:10 -04:00
|
|
|
#if CIRCUITPY_ALARM
|
|
|
|
#include "common-hal/alarm/__init__.h"
|
|
|
|
#endif
|
2022-06-07 16:39:31 -04:00
|
|
|
#if CIRCUITPY_RTC
|
|
|
|
#include "shared-bindings/rtc/__init__.h"
|
|
|
|
#endif
|
2019-07-18 17:55:57 -04:00
|
|
|
|
2021-03-11 17:50:05 -05:00
|
|
|
#include "peripherals/clocks.h"
|
|
|
|
#include "peripherals/gpio.h"
|
|
|
|
#include "peripherals/rtc.h"
|
2019-07-18 17:55:57 -04:00
|
|
|
|
2020-04-20 21:25:13 -04:00
|
|
|
#include STM32_HAL_H
|
|
|
|
|
2020-09-24 12:20:32 -04:00
|
|
|
void NVIC_SystemReset(void) NORETURN;
|
|
|
|
|
2020-06-09 18:01:52 -04:00
|
|
|
#if (CPY_STM32H7) || (CPY_STM32F7)
|
2020-04-02 16:15:12 -04:00
|
|
|
|
|
|
|
// Device memories must be accessed in order.
|
|
|
|
#define DEVICE 2
|
|
|
|
// Normal memory can have accesses reorder and prefetched.
|
|
|
|
#define NORMAL 0
|
|
|
|
// Prevents instruction access.
|
|
|
|
#define NO_EXECUTION 1
|
|
|
|
#define EXECUTION 0
|
|
|
|
// Shareable if the memory system manages coherency.
|
|
|
|
#define NOT_SHAREABLE 0
|
|
|
|
#define SHAREABLE 1
|
|
|
|
#define NOT_CACHEABLE 0
|
|
|
|
#define CACHEABLE 1
|
|
|
|
#define NOT_BUFFERABLE 0
|
|
|
|
#define BUFFERABLE 1
|
|
|
|
#define NO_SUBREGIONS 0
|
|
|
|
|
|
|
|
extern uint32_t _ld_stack_top;
|
|
|
|
|
|
|
|
extern uint32_t _ld_d1_ram_bss_start;
|
|
|
|
extern uint32_t _ld_d1_ram_bss_size;
|
|
|
|
extern uint32_t _ld_d1_ram_data_destination;
|
|
|
|
extern uint32_t _ld_d1_ram_data_size;
|
|
|
|
extern uint32_t _ld_d1_ram_data_flash_copy;
|
|
|
|
extern uint32_t _ld_dtcm_bss_start;
|
|
|
|
extern uint32_t _ld_dtcm_bss_size;
|
|
|
|
extern uint32_t _ld_dtcm_data_destination;
|
|
|
|
extern uint32_t _ld_dtcm_data_size;
|
|
|
|
extern uint32_t _ld_dtcm_data_flash_copy;
|
|
|
|
extern uint32_t _ld_itcm_destination;
|
|
|
|
extern uint32_t _ld_itcm_size;
|
|
|
|
extern uint32_t _ld_itcm_flash_copy;
|
|
|
|
|
|
|
|
extern void main(void);
|
|
|
|
extern void SystemInit(void);
|
|
|
|
|
2020-06-09 18:01:52 -04:00
|
|
|
// This replaces the Reset_Handler in gcc/startup_*.s, calls SystemInit from system_*.c
|
2020-04-02 16:15:12 -04:00
|
|
|
__attribute__((used, naked)) void Reset_Handler(void) {
|
|
|
|
__disable_irq();
|
2021-03-15 09:57:36 -04:00
|
|
|
__set_MSP((uint32_t)&_ld_stack_top);
|
2020-04-02 16:15:12 -04:00
|
|
|
|
|
|
|
/* Disable MPU */
|
|
|
|
ARM_MPU_Disable();
|
|
|
|
|
|
|
|
// Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write
|
|
|
|
// protect it.
|
2021-03-15 09:57:36 -04:00
|
|
|
for (uint32_t i = 0; i < ((size_t)&_ld_itcm_size) / 4; i++) {
|
2020-04-02 16:15:12 -04:00
|
|
|
(&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i];
|
|
|
|
}
|
|
|
|
|
|
|
|
// The first number in RBAR is the region number. When searching for a policy, the region with
|
|
|
|
// the highest number wins. If none match, then the default policy set at enable applies.
|
|
|
|
|
2020-04-20 21:25:13 -04:00
|
|
|
// Mark all the flash the same until instructed otherwise.
|
2020-04-02 16:15:12 -04:00
|
|
|
MPU->RBAR = ARM_MPU_RBAR(11, 0x08000000U);
|
2020-06-09 18:01:52 -04:00
|
|
|
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_FLASH_REGION_SIZE);
|
2020-04-02 16:15:12 -04:00
|
|
|
|
|
|
|
// This the ITCM. Set it to read-only because we've loaded everything already and it's easy to
|
|
|
|
// accidentally write the wrong value to 0x00000000 (aka NULL).
|
|
|
|
MPU->RBAR = ARM_MPU_RBAR(12, 0x00000000U);
|
2020-06-09 18:01:52 -04:00
|
|
|
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_ITCM_REGION_SIZE);
|
2020-04-02 16:15:12 -04:00
|
|
|
|
|
|
|
// This the DTCM.
|
|
|
|
MPU->RBAR = ARM_MPU_RBAR(14, 0x20000000U);
|
2020-06-09 18:01:52 -04:00
|
|
|
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_DTCM_REGION_SIZE);
|
2020-04-02 16:15:12 -04:00
|
|
|
|
|
|
|
// This is AXI SRAM (D1).
|
2020-06-09 18:01:52 -04:00
|
|
|
MPU->RBAR = ARM_MPU_RBAR(15, CPY_SRAM_START_ADDR);
|
|
|
|
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, CPY_SRAM_SUBMASK, CPY_SRAM_REGION_SIZE);
|
2020-04-02 16:15:12 -04:00
|
|
|
|
|
|
|
/* Enable MPU */
|
|
|
|
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
2019-09-12 13:47:01 -04:00
|
|
|
|
2020-04-02 16:15:12 -04:00
|
|
|
// Copy all of the data to run from DTCM.
|
2021-03-15 09:57:36 -04:00
|
|
|
for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_data_size) / 4; i++) {
|
2020-04-02 16:15:12 -04:00
|
|
|
(&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i];
|
|
|
|
}
|
|
|
|
|
|
|
|
// Clear DTCM bss.
|
2021-03-15 09:57:36 -04:00
|
|
|
for (uint32_t i = 0; i < ((size_t)&_ld_dtcm_bss_size) / 4; i++) {
|
2020-04-02 16:15:12 -04:00
|
|
|
(&_ld_dtcm_bss_start)[i] = 0;
|
|
|
|
}
|
2019-07-18 17:55:57 -04:00
|
|
|
|
2020-04-02 16:15:12 -04:00
|
|
|
// Copy all of the data to run from D1 RAM.
|
2021-03-15 09:57:36 -04:00
|
|
|
for (uint32_t i = 0; i < ((size_t)&_ld_d1_ram_data_size) / 4; i++) {
|
2020-04-02 16:15:12 -04:00
|
|
|
(&_ld_d1_ram_data_destination)[i] = (&_ld_d1_ram_data_flash_copy)[i];
|
|
|
|
}
|
|
|
|
|
|
|
|
// Clear D1 RAM bss.
|
2021-03-15 09:57:36 -04:00
|
|
|
for (uint32_t i = 0; i < ((size_t)&_ld_d1_ram_bss_size) / 4; i++) {
|
2020-04-02 16:15:12 -04:00
|
|
|
(&_ld_d1_ram_bss_start)[i] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
SystemInit();
|
|
|
|
__enable_irq();
|
|
|
|
main();
|
|
|
|
}
|
2021-03-15 09:57:36 -04:00
|
|
|
#endif // end H7 specific code
|
2019-07-18 17:55:57 -04:00
|
|
|
|
2020-06-05 11:42:34 -04:00
|
|
|
// Low power clock variables
|
|
|
|
static volatile uint32_t systick_ms;
|
2020-03-23 17:46:25 -04:00
|
|
|
|
2019-06-28 15:36:08 -04:00
|
|
|
safe_mode_t port_init(void) {
|
2020-06-05 11:42:34 -04:00
|
|
|
HAL_Init(); // Turns on SysTick
|
2019-09-18 16:49:15 -04:00
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
2021-09-28 17:13:04 -04:00
|
|
|
|
feat: add Blues Swan R5 support
complete pin mapping for Feather pins
stubbed out files needed for complilation. still to be modified
0 out all CPY modules in mpconfigboard.mk until we get the build running
add csv for pin generation for STM32L4R5
add F4R5 references in peripherals files
refactored out board files BECAUSE I AM AN IDIOT; add L4 series system clocks file from CubeMX
took a guess at the number of USB endpoint pairs to get the build done
guess was close, but wrong. It is 8
clean up peripheral DEFs
Fixes build error:
```
In file included from ../../py/mpstate.h:33,
from ../../py/mpstate.c:27:
../../py/misc.h: In function 'vstr_str':
../../py/misc.h:196:1: sorry, unimplemented: Thumb-1 hard-float VFP ABI
static inline char *vstr_str(vstr_t *vstr) {
^~~~~~
```
Sleuthing steps:
* verify that the feather_stm32f4_express board builds correctly
* put a `#error` at the bottom of the `mpstate.c` file.
* build for the feather and swan boards, with V=2 to capture the build command for that file.
* use a differencing tool to inspect the differences between the two invocations
* inspecting the differences, I saw a missing `-mcpu=cortex-m4` I tested by adding that to the Swan build command. The file built fine (stopping at the hard error, but no other warnings.)
A grep through the sources revealed where this flag was being set for the stm ports.
With this commit, the build gets further, but does not complete. The next exciting episode in this unfolding coding saga is just a commit away!
working build with minimal set of modules for the Blues Swan r5
chore:change header copyright name to Blues Wireless Contributors
USB operational. Fixed up clocks to be hardwired for LSE no HSE case. (Trying to combine HSE in there made the code much more complex, and I don't have a board to test it out on.)
USART working
adds support for `ENABLE_3V3` and `DISCHARGE_3V3` pins. I am surprised that pin definitions are quite low-level and don't include default direction and state, so the code currently has to initialize `ENABLE_3V3` pin as output. The LED takes over a second to discharge, so I wonder if the board startup code is not having the desired affect.
short circuit implementation of backup memory for the STM32L4
all the ports
remove company name from board name to be consistent with the Arduino board definition.
add default pins for I2C, SPI and UART, so that `board.I2C` et al. works as expected. Confirmed I2C timing.
fix board name
fix incorrect pin definition. add test to allow manual check of each output pin
analog IO
code changes for WebUSB. Doesn't appear to work, will revisit later.
ensure that `sys.platform` is available
checkin missing file
feat: make room for a larger filesystem so the sensor tutorial will fit on the device.
fix:(stm32l4r5zi.csv): merged AF0-7 and AF8-15 into single lines and removed extraneous headers mixed in with the data.
fix(parse_af_csv.py): pin index in the csv is 0 not 1, and AF index made 1 larger
chore(Swan R5): update peripherals pins from `parse_af_csv.py` output
optimize flash sector access
2021-07-29 18:06:31 -04:00
|
|
|
#if CPY_STM32F4 || CPY_STM32L4
|
2021-03-15 09:57:36 -04:00
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
2021-04-01 20:53:25 -04:00
|
|
|
HAL_PWR_EnableBkUpAccess();
|
2021-04-02 15:13:10 -04:00
|
|
|
|
2021-04-02 17:25:17 -04:00
|
|
|
#if CIRCUITPY_ALARM
|
2021-04-02 15:13:10 -04:00
|
|
|
// TODO: don't reset RTC entirely and move this back to alarm
|
|
|
|
if (STM_ALARM_FLAG & 0x01) {
|
|
|
|
// We've woken from deep sleep. Was it the WKUP pin or the RTC?
|
|
|
|
if (RTC->ISR & RTC_FLAG_ALRBF) {
|
|
|
|
// Alarm B is the deep sleep alarm
|
|
|
|
alarm_set_wakeup_reason(STM_WAKEUP_RTC);
|
|
|
|
} else {
|
|
|
|
alarm_set_wakeup_reason(STM_WAKEUP_GPIO);
|
|
|
|
}
|
|
|
|
}
|
2021-04-02 17:25:17 -04:00
|
|
|
#endif
|
2021-04-21 17:34:13 -04:00
|
|
|
|
2021-03-21 13:15:44 -04:00
|
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
|
|
|
2021-04-29 14:48:16 -04:00
|
|
|
#endif
|
|
|
|
|
2020-03-17 18:26:13 -04:00
|
|
|
stm32_peripherals_clocks_init();
|
|
|
|
stm32_peripherals_gpio_init();
|
2021-03-11 17:50:05 -05:00
|
|
|
stm32_peripherals_rtc_init();
|
2020-04-08 17:41:57 -04:00
|
|
|
|
2021-03-21 13:15:44 -04:00
|
|
|
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
|
2021-04-02 15:13:10 -04:00
|
|
|
stm32_peripherals_rtc_reset_alarms();
|
2021-03-21 13:15:44 -04:00
|
|
|
|
2020-06-05 11:42:34 -04:00
|
|
|
// Turn off SysTick
|
|
|
|
SysTick->CTRL = 0;
|
|
|
|
|
2023-02-11 23:50:20 -05:00
|
|
|
return SAFE_MODE_NONE;
|
2019-06-28 15:36:08 -04:00
|
|
|
}
|
|
|
|
|
2020-06-05 11:42:34 -04:00
|
|
|
void HAL_Delay(uint32_t delay_ms) {
|
|
|
|
if (SysTick->CTRL != 0) {
|
|
|
|
// SysTick is on, so use it
|
|
|
|
uint32_t tickstart = systick_ms;
|
|
|
|
while (systick_ms - tickstart < delay_ms) {
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
mp_hal_delay_ms(delay_ms);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t HAL_GetTick() {
|
|
|
|
if (SysTick->CTRL != 0) {
|
|
|
|
return systick_ms;
|
|
|
|
} else {
|
|
|
|
uint8_t subticks;
|
|
|
|
uint32_t result = (uint32_t)port_get_raw_ticks(&subticks);
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-20 15:58:34 -04:00
|
|
|
void SysTick_Handler(void) {
|
2020-06-05 11:42:34 -04:00
|
|
|
systick_ms += 1;
|
2020-03-20 15:58:34 -04:00
|
|
|
// Read the CTRL register to clear the SysTick interrupt.
|
|
|
|
SysTick->CTRL;
|
|
|
|
}
|
|
|
|
|
2019-06-28 15:36:08 -04:00
|
|
|
void reset_port(void) {
|
2019-11-12 11:26:14 -05:00
|
|
|
reset_all_pins();
|
2022-09-12 09:48:41 -04:00
|
|
|
|
2022-06-07 16:39:31 -04:00
|
|
|
#if CIRCUITPY_RTC
|
|
|
|
rtc_reset();
|
|
|
|
#endif
|
|
|
|
|
2021-03-06 02:20:16 -05:00
|
|
|
#if CIRCUITPY_AUDIOPWMIO
|
|
|
|
audiopwmout_reset();
|
|
|
|
#endif
|
2021-03-15 09:57:36 -04:00
|
|
|
#if CIRCUITPY_BUSIO
|
2019-09-19 16:02:52 -04:00
|
|
|
i2c_reset();
|
2019-09-27 17:59:55 -04:00
|
|
|
spi_reset();
|
2019-10-04 14:37:18 -04:00
|
|
|
uart_reset();
|
2021-03-15 09:57:36 -04:00
|
|
|
#endif
|
|
|
|
#if CIRCUITPY_SDIOIO
|
2020-06-26 11:13:02 -04:00
|
|
|
sdioio_reset();
|
2021-03-15 09:57:36 -04:00
|
|
|
#endif
|
|
|
|
#if CIRCUITPY_PULSEIO || CIRCUITPY_PWMIO
|
2020-07-01 10:07:45 -04:00
|
|
|
timers_reset();
|
2021-03-15 09:57:36 -04:00
|
|
|
#endif
|
|
|
|
#if CIRCUITPY_PULSEIO
|
2020-02-29 14:44:33 -05:00
|
|
|
pulseout_reset();
|
2020-03-10 17:16:31 -04:00
|
|
|
pulsein_reset();
|
2021-03-15 09:57:36 -04:00
|
|
|
#endif
|
|
|
|
#if CIRCUITPY_PWMIO
|
2020-08-18 16:08:33 -04:00
|
|
|
pwmout_reset();
|
2021-03-15 09:57:36 -04:00
|
|
|
#endif
|
2021-03-29 12:27:25 -04:00
|
|
|
#if CIRCUITPY_PULSEIO || CIRCUITPY_ALARM
|
2021-05-10 18:04:43 -04:00
|
|
|
exti_reset();
|
2021-03-29 12:27:25 -04:00
|
|
|
#endif
|
2019-06-28 15:36:08 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
void reset_to_bootloader(void) {
|
2022-09-18 10:51:12 -04:00
|
|
|
|
|
|
|
/*
|
|
|
|
From STM AN2606:
|
|
|
|
Before jumping to bootloader user must:
|
|
|
|
• Disable all peripheral clocks
|
|
|
|
• Disable used PLL
|
|
|
|
• Disable interrupts
|
|
|
|
• Clear pending interrupts
|
|
|
|
System memory boot mode can be exited by getting out from bootloader activation
|
|
|
|
condition and generating hardware reset or using Go command to execute user code
|
|
|
|
*/
|
|
|
|
HAL_RCC_DeInit();
|
|
|
|
HAL_DeInit();
|
|
|
|
|
2022-09-25 13:49:46 -04:00
|
|
|
// Disable all pending interrupts using NVIC
|
2022-09-29 16:10:21 -04:00
|
|
|
for (uint8_t i = 0; i < MP_ARRAY_SIZE(NVIC->ICER); ++i) {
|
2022-09-25 13:49:46 -04:00
|
|
|
NVIC->ICER[i] = 0xFFFFFFFF;
|
|
|
|
}
|
2022-09-18 10:51:12 -04:00
|
|
|
|
2022-09-25 13:49:46 -04:00
|
|
|
// if it is necessary to ensure an interrupt will not be triggered after disabling it in the NVIC,
|
|
|
|
// add a DSB instruction and then an ISB instruction. (ARM Cortex™-M Programming Guide to
|
|
|
|
// Memory Barrier Instructions, 4.6 Disabling Interrupts using NVIC)
|
|
|
|
__DSB();
|
|
|
|
__ISB();
|
|
|
|
|
|
|
|
// Clear all pending interrupts using NVIC
|
2022-09-29 16:10:21 -04:00
|
|
|
for (uint8_t i = 0; i < MP_ARRAY_SIZE(NVIC->ICPR); ++i) {
|
2022-09-18 10:51:12 -04:00
|
|
|
NVIC->ICPR[i] = 0xFFFFFFFF;
|
|
|
|
}
|
2022-09-25 13:49:46 -04:00
|
|
|
|
2022-09-18 10:51:12 -04:00
|
|
|
// information about jump addresses has been taken from STM AN2606.
|
|
|
|
#if defined(STM32F4)
|
|
|
|
__set_MSP(*((uint32_t *)0x1FFF0000));
|
|
|
|
((void (*)(void)) * ((uint32_t *)0x1FFF0004))();
|
|
|
|
#else
|
|
|
|
// DFU mode for STM32 variant note implemented.
|
2020-09-24 12:20:32 -04:00
|
|
|
NVIC_SystemReset();
|
2022-09-18 10:51:12 -04:00
|
|
|
#endif
|
|
|
|
|
|
|
|
while (true) {
|
|
|
|
asm ("nop;");
|
|
|
|
}
|
2019-06-28 15:36:08 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
void reset_cpu(void) {
|
2019-11-12 11:26:14 -05:00
|
|
|
NVIC_SystemReset();
|
2019-06-28 15:36:08 -04:00
|
|
|
}
|
|
|
|
|
2020-04-02 16:15:12 -04:00
|
|
|
extern uint32_t _ld_heap_start, _ld_heap_end, _ld_stack_top, _ld_stack_bottom;
|
|
|
|
|
2020-01-18 21:06:56 -05:00
|
|
|
uint32_t *port_heap_get_bottom(void) {
|
2020-04-02 16:15:12 -04:00
|
|
|
return &_ld_heap_start;
|
2020-01-18 21:06:56 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t *port_heap_get_top(void) {
|
2020-04-02 16:15:12 -04:00
|
|
|
return &_ld_heap_end;
|
2020-01-18 21:06:56 -05:00
|
|
|
}
|
|
|
|
|
2020-10-11 08:59:33 -04:00
|
|
|
bool port_has_fixed_stack(void) {
|
|
|
|
return false;
|
2020-05-15 19:22:33 -04:00
|
|
|
}
|
|
|
|
|
2019-10-18 05:00:09 -04:00
|
|
|
uint32_t *port_stack_get_limit(void) {
|
2020-04-20 21:25:13 -04:00
|
|
|
return &_ld_stack_bottom;
|
2019-10-18 05:00:09 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t *port_stack_get_top(void) {
|
2020-04-02 16:15:12 -04:00
|
|
|
return &_ld_stack_top;
|
2019-10-18 05:00:09 -04:00
|
|
|
}
|
|
|
|
|
2019-06-28 15:36:08 -04:00
|
|
|
extern uint32_t _ebss;
|
2020-04-15 10:18:09 -04:00
|
|
|
|
2019-06-28 15:36:08 -04:00
|
|
|
// Place the word to save just after our BSS section that gets blanked.
|
|
|
|
void port_set_saved_word(uint32_t value) {
|
|
|
|
_ebss = value;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t port_get_saved_word(void) {
|
|
|
|
return _ebss;
|
|
|
|
}
|
|
|
|
|
2021-03-15 09:57:36 -04:00
|
|
|
__attribute__((used)) void MemManage_Handler(void) {
|
2023-02-11 23:50:20 -05:00
|
|
|
reset_into_safe_mode(SAFE_MODE_HARD_FAULT);
|
2020-04-02 16:15:12 -04:00
|
|
|
while (true) {
|
2021-03-15 09:57:36 -04:00
|
|
|
asm ("nop;");
|
2020-04-02 16:15:12 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-03-15 09:57:36 -04:00
|
|
|
__attribute__((used)) void BusFault_Handler(void) {
|
2023-02-11 23:50:20 -05:00
|
|
|
reset_into_safe_mode(SAFE_MODE_HARD_FAULT);
|
2020-04-02 16:15:12 -04:00
|
|
|
while (true) {
|
2021-03-15 09:57:36 -04:00
|
|
|
asm ("nop;");
|
2020-04-02 16:15:12 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-03-15 09:57:36 -04:00
|
|
|
__attribute__((used)) void UsageFault_Handler(void) {
|
2023-02-11 23:50:20 -05:00
|
|
|
reset_into_safe_mode(SAFE_MODE_HARD_FAULT);
|
2020-04-02 16:15:12 -04:00
|
|
|
while (true) {
|
2021-03-15 09:57:36 -04:00
|
|
|
asm ("nop;");
|
2020-04-02 16:15:12 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-03-15 09:57:36 -04:00
|
|
|
__attribute__((used)) void HardFault_Handler(void) {
|
2023-02-11 23:50:20 -05:00
|
|
|
reset_into_safe_mode(SAFE_MODE_HARD_FAULT);
|
2019-09-12 13:47:01 -04:00
|
|
|
while (true) {
|
2021-03-15 09:57:36 -04:00
|
|
|
asm ("nop;");
|
2019-09-12 13:47:01 -04:00
|
|
|
}
|
2019-08-14 13:14:42 -04:00
|
|
|
}
|
2020-03-20 15:58:34 -04:00
|
|
|
|
2021-05-10 18:04:43 -04:00
|
|
|
uint64_t port_get_raw_ticks(uint8_t *subticks) {
|
2021-03-11 17:50:05 -05:00
|
|
|
return stm32_peripherals_rtc_raw_ticks(subticks);
|
2020-03-20 15:58:34 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
// Enable 1/1024 second tick.
|
|
|
|
void port_enable_tick(void) {
|
2021-03-11 17:50:05 -05:00
|
|
|
stm32_peripherals_rtc_set_wakeup_mode_tick();
|
|
|
|
stm32_peripherals_rtc_assign_wkup_callback(supervisor_tick);
|
|
|
|
stm32_peripherals_rtc_enable_wakeup_timer();
|
2020-03-20 15:58:34 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
// Disable 1/1024 second tick.
|
|
|
|
void port_disable_tick(void) {
|
2021-03-11 17:50:05 -05:00
|
|
|
stm32_peripherals_rtc_disable_wakeup_timer();
|
2020-03-20 15:58:34 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
void port_interrupt_after_ticks(uint32_t ticks) {
|
2021-03-11 17:50:05 -05:00
|
|
|
stm32_peripherals_rtc_set_alarm(PERIPHERALS_ALARM_A, ticks);
|
2020-03-20 15:58:34 -04:00
|
|
|
}
|
|
|
|
|
2020-12-02 21:05:29 -05:00
|
|
|
void port_idle_until_interrupt(void) {
|
2020-03-20 15:58:34 -04:00
|
|
|
// Clear the FPU interrupt because it can prevent us from sleeping.
|
2021-03-15 09:57:36 -04:00
|
|
|
if (__get_FPSCR() & ~(0x9f)) {
|
|
|
|
__set_FPSCR(__get_FPSCR() & ~(0x9f));
|
|
|
|
(void)__get_FPSCR();
|
2020-03-20 15:58:34 -04:00
|
|
|
}
|
2021-03-11 17:50:05 -05:00
|
|
|
// The alarm might have triggered before we even reach the WFI
|
|
|
|
if (stm32_peripherals_rtc_alarm_triggered(PERIPHERALS_ALARM_A)) {
|
2020-04-08 17:41:57 -04:00
|
|
|
return;
|
|
|
|
}
|
2021-08-19 15:18:13 -04:00
|
|
|
common_hal_mcu_disable_interrupts();
|
|
|
|
if (!background_callback_pending()) {
|
|
|
|
__WFI();
|
|
|
|
}
|
|
|
|
common_hal_mcu_enable_interrupts();
|
2020-03-20 15:58:34 -04:00
|
|
|
}
|
|
|
|
|
2020-04-16 14:53:52 -04:00
|
|
|
// Required by __libc_init_array in startup code if we are compiling using
|
|
|
|
// -nostdlib/-nostartfiles.
|
2021-03-15 09:57:36 -04:00
|
|
|
void _init(void) {
|
2020-04-16 14:53:52 -04:00
|
|
|
|
|
|
|
}
|
2021-03-27 13:16:12 -04:00
|
|
|
|
|
|
|
#if CIRCUITPY_ALARM
|
|
|
|
// in case boards/xxx/board.c does not provide board_deinit()
|
|
|
|
MP_WEAK void board_deinit(void) {
|
|
|
|
}
|
|
|
|
#endif
|