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Add DTCM and ITCM support to F7 series

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This commit is contained in:
Lucian Copeland 2020-06-09 18:01:52 -04:00
parent 0ba541d498
commit b414f82669
8 changed files with 50 additions and 13 deletions
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10
ports/stm/boards/STM32F746xG_fs.ld
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@ -26,6 +26,11 @@
* THE SOFTWARE.
*/
/* Entry Point */
ENTRY(Reset_Handler)
_ld_default_stack_size = 24K;
/* Specify the memory areas */
MEMORY
{
@ -33,7 +38,8 @@ MEMORY
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 32K /* sector 0 */
FLASH_FS (rx) : ORIGIN = 0x08008000, LENGTH = 96K /* sectors 1,2,3 are 32K */
FLASH_FIRMWARE (rx) : ORIGIN = 0x08020000, LENGTH = 896K /* sector 4 is 128K, sectors 5,6,7 are 256K */
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 256K /* AXI SRAM */
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 16K
}
@ -44,7 +50,7 @@ _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
above last byte of RAM. Note that EABI requires the stack to be 8-byte
aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM);
_estack = ORIGIN(DTCM) + LENGTH(DTCM);
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);

11
ports/stm/boards/STM32F767_fs.ld
View File

@ -2,6 +2,11 @@
GNU linker script for STM32F767 with filesystem
*/
/* Entry Point */
ENTRY(Reset_Handler)
_ld_default_stack_size = 24K;
/* Specify the memory areas */
MEMORY
{
@ -9,7 +14,9 @@ MEMORY
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 32K /* sector 0 */
FLASH_FS (rx) : ORIGIN = 0x08008000, LENGTH = 96K /* sectors 1,2,3 are 32K */
FLASH_FIRMWARE (rx) : ORIGIN = 0x08020000, LENGTH = 1920K /* sector 4 is 128K, sectors 5,6,7 are 256K */
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
RAM (xrw) : ORIGIN = 0x20020000, LENGTH = 384K /* AXI SRAM */
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 16K
}
/* produce a link error if there is not this amount of RAM for these sections */
@ -19,7 +26,7 @@ _minimum_heap_size = 16K;
/* Define tho top end of the stack. The stack is full descending so begins just
above last byte of RAM. Note that EABI requires the stack to be 8-byte
aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM);
_estack = ORIGIN(DTCM) + LENGTH(DTCM);
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);

8
ports/stm/boards/nucleo_f746zg/mpconfigboard.h
View File

@ -33,6 +33,14 @@
#define FLASH_SIZE (0x100000)
#define FLASH_PAGE_SIZE (0x4000)
// H7 and F7 MPU definitions
#define CPY_FLASH_REGION_SIZE ARM_MPU_REGION_SIZE_1MB
#define CPY_ITCM_REGION_SIZE ARM_MPU_REGION_SIZE_16KB
#define CPY_DTCM_REGION_SIZE ARM_MPU_REGION_SIZE_128KB
#define CPY_SRAM_REGION_SIZE ARM_MPU_REGION_SIZE_256KB
#define CPY_SRAM_SUBMASK 0x00
#define CPY_SRAM_START_ADDR 0x20010000
#define HSE_VALUE ((uint32_t)8000000)
#define LSE_VALUE ((uint32_t)32768)
#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal

2
ports/stm/boards/nucleo_f746zg/mpconfigboard.mk
View File

@ -10,5 +10,5 @@ MCU_SERIES = F7
MCU_VARIANT = STM32F746xx
MCU_PACKAGE = LQFP144
LD_COMMON = boards/common_default.ld
LLD_COMMON = boards/common_tcm.ld
LD_FILE = boards/STM32F746xG_fs.ld

8
ports/stm/boards/nucleo_f767zi/mpconfigboard.h
View File

@ -32,6 +32,14 @@
#define FLASH_SIZE (0x200000)
#define FLASH_PAGE_SIZE (0x4000)
// H7 and F7 MPU definitions
#define CPY_FLASH_REGION_SIZE ARM_MPU_REGION_SIZE_2MB
#define CPY_ITCM_REGION_SIZE ARM_MPU_REGION_SIZE_16KB
#define CPY_DTCM_REGION_SIZE ARM_MPU_REGION_SIZE_128KB
#define CPY_SRAM_REGION_SIZE ARM_MPU_REGION_SIZE_512KB
#define CPY_SRAM_SUBMASK 0xFC // Mask 512 to 384
#define CPY_SRAM_START_ADDR 0x20020000
#define HSE_VALUE ((uint32_t)8000000)
#define LSE_VALUE ((uint32_t)32768)
#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal

2
ports/stm/boards/nucleo_f767zi/mpconfigboard.mk
View File

@ -10,5 +10,5 @@ MCU_SERIES = F7
MCU_VARIANT = STM32F767xx
MCU_PACKAGE = LQFP144
LD_COMMON = boards/common_default.ld
LD_COMMON = boards/common_tcm.ld
LD_FILE = boards/STM32F767_fs.ld

8
ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h
View File

@ -31,6 +31,14 @@
#define FLASH_PAGE_SIZE (0x4000)
// H7 and F7 MPU definitions
#define CPY_FLASH_REGION_SIZE ARM_MPU_REGION_SIZE_2MB
#define CPY_ITCM_REGION_SIZE ARM_MPU_REGION_SIZE_64KB
#define CPY_DTCM_REGION_SIZE ARM_MPU_REGION_SIZE_128KB
#define CPY_SRAM_REGION_SIZE ARM_MPU_REGION_SIZE_512KB
#define CPY_SRAM_SUBMASK 0x00
#define CPY_SRAM_START_ADDR 0x24000000
#define HSE_VALUE ((uint32_t)8000000)
#define LSE_VALUE ((uint32_t)32768)
#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal

14
ports/stm/supervisor/port.c
View File

@ -49,7 +49,7 @@
#include STM32_HAL_H
//only enable the Reset Handler overwrite for the H7 for now
#if (CPY_STM32H7)
#if (CPY_STM32H7) || (CPY_STM32F7)
// Device memories must be accessed in order.
#define DEVICE 2
@ -86,7 +86,7 @@ extern uint32_t _ld_itcm_flash_copy;
extern void main(void);
extern void SystemInit(void);
// This replaces the Reset_Handler in startup_*.S and SystemInit in system_*.c.
// This replaces the Reset_Handler in gcc/startup_*.s, calls SystemInit from system_*.c
__attribute__((used, naked)) void Reset_Handler(void) {
__disable_irq();
__set_MSP((uint32_t) &_ld_stack_top);
@ -105,20 +105,20 @@ __attribute__((used, naked)) void Reset_Handler(void) {
// Mark all the flash the same until instructed otherwise.
MPU->RBAR = ARM_MPU_RBAR(11, 0x08000000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_2MB);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_FLASH_REGION_SIZE);
// This the ITCM. Set it to read-only because we've loaded everything already and it's easy to
// accidentally write the wrong value to 0x00000000 (aka NULL).
MPU->RBAR = ARM_MPU_RBAR(12, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_64KB);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_ITCM_REGION_SIZE);
// This the DTCM.
MPU->RBAR = ARM_MPU_RBAR(14, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_128KB);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_DTCM_REGION_SIZE);
// This is AXI SRAM (D1).
MPU->RBAR = ARM_MPU_RBAR(15, 0x24000000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512KB);
MPU->RBAR = ARM_MPU_RBAR(15, CPY_SRAM_START_ADDR);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, CPY_SRAM_SUBMASK, CPY_SRAM_REGION_SIZE);
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);