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circuitpython/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h

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mimxrt/boards: Integrate support for MIMXRT1020_EVK board.
2020-04-14 15:08:59 -04:00
#define MICROPY_HW_BOARD_NAME "i.MX RT1020 EVK"
#define MICROPY_HW_MCU_NAME "MIMXRT1021DAG5A"
// i.MX RT1020 EVK has 1 board LED
mimxrt: Implement machine.Pin class. - modified pin type from pin_obj_t to machine_pin_obj_t - created machine_pin.c - implemented basic version of make-pins.py to genertate pins.c/.h files automatically; the only alternate function currently supported is GPIO - added af.csv files for all supported MCUs - replaced pins.c/pins.h files with pin.csv for all boards - implemented on/off/high/low/value/init methods - Implemented IN/OUT/OPEN_DRAIN modes - modified LDFLAGS for DEBUG build to get usefull .elf file for debugging Signed-off-by: Philipp Ebensberger
2020-08-21 10:03:21 -04:00
// Todo: think about replacing the define with searching in the generated pins?
#define MICROPY_HW_LED1_PIN (pin_GPIO_AD_B0_05)
mimxrt/boards: Integrate support for MIMXRT1020_EVK board.
2020-04-14 15:08:59 -04:00
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
mimxrt/machine_uart: Add the UART class to the machine module. The implementation uses the LPUARTx devices. Up to 8 UARTs can be used, given that the pins are accessible. E.g. 8 on Teensy 4.1, 5 on MIMXRT1020_EVK. For Tennsy 4.0 and 4.1 the UART numbers are as printed on the pinout 1..N. The MIMXRT10xx-EVK boards have only one UART named, which gets the number 1. All other UART are assigned to different Pins: MIMXRT1010-EVK: D0/D1 UART 1 D6/D7 UART 2 A0/D4 UART 3 MIMXRT1020-EVK: D0/D1 UART 1 D6/D9 UART 2 D10/D12 UART 3 D14/D15 UART 4 A0/A1 UART 5 MIMXRT1050-EVK, MIMXRT1060-EVK, MIMXRT1064-EVK: D0/D1 UART 1 D7/D6 UART 2 D8/D9 UART 3 A1/A0 UART 4
2021-05-30 12:18:33 -04:00
mimxrt/machine_pin: Implement pin.irq() functionality.
2021-06-05 08:06:04 -04:00
#define MICROPY_HW_NUM_PIN_IRQS (3 * 32)
mimxrt/machine_uart: Add the UART class to the machine module. The implementation uses the LPUARTx devices. Up to 8 UARTs can be used, given that the pins are accessible. E.g. 8 on Teensy 4.1, 5 on MIMXRT1020_EVK. For Tennsy 4.0 and 4.1 the UART numbers are as printed on the pinout 1..N. The MIMXRT10xx-EVK boards have only one UART named, which gets the number 1. All other UART are assigned to different Pins: MIMXRT1010-EVK: D0/D1 UART 1 D6/D7 UART 2 A0/D4 UART 3 MIMXRT1020-EVK: D0/D1 UART 1 D6/D9 UART 2 D10/D12 UART 3 D14/D15 UART 4 A0/A1 UART 5 MIMXRT1050-EVK, MIMXRT1060-EVK, MIMXRT1064-EVK: D0/D1 UART 1 D7/D6 UART 2 D8/D9 UART 3 A1/A0 UART 4
2021-05-30 12:18:33 -04:00
// Define mapping logical UART # to hardware UART #
mimxrt: Define UART 0 on MIMXRT boards. UART 0 is attached to the Debug USB port. The settings are 115200 Baud, 8N1. For MIMXRT1010_EVK this is identical to UART1. For the other boards, this is an additional UART.
2021-11-03 10:57:48 -04:00
// RX/TX HW-UART Logical UART
// DEBUG USB LPUART1 -> 0
// D3/D5 LPUART1 Not usable, Since D3 is blocked.
// D0/D1 LPUART2 -> 1
// D6/D9 LPUART3 -> 2
// D10/D12 LPUART5 -> 3
// D14/D15 LPUART8 -> 4
// A0/A1 LPUART4 -> 5
mimxrt/machine_uart: Add the UART class to the machine module. The implementation uses the LPUARTx devices. Up to 8 UARTs can be used, given that the pins are accessible. E.g. 8 on Teensy 4.1, 5 on MIMXRT1020_EVK. For Tennsy 4.0 and 4.1 the UART numbers are as printed on the pinout 1..N. The MIMXRT10xx-EVK boards have only one UART named, which gets the number 1. All other UART are assigned to different Pins: MIMXRT1010-EVK: D0/D1 UART 1 D6/D7 UART 2 A0/D4 UART 3 MIMXRT1020-EVK: D0/D1 UART 1 D6/D9 UART 2 D10/D12 UART 3 D14/D15 UART 4 A0/A1 UART 5 MIMXRT1050-EVK, MIMXRT1060-EVK, MIMXRT1064-EVK: D0/D1 UART 1 D7/D6 UART 2 D8/D9 UART 3 A1/A0 UART 4
2021-05-30 12:18:33 -04:00
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
mimxrt: Define UART 0 on MIMXRT boards. UART 0 is attached to the Debug USB port. The settings are 115200 Baud, 8N1. For MIMXRT1010_EVK this is identical to UART1. For the other boards, this is an additional UART.
2021-11-03 10:57:48 -04:00
#define MICROPY_HW_UART_INDEX { 1, 2, 3, 5, 8, 4 }
mimxrt/machine_uart: Add the UART class to the machine module. The implementation uses the LPUARTx devices. Up to 8 UARTs can be used, given that the pins are accessible. E.g. 8 on Teensy 4.1, 5 on MIMXRT1020_EVK. For Tennsy 4.0 and 4.1 the UART numbers are as printed on the pinout 1..N. The MIMXRT10xx-EVK boards have only one UART named, which gets the number 1. All other UART are assigned to different Pins: MIMXRT1010-EVK: D0/D1 UART 1 D6/D7 UART 2 A0/D4 UART 3 MIMXRT1020-EVK: D0/D1 UART 1 D6/D9 UART 2 D10/D12 UART 3 D14/D15 UART 4 A0/A1 UART 5 MIMXRT1050-EVK, MIMXRT1060-EVK, MIMXRT1064-EVK: D0/D1 UART 1 D7/D6 UART 2 D8/D9 UART 3 A1/A0 UART 4
2021-05-30 12:18:33 -04:00
#define IOMUX_TABLE_UART \
{ IOMUXC_GPIO_AD_B0_06_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_07_LPUART1_RX }, \
{ IOMUXC_GPIO_AD_B1_08_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_09_LPUART2_RX }, \
{ IOMUXC_GPIO_AD_B0_14_LPUART3_TX }, { IOMUXC_GPIO_AD_B0_15_LPUART3_RX }, \
{ IOMUXC_GPIO_AD_B1_10_LPUART4_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART4_RX }, \
{ IOMUXC_GPIO_AD_B0_10_LPUART5_TX }, { IOMUXC_GPIO_AD_B0_11_LPUART5_RX }, \
{ 0 }, { 0 }, \
{ 0 }, { 0 }, \
{ IOMUXC_GPIO_SD_B1_02_LPUART8_TX }, { IOMUXC_GPIO_SD_B1_03_LPUART8_RX },
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
#define MICROPY_HW_SPI_INDEX { 1, 3 }
#define IOMUX_TABLE_SPI \
{ IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK }, { IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 }, \
{ IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO }, { IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI }, \
mimxrt: Allow to select cs0 or cs1 for SPI. Using the keyword argument cs=nnn in the constructor. The cs1 pin has to be defined in mpconfigboard.h. Note: Only a few boards have the CS1 pin exposed to the connectors.
2022-01-10 12:14:40 -05:00
{ 0 }, \
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
{ 0 }, { 0 }, \
{ 0 }, { 0 }, \
mimxrt: Allow to select cs0 or cs1 for SPI. Using the keyword argument cs=nnn in the constructor. The cs1 pin has to be defined in mpconfigboard.h. Note: Only a few boards have the CS1 pin exposed to the connectors.
2022-01-10 12:14:40 -05:00
{ 0 }, \
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
{ IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK }, { IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 }, \
mimxrt: Allow to select cs0 or cs1 for SPI. Using the keyword argument cs=nnn in the constructor. The cs1 pin has to be defined in mpconfigboard.h. Note: Only a few boards have the CS1 pin exposed to the connectors.
2022-01-10 12:14:40 -05:00
{ IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO }, { IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI }, \
{ IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 } \
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
mimxrt: Rework flash configuration. - Moves definition of BOARD_FLASH_SIZE and other header files related to flash configuration into the Makefile. - Adds board specific clock_config.h. - Adds board.h, pin_mux.h, and peripherals.h as they are required by NXP MCU SDK in order to use our own clock_config.h. - Renames board specific FlexSPI configuration files. - Updates flash frequency of MIMXRT1020_EVK - Creates separated flash_config files for QSPI NOR and QSPI Hyper flash. - Unifies VFS start address to be @ 1M for 1010 and 1020 boards. - Unifies 1050EVK boards - Adds support to both NOR and HyperFlash on boards with both capabilities. - Adds automatic FlexRAM initialization to start-up code based on linker script and NXP HAL. - Applies code formatting to all files in mimxrt port. With this change the flash configuration is restructured and organized. This simplifies the configuration process and provides a better overview of each board's settings. With the integration of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better control of the settings and clock configurations. Furthermore the implementation of an explicit FlexRAM setup improves the system performance and allows for performance tuning. Signed-off-by: Philipp Ebensberger
2021-08-20 15:41:58 -04:00
kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }
mimxrt/machine_spi: Add the SPI class to the machine module. This class supports SPI bus controller mode, with blocking transfers. SPI device numbers start at 0, to comply with the pinout of the Teensy boards. With the configured clock frequency the fastest baud rate is 33MHz. For messages longer 16 bytes DMA is used. The class uses the existing framework with extmod/machine_spi.c. Extended driver options: - drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6. Since the pins used by the SPI are fixed, no Pin settings can be made. Thus the drive option is added allowing to control ringing and crosstalk on the connection. - gap_ns=nnnnn is the time between sent data items in a frame given in ns. Default is 2 clock cycles.
2021-06-09 04:47:18 -04:00
#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
mimxrt: Rework flash configuration. - Moves definition of BOARD_FLASH_SIZE and other header files related to flash configuration into the Makefile. - Adds board specific clock_config.h. - Adds board.h, pin_mux.h, and peripherals.h as they are required by NXP MCU SDK in order to use our own clock_config.h. - Renames board specific FlexSPI configuration files. - Updates flash frequency of MIMXRT1020_EVK - Creates separated flash_config files for QSPI NOR and QSPI Hyper flash. - Unifies VFS start address to be @ 1M for 1010 and 1020 boards. - Unifies 1050EVK boards - Adds support to both NOR and HyperFlash on boards with both capabilities. - Adds automatic FlexRAM initialization to start-up code based on linker script and NXP HAL. - Applies code formatting to all files in mimxrt port. With this change the flash configuration is restructured and organized. This simplifies the configuration process and provides a better overview of each board's settings. With the integration of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better control of the settings and clock configurations. Furthermore the implementation of an explicit FlexRAM setup improves the system performance and allows for performance tuning. Signed-off-by: Philipp Ebensberger
2021-08-20 15:41:58 -04:00
kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }
mimxrt/machine_i2c: Add hardware-based machine.I2C to machine module. It uses non-blocking transfer of data. Advantage over SoftI2C: - Higher data rate up to ~3 MHZ. - Full protocol support.
2021-06-19 16:09:40 -04:00
// Define mapping hardware I2C # to logical I2C #
// SDA/SCL HW-I2C Logical I2C
// D14/D15 LPI2C4 -> 0
// A4/A5 LPI2C1 -> 1
// D0/D1 LPI2C2 -> 2
#define MICROPY_HW_I2C_INDEX { 4, 1, 2 }
#define IOMUX_TABLE_I2C \
{ IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL }, { IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA }, \
{ IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL }, { IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA }, \
{ 0 }, { 0 }, \
{ IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL }, { IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA },
mimxrt/sdcard: Implement SDCard driver. - Configures `PLL2->PFD0` with **198MHz** as base clock of `USDHCx` peripheral. - Adds guards for SDCard related files via `MICROPY_PY_MACHINE_SDCARD` - Adds creation of pin defines for SDCard to make-pins.py - Adds new configuration option for SDCard peripheral pinout to mpconfigport.h - Adds interrupt handling support instead of polling - Adds support for `ADMA2` powered data transfer - Configures SDCard to run in HS (high-speed mode) with **50MHz** only! SDCard support is optional and requires `USDHC` peripheral. Thus this driver is not available on `MIMXRT1010_EVK`. SDCard support is enabled by setting `MICROPY_PY_MACHINE_SDCARD = 1` in mpconfigboard.mk. Signed-off-by: Philipp Ebensberger
2021-08-01 05:20:39 -04:00
mixmrt/machine_i2s: Add I2S protocol support. This commit adds support for machine.I2S on the mimxrt port. The I2S API is consistent with the existing stm32, esp32, and rp2 implementations. I2S features: - controller transmit and controller receive - 16-bit and 32-bit sample sizes - mono and stereo formats - sampling frequencies from 8kHz to 48kHz - 3 modes of operation: - blocking - non-blocking with callback - uasyncio - configurable internal buffer - optional MCK Tested with the following development boards: - MIMXRT1010_EVK, MIMXRT1015_EVK, MIMXRT1020_EVK, MIMXRT1050_EVK - Teensy 4.0, Teensy 4.1 - Olimex RT1010 - Seeed ARCH MIX Tested with the following I2S hardware peripherals: - UDA1334 - GY-SPH0645LM4H - WM8960 codec on board the MIMXRT boards and separate breakout board - INMP441 - PCM5102 - SGTL5000 on the Teensy audio shield Signed-off-by: Mike Teachman <mike.teachman@gmail.com>
2021-11-29 12:50:34 -05:00
#define MICROPY_PY_MACHINE_I2S (1)
#define MICROPY_HW_I2S_NUM (1)
#define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }
#define I2S_CLOCK_PRE_DIV { 0, kCLOCK_Sai1PreDiv, kCLOCK_Sai2PreDiv }
#define I2S_CLOCK_DIV { 0, kCLOCK_Sai1Div, kCLOCK_Sai2Div }
#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir }
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
mimxrt: Add support for MIMXRT1176 MCUs, and MIMXRT1170_EVK board. The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
2021-10-20 15:24:20 -04:00
#define I2S_AUDIO_PLL_CLOCK (2U)
mixmrt/machine_i2s: Add I2S protocol support. This commit adds support for machine.I2S on the mimxrt port. The I2S API is consistent with the existing stm32, esp32, and rp2 implementations. I2S features: - controller transmit and controller receive - 16-bit and 32-bit sample sizes - mono and stereo formats - sampling frequencies from 8kHz to 48kHz - 3 modes of operation: - blocking - non-blocking with callback - uasyncio - configurable internal buffer - optional MCK Tested with the following development boards: - MIMXRT1010_EVK, MIMXRT1015_EVK, MIMXRT1020_EVK, MIMXRT1050_EVK - Teensy 4.0, Teensy 4.1 - Olimex RT1010 - Seeed ARCH MIX Tested with the following I2S hardware peripherals: - UDA1334 - GY-SPH0645LM4H - WM8960 codec on board the MIMXRT boards and separate breakout board - INMP441 - PCM5102 - SGTL5000 on the Teensy audio shield Signed-off-by: Mike Teachman <mike.teachman@gmail.com>
2021-11-29 12:50:34 -05:00
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
{ \
.hw_id = _hwid, \
.fn = _fn, \
.mode = _mode, \
.name = MP_QSTR_##_pin, \
.iomux = {_iomux}, \
}
#define I2S_GPIO_MAP \
{ \
I2S_GPIO(1, MCK, TX, GPIO_AD_B1_00, IOMUXC_GPIO_AD_B1_00_SAI1_MCLK), \
I2S_GPIO(1, SCK, RX, GPIO_AD_B1_06, IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK), \
I2S_GPIO(1, WS, RX, GPIO_AD_B1_04, IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC), \
I2S_GPIO(1, SD, RX, GPIO_AD_B1_05, IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA00), \
I2S_GPIO(1, SCK, TX, GPIO_AD_B1_01, IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK), \
I2S_GPIO(1, WS, TX, GPIO_AD_B1_02, IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC), \
I2S_GPIO(1, SD, TX, GPIO_AD_B1_03, IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA00), \
}
mimxrt: Rework flash configuration. - Moves definition of BOARD_FLASH_SIZE and other header files related to flash configuration into the Makefile. - Adds board specific clock_config.h. - Adds board.h, pin_mux.h, and peripherals.h as they are required by NXP MCU SDK in order to use our own clock_config.h. - Renames board specific FlexSPI configuration files. - Updates flash frequency of MIMXRT1020_EVK - Creates separated flash_config files for QSPI NOR and QSPI Hyper flash. - Unifies VFS start address to be @ 1M for 1010 and 1020 boards. - Unifies 1050EVK boards - Adds support to both NOR and HyperFlash on boards with both capabilities. - Adds automatic FlexRAM initialization to start-up code based on linker script and NXP HAL. - Applies code formatting to all files in mimxrt port. With this change the flash configuration is restructured and organized. This simplifies the configuration process and provides a better overview of each board's settings. With the integration of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better control of the settings and clock configurations. Furthermore the implementation of an explicit FlexRAM setup improves the system performance and allows for performance tuning. Signed-off-by: Philipp Ebensberger
2021-08-20 15:41:58 -04:00
#define USDHC_DUMMY_PIN NULL, 0
mimxrt/sdcard: Implement SDCard driver. - Configures `PLL2->PFD0` with **198MHz** as base clock of `USDHCx` peripheral. - Adds guards for SDCard related files via `MICROPY_PY_MACHINE_SDCARD` - Adds creation of pin defines for SDCard to make-pins.py - Adds new configuration option for SDCard peripheral pinout to mpconfigport.h - Adds interrupt handling support instead of polling - Adds support for `ADMA2` powered data transfer - Configures SDCard to run in HS (high-speed mode) with **50MHz** only! SDCard support is optional and requires `USDHC` peripheral. Thus this driver is not available on `MIMXRT1010_EVK`. SDCard support is enabled by setting `MICROPY_PY_MACHINE_SDCARD = 1` in mpconfigboard.mk. Signed-off-by: Philipp Ebensberger
2021-08-01 05:20:39 -04:00
#define MICROPY_USDHC1 \
{ \
.cmd = {GPIO_SD_B0_02_USDHC1_CMD}, \
.clk = { GPIO_SD_B0_03_USDHC1_CLK }, \
mimxrt: Rework flash configuration. - Moves definition of BOARD_FLASH_SIZE and other header files related to flash configuration into the Makefile. - Adds board specific clock_config.h. - Adds board.h, pin_mux.h, and peripherals.h as they are required by NXP MCU SDK in order to use our own clock_config.h. - Renames board specific FlexSPI configuration files. - Updates flash frequency of MIMXRT1020_EVK - Creates separated flash_config files for QSPI NOR and QSPI Hyper flash. - Unifies VFS start address to be @ 1M for 1010 and 1020 boards. - Unifies 1050EVK boards - Adds support to both NOR and HyperFlash on boards with both capabilities. - Adds automatic FlexRAM initialization to start-up code based on linker script and NXP HAL. - Applies code formatting to all files in mimxrt port. With this change the flash configuration is restructured and organized. This simplifies the configuration process and provides a better overview of each board's settings. With the integration of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better control of the settings and clock configurations. Furthermore the implementation of an explicit FlexRAM setup improves the system performance and allows for performance tuning. Signed-off-by: Philipp Ebensberger
2021-08-20 15:41:58 -04:00
.cd_b = { GPIO_SD_B0_06_USDHC1_CD_B }, \
.data0 = { GPIO_SD_B0_04_USDHC1_DATA0 }, \
.data1 = { GPIO_SD_B0_05_USDHC1_DATA1 }, \
.data2 = { GPIO_SD_B0_00_USDHC1_DATA2 }, \
.data3 = { GPIO_SD_B0_01_USDHC1_DATA3 }, \
mimxrt/sdcard: Implement SDCard driver. - Configures `PLL2->PFD0` with **198MHz** as base clock of `USDHCx` peripheral. - Adds guards for SDCard related files via `MICROPY_PY_MACHINE_SDCARD` - Adds creation of pin defines for SDCard to make-pins.py - Adds new configuration option for SDCard peripheral pinout to mpconfigport.h - Adds interrupt handling support instead of polling - Adds support for `ADMA2` powered data transfer - Configures SDCard to run in HS (high-speed mode) with **50MHz** only! SDCard support is optional and requires `USDHC` peripheral. Thus this driver is not available on `MIMXRT1010_EVK`. SDCard support is enabled by setting `MICROPY_PY_MACHINE_SDCARD = 1` in mpconfigboard.mk. Signed-off-by: Philipp Ebensberger
2021-08-01 05:20:39 -04:00
}
mimxrt/sdram: Add SDRAM support. Adds support for SDRAM via `SEMC` peripheral. SDRAM support can be enabled in the mpconfigboard.mk file by setting `MICROPY_HW_SDRAM_AVAIL` to `1` and poviding the size of the RAM via `MICROPY_HW_FLASH_SIZE`. When SDRAM support is enabled the whole SDRAM is currently used used for MicroPython heap. Signed-off-by: Philipp Ebensberger
2021-08-20 15:41:58 -04:00
// --- SEMC --- //
#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_32_SEMC_DATA08
#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_33_SEMC_DATA09
#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_34_SEMC_DATA10
#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_35_SEMC_DATA11
#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_36_SEMC_DATA12
#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_37_SEMC_DATA13
#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_38_SEMC_DATA14
#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_39_SEMC_DATA15
#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_16_SEMC_ADDR00
#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_17_SEMC_ADDR01
#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_18_SEMC_ADDR02
#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_19_SEMC_ADDR03
#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_20_SEMC_ADDR04
#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_21_SEMC_ADDR05
#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_22_SEMC_ADDR06
#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_23_SEMC_ADDR07
#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_24_SEMC_ADDR08
#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_25_SEMC_ADDR09
#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_15_SEMC_ADDR10
#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_26_SEMC_ADDR11
#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_27_SEMC_ADDR12
#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_13_SEMC_BA0
#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_14_SEMC_BA1
#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_10_SEMC_CAS
#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_29_SEMC_CKE
#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_30_SEMC_CLK
#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_08_SEMC_DM00
#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_31_SEMC_DM01
#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_28_SEMC_DQS
#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_11_SEMC_RAS
#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_09_SEMC_WE
#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_12_SEMC_CS0
mimxrt/eth: Add LAN support and integrate the network module. This commit implements 10/100 Mbit Ethernet support in the mimxrt port. The following boards are configured without ETH network: - MIMXRT1010_EVK - Teensy 4.0 The following boards are configured with ETH network: - MIMXRT1020_EVK - MIMXRT1050_EVK - MIMXRT1060_EVK - MIMXRT1064_EVK - Teensy 4.1 Ethernet support tested with TEENSY 4.1, MIMRTX1020_EVK and MIMXRT1050_EVK. Build tested with Teensy 4.0 and MIMXRT1010_EVK to be still working. Compiles and builds properly for MIMXRT1060_EVK and MIMXRT1064_EVK, but not tested lacking suitable boards. Tested functions are: - ping works bothway - simple UDP transfer works bothway - ntptime works - the ftp server works - secure socker works - telnet and webrepl works The MAC address is 0x02 plus 5 bytes from the manifacturing info field, which can be considered as unique per device. Some boards do not wire the RESET and INT pin of the PHY transceiver. For operation, these are not required. If they are defined, they will be used.
2021-07-03 12:39:17 -04:00
// Network definitions
// Transceiver Phy Address
#define ENET_PHY_ADDRESS (2)
#define ENET_PHY_OPS phyksz8081_ops
// Etherner PIN definitions
mimxrt: Add support for MIMXRT1176 MCUs, and MIMXRT1170_EVK board. The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
2021-10-20 15:24:20 -04:00
#define ENET_RESET_PIN &pin_GPIO_AD_B0_04
#define ENET_INT_PIN &pin_GPIO_AD_B1_06
mimxrt/eth: Add LAN support and integrate the network module. This commit implements 10/100 Mbit Ethernet support in the mimxrt port. The following boards are configured without ETH network: - MIMXRT1010_EVK - Teensy 4.0 The following boards are configured with ETH network: - MIMXRT1020_EVK - MIMXRT1050_EVK - MIMXRT1060_EVK - MIMXRT1064_EVK - Teensy 4.1 Ethernet support tested with TEENSY 4.1, MIMRTX1020_EVK and MIMXRT1050_EVK. Build tested with Teensy 4.0 and MIMXRT1010_EVK to be still working. Compiles and builds properly for MIMXRT1060_EVK and MIMXRT1064_EVK, but not tested lacking suitable boards. Tested functions are: - ping works bothway - simple UDP transfer works bothway - ntptime works - the ftp server works - secure socker works - telnet and webrepl works The MAC address is 0x02 plus 5 bytes from the manifacturing info field, which can be considered as unique per device. Some boards do not wire the RESET and INT pin of the PHY transceiver. For operation, these are not required. If they are defined, they will be used.
2021-07-03 12:39:17 -04:00
#define IOMUX_TABLE_ENET \
{ IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1, 0xB0E9u }, \
{ IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_EMC_40_ENET_MDIO, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_EMC_41_ENET_MDC, 0, 0xB0E9u },
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