mimxrt/sdram: Add SDRAM support.

Adds support for SDRAM via `SEMC` peripheral. SDRAM support can be enabled in the mpconfigboard.mk file by setting `MICROPY_HW_SDRAM_AVAIL` to `1` and poviding the size of the RAM via `MICROPY_HW_FLASH_SIZE`. When SDRAM support is enabled the whole SDRAM is currently used used for MicroPython heap. Signed-off-by: Philipp Ebensberger
2021-08-20 21:41:58 +02:00 · 2021-08-20 21:41:58 +02:00 · 7e62c9707a
commit 7e62c9707a
parent f4c1389fbc
34 changed files with 514 additions and 72 deletions
--- a/ports/mimxrt/Makefile
+++ b/ports/mimxrt/Makefile
@ -13,15 +13,22 @@ endif
 include ../../py/mkenv.mk
 include $(BOARD_DIR)/mpconfigboard.mk

-# Set optional flash configuration variables
-BOARD_FLASH_RESERVED ?=
+LD_MEMORY_CONFIG_DEFINES += \
+	MICROPY_HW_FLASH_TYPE=$(MICROPY_HW_FLASH_TYPE) \
+	MICROPY_HW_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE)
+
+ifdef MICROPY_HW_FLASH_RESERVED
+LD_MEMORY_CONFIG_DEFINES += MICROPY_HW_FLASH_RESERVED=$(MICROPY_HW_FLASH_RESERVED)
+endif
+
+ifdef MICROPY_HW_SDRAM_AVAIL
+CFLAGS += \
+	-DMICROPY_HW_SDRAM_AVAIL=$(MICROPY_HW_SDRAM_AVAIL) \
+	-DMICROPY_HW_SDRAM_SIZE=$(MICROPY_HW_SDRAM_SIZE)

 LD_MEMORY_CONFIG_DEFINES += \
-	BOARD_FLASH_TYPE=$(BOARD_FLASH_TYPE) \
-	BOARD_FLASH_SIZE=$(BOARD_FLASH_SIZE)
-
-ifdef $(BOARD_FLASH_RESERVED)
-LD_MEMORY_CONFIG_DEFINES += BOARD_FLASH_RESERVED=$(BOARD_FLASH_RESERVED)
+	MICROPY_HW_SDRAM_AVAIL=$(MICROPY_HW_SDRAM_AVAIL) \
+	MICROPY_HW_SDRAM_SIZE=$(MICROPY_HW_SDRAM_SIZE)
 endif

 # Qstr definitions (must come before including py.mk)
@ -81,12 +88,13 @@ CFLAGS += -DXIP_EXTERNAL_FLASH=1 \
 	-D__STARTUP_INITIALIZE_RAMFUNCTION \
 	-D__START=main \
 	-DCPU_HEADER_H='<$(MCU_SERIES).h>' \
-	-DBOARD_FLASH_SIZE=$(BOARD_FLASH_SIZE) \
+	-DBOARD_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
+	-DMICROPY_HW_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
 	-DBOARD_FLASH_CONFIG_HEADER_H=\"$(BOARD)_flexspi_nor_config.h\"

-ifeq ($(BOARD_FLASH_TYPE), qspi_nor)
+ifeq ($(MICROPY_HW_FLASH_TYPE), qspi_nor)
 CFLAGS += -DBOARD_FLASH_OPS_HEADER_H=\"hal/flexspi_nor_flash.h\"
-else ifeq ($(BOARD_FLASH_TYPE), hyperflash)
+else ifeq ($(MICROPY_HW_FLASH_TYPE), hyperflash)
 CFLAGS += -DBOARD_FLASH_OPS_HEADER_H=\"hal/flexspi_hyper_flash.h\"
 endif

@ -163,6 +171,10 @@ SRC_HAL_IMX_C += \
 	$(MCU_DIR)/system_$(MCU_SERIES).c \
 	$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \

+ifeq ($(MICROPY_HW_SDRAM_AVAIL), 1)
+SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_semc.c
+endif
+
 ifeq ($(MICROPY_PY_MACHINE_SDCARD),1)
 SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_usdhc.c
 endif
@ -186,6 +198,7 @@ SRC_C += \
 	machine_uart.c \
 	main.c \
 	mimxrt_flash.c \
+	mimxrt_sdram.c \
 	modmachine.c \
 	modmimxrt.c \
 	moduos.c \
@ -207,16 +220,16 @@ SRC_C += \
 	$(SRC_TINYUSB_C) \
 	$(SRC_HAL_IMX_C) \

-ifeq ($(BOARD_FLASH_TYPE), qspi_nor)
+ifeq ($(MICROPY_HW_FLASH_TYPE), qspi_nor)
 SRC_C += \
 	hal/flexspi_nor_flash.c \
 	$(BOARD_DIR)/qspi_nor_flash_config.c
-else ifeq ($(BOARD_FLASH_TYPE), hyperflash)
+else ifeq ($(MICROPY_HW_FLASH_TYPE), hyperflash)
 SRC_C += \
 	hal/flexspi_hyper_flash.c \
 	$(BOARD_DIR)/qspi_hyper_flash_config.c
 else
-$(error Error: Unknown board flash type $(BOARD_FLASH_TYPE))
+$(error Error: Unknown board flash type $(MICROPY_HW_FLASH_TYPE))
 endif

 ifeq ($(MICROPY_FLOAT_IMPL),double)
--- a/ports/mimxrt/board_init.c
+++ b/ports/mimxrt/board_init.c
@ -51,8 +51,12 @@ void board_init(void) {
    // Enable IOCON clock
    CLOCK_EnableClock(kCLOCK_Iomuxc);

-    // ------------- USB0 ------------- //
+    // ------------- SDRAM ------------ //
+    #ifdef MICROPY_HW_SDRAM_AVAIL
+    mimxrt_sdram_init();
+    #endif

+    // ------------- USB0 ------------- //
    // Clock
    CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
    CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
--- a/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.mk
+++ b/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.mk
@ -3,8 +3,8 @@ MCU_VARIANT = MIMXRT1011DAE5A

 MICROPY_FLOAT_IMPL = single
 MICROPY_PY_MACHINE_SDCARD = 0
-BOARD_FLASH_TYPE ?= qspi_nor
-BOARD_FLASH_SIZE ?= 0x1000000  # 16MB
+MICROPY_HW_FLASH_TYPE ?= qspi_nor
+MICROPY_HW_FLASH_SIZE ?= 0x1000000  # 16MB

 JLINK_PATH ?= /media/RT1010-EVK/
 JLINK_COMMANDER_SCRIPT = $(BUILD)/script.jlink
--- a/ports/mimxrt/boards/MIMXRT1010_EVK/qspi_nor_flash_config.c
+++ b/ports/mimxrt/boards/MIMXRT1010_EVK/qspi_nor_flash_config.c
@ -34,7 +34,7 @@ const flexspi_nor_config_t qspiflash_config = {
        .csSetupTime = 3u,
        .sflashPadType = kSerialFlash_4Pads,
        .serialClkFreq = kFlexSpiSerialClk_100MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .lookupTable =
        {
            // 0 Read LUTs 0 -> 0
--- a/ports/mimxrt/boards/MIMXRT1011.ld
+++ b/ports/mimxrt/boards/MIMXRT1011.ld
@ -1,14 +1,14 @@
 /* Memory configuration */
-#if BOARD_FLASH_RESERVED
-reserved_size = BOARD_FLASH_RESERVED;
+#if MICROPY_HW_FLASH_RESERVED
+reserved_size = MICROPY_HW_FLASH_RESERVED;
 #endif

-#if BOARD_FLASH_TYPE==qspi_nor
+#if MICROPY_HW_FLASH_TYPE==qspi_nor
 flash_start         = 0x60000000;
 #else
-#error Unknown BOARD_FLASH_TYPE
+#error Unknown MICROPY_HW_FLASH_TYPE
 #endif
-flash_size          = BOARD_FLASH_SIZE;
+flash_size          = MICROPY_HW_FLASH_SIZE;
 flash_end           = DEFINED(reserved_size) ? ((flash_start) + (flash_size - reserved_size)) : ((flash_start) + (flash_size));
 flash_config_start  = flash_start + 0x00000400;
 flash_config_size   = 0x00000C00;
--- a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h
+++ b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h
@ -72,3 +72,48 @@
        .data2 = { GPIO_SD_B0_00_USDHC1_DATA2 }, \
        .data3 = { GPIO_SD_B0_01_USDHC1_DATA3 }, \
    }
+
+// --- SEMC --- //
+#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
+#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
+#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
+#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
+#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
+#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
+#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
+#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
+#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_32_SEMC_DATA08
+#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_33_SEMC_DATA09
+#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_34_SEMC_DATA10
+#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_35_SEMC_DATA11
+#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_36_SEMC_DATA12
+#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_37_SEMC_DATA13
+#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_38_SEMC_DATA14
+#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_39_SEMC_DATA15
+
+#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_16_SEMC_ADDR00
+#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_17_SEMC_ADDR01
+#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_18_SEMC_ADDR02
+#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_19_SEMC_ADDR03
+#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_20_SEMC_ADDR04
+#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_21_SEMC_ADDR05
+#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_22_SEMC_ADDR06
+#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_23_SEMC_ADDR07
+#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_24_SEMC_ADDR08
+#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_25_SEMC_ADDR09
+#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_15_SEMC_ADDR10
+#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_26_SEMC_ADDR11
+#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_27_SEMC_ADDR12
+
+#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_13_SEMC_BA0
+#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_14_SEMC_BA1
+#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_10_SEMC_CAS
+#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_29_SEMC_CKE
+#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_30_SEMC_CLK
+#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_08_SEMC_DM00
+#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_31_SEMC_DM01
+#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_28_SEMC_DQS
+#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_11_SEMC_RAS
+#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_09_SEMC_WE
+
+#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_12_SEMC_CS0
--- a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.mk
+++ b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.mk
@ -3,8 +3,11 @@ MCU_VARIANT = MIMXRT1021DAG5A

 MICROPY_FLOAT_IMPL = double
 MICROPY_PY_MACHINE_SDCARD = 1
-BOARD_FLASH_TYPE ?= qspi_nor
-BOARD_FLASH_SIZE ?= 0x800000  # 8MB
+MICROPY_HW_FLASH_TYPE ?= qspi_nor
+MICROPY_HW_FLASH_SIZE ?= 0x800000  # 8MB
+
+MICROPY_HW_SDRAM_AVAIL = 1
+MICROPY_HW_SDRAM_SIZE  = 0x2000000  # 32MB

 JLINK_PATH ?= /media/RT1020-EVK/
 JLINK_COMMANDER_SCRIPT = $(BUILD)/script.jlink
--- a/ports/mimxrt/boards/MIMXRT1020_EVK/qspi_nor_flash_config.c
+++ b/ports/mimxrt/boards/MIMXRT1020_EVK/qspi_nor_flash_config.c
@ -45,7 +45,7 @@ const flexspi_nor_config_t qspiflash_config = {
        .deviceType = kFlexSpiDeviceType_SerialNOR,
        .sflashPadType = kSerialFlash_4Pads,
        .serialClkFreq = kFlexSpiSerialClk_100MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .lookupTable =
        {
            // 0 Read LUTs 0 -> 0
--- a/ports/mimxrt/boards/MIMXRT1021.ld
+++ b/ports/mimxrt/boards/MIMXRT1021.ld
@ -1,14 +1,14 @@
 /* Memory configuration */
-#if defined BOARD_FLASH_RESERVED
-reserved_size = BOARD_FLASH_RESERVED;
+#if defined MICROPY_HW_FLASH_RESERVED
+reserved_size = MICROPY_HW_FLASH_RESERVED;
 #endif

-#if BOARD_FLASH_TYPE == qspi_nor
+#if MICROPY_HW_FLASH_TYPE == qspi_nor
 flash_start         = 0x60000000;
 #else
-#error Unknown BOARD_FLASH_TYPE
+#error Unknown MICROPY_HW_FLASH_TYPE
 #endif
-flash_size          = BOARD_FLASH_SIZE;
+flash_size          = MICROPY_HW_FLASH_SIZE;
 flash_end           = DEFINED(reserved_size) ? ((flash_start) + (flash_size - reserved_size)) : ((flash_start) + (flash_size));
 flash_config_start  = flash_start;
 flash_config_size   = 0x00001000;
@ -27,11 +27,21 @@ dtcm_size           = 0x00018000;
 ocrm_start          = 0x20200000;
 ocrm_size           = 0x00020000;

+#ifdef MICROPY_HW_SDRAM_AVAIL
+sdram_start         = 0x80000000;
+sdram_size          = MICROPY_HW_SDRAM_SIZE;
+#endif
+
 /* 24kiB stack. */
 __stack_size__ = 0x6000;
 _estack = __StackTop;
 _sstack = __StackLimit;

+#ifdef MICROPY_HW_SDRAM_AVAIL
+_gc_heap_start = ORIGIN(m_sdram);
+_gc_heap_end = ORIGIN(m_sdram) + LENGTH(m_sdram);
+#else
 /* Use second OCRAM bank for GC heap. */
 _gc_heap_start = ORIGIN(m_ocrm);
 _gc_heap_end = ORIGIN(m_ocrm) + LENGTH(m_ocrm);
+#endif
--- a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h
+++ b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h
@ -63,3 +63,48 @@
        .data2 = { GPIO_SD_B0_04_USDHC1_DATA2 }, \
        .data3 = { GPIO_SD_B0_05_USDHC1_DATA3 }, \
    }
+
+// --- SEMC --- //
+#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
+#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
+#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
+#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
+#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
+#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
+#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
+#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
+#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DATA08
+#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DATA09
+#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DATA10
+#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DATA11
+#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DATA12
+#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DATA13
+#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DATA14
+#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DATA15
+
+#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_10_SEMC_ADDR01
+#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_11_SEMC_ADDR02
+#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_12_SEMC_ADDR03
+#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_13_SEMC_ADDR04
+#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_14_SEMC_ADDR05
+#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_15_SEMC_ADDR06
+#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_16_SEMC_ADDR07
+#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_17_SEMC_ADDR08
+#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_18_SEMC_ADDR09
+#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_23_SEMC_ADDR10
+#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_19_SEMC_ADDR11
+#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_20_SEMC_ADDR12
+
+#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_21_SEMC_BA0
+#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_22_SEMC_BA1
+#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_24_SEMC_CAS
+#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_27_SEMC_CKE
+#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_26_SEMC_CLK
+#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_08_SEMC_DM00
+#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_38_SEMC_DM01
+#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_39_SEMC_DQS
+#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_25_SEMC_RAS
+#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_28_SEMC_WE
+
+#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_29_SEMC_CS0
--- a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.mk
+++ b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.mk
@ -3,8 +3,11 @@ MCU_VARIANT = MIMXRT1052DVL6B

 MICROPY_FLOAT_IMPL = double
 MICROPY_PY_MACHINE_SDCARD = 1
-BOARD_FLASH_TYPE ?= hyperflash
-BOARD_FLASH_SIZE ?= 0x4000000  # 64MB
+MICROPY_HW_FLASH_TYPE ?= hyperflash
+MICROPY_HW_FLASH_SIZE ?= 0x4000000  # 64MB
+
+MICROPY_HW_SDRAM_AVAIL = 1
+MICROPY_HW_SDRAM_SIZE  = 0x2000000  # 32MB

 JLINK_PATH ?= /media/RT1050-EVKB/

--- a/ports/mimxrt/boards/MIMXRT1050_EVK/qspi_hyper_flash_config.c
+++ b/ports/mimxrt/boards/MIMXRT1050_EVK/qspi_hyper_flash_config.c
@ -37,7 +37,7 @@ const flexspi_nor_config_t qspiflash_config = {
            (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
        .sflashPadType = kSerialFlash_8Pads,
        .serialClkFreq = kFlexSpiSerialClk_133MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .dataValidTime = {16u, 16u},
        .lookupTable =
        {
--- a/ports/mimxrt/boards/MIMXRT1050_EVK/qspi_nor_flash_config.c
+++ b/ports/mimxrt/boards/MIMXRT1050_EVK/qspi_nor_flash_config.c
@ -37,7 +37,7 @@ const flexspi_nor_config_t qspiflash_config = {
            (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
        .sflashPadType = kSerialFlash_8Pads,
        .serialClkFreq = kFlexSpiSerialClk_133MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .dataValidTime = {16u, 16u},
        .lookupTable =
        {
--- a/ports/mimxrt/boards/MIMXRT1052.ld
+++ b/ports/mimxrt/boards/MIMXRT1052.ld
@ -1,16 +1,16 @@
 /* Memory configuration */
-#if BOARD_FLASH_RESERVED
-reserved_size = BOARD_FLASH_RESERVED;
+#if MICROPY_HW_FLASH_RESERVED
+reserved_size = MICROPY_HW_FLASH_RESERVED;
 #endif

-#if BOARD_FLASH_TYPE==qspi_nor
+#if MICROPY_HW_FLASH_TYPE==qspi_nor
 flash_start         = 0x60000000;
-#elif BOARD_FLASH_TYPE==hyperflash
+#elif MICROPY_HW_FLASH_TYPE==hyperflash
 flash_start         = 0x60000000;
 #else
-#error Unknown BOARD_FLASH_TYPE
+#error Unknown MICROPY_HW_FLASH_TYPE
 #endif
-flash_size          = BOARD_FLASH_SIZE;
+flash_size          = MICROPY_HW_FLASH_SIZE;
 flash_end           = DEFINED(reserved_size) ? ((flash_start) + (flash_size - reserved_size)) : ((flash_start) + (flash_size));
 flash_config_start  = flash_start;
 flash_config_size   = 0x00001000;
@ -29,11 +29,21 @@ dtcm_size           = 0x00020000;
 ocrm_start          = 0x20200000;
 ocrm_size           = 0x00040000;

+#ifdef MICROPY_HW_SDRAM_AVAIL
+sdram_start         = 0x80000000;
+sdram_size          = MICROPY_HW_SDRAM_SIZE;
+#endif
+
 /* 24kiB stack. */
 __stack_size__ = 0x6000;
 _estack = __StackTop;
 _sstack = __StackLimit;

+#ifdef MICROPY_HW_SDRAM_AVAIL
+_gc_heap_start = ORIGIN(m_sdram);
+_gc_heap_end = ORIGIN(m_sdram) + LENGTH(m_sdram);
+#else
 /* Use second OCRAM bank for GC heap. */
 _gc_heap_start = ORIGIN(m_ocrm);
 _gc_heap_end = ORIGIN(m_ocrm) + LENGTH(m_ocrm);
+#endif
--- a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h
+++ b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h
@ -62,3 +62,48 @@
        .data2 = { GPIO_SD_B0_04_USDHC1_DATA2 }, \
        .data3 = { GPIO_SD_B0_05_USDHC1_DATA3 }, \
    }
+
+// --- SEMC --- //
+#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
+#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
+#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
+#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
+#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
+#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
+#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
+#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
+#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DATA08
+#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DATA09
+#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DATA10
+#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DATA11
+#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DATA12
+#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DATA13
+#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DATA14
+#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DATA15
+
+#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_10_SEMC_ADDR01
+#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_11_SEMC_ADDR02
+#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_12_SEMC_ADDR03
+#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_13_SEMC_ADDR04
+#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_14_SEMC_ADDR05
+#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_15_SEMC_ADDR06
+#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_16_SEMC_ADDR07
+#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_17_SEMC_ADDR08
+#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_18_SEMC_ADDR09
+#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_23_SEMC_ADDR10
+#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_19_SEMC_ADDR11
+#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_20_SEMC_ADDR12
+
+#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_21_SEMC_BA0
+#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_22_SEMC_BA1
+#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_24_SEMC_CAS
+#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_27_SEMC_CKE
+#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_26_SEMC_CLK
+#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_08_SEMC_DM00
+#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_38_SEMC_DM01
+#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_39_SEMC_DQS
+#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_25_SEMC_RAS
+#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_28_SEMC_WE
+
+#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_29_SEMC_CS0
--- a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.mk
+++ b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.mk
@ -3,8 +3,11 @@ MCU_VARIANT = MIMXRT1062DVJ6A

 MICROPY_FLOAT_IMPL = double
 MICROPY_PY_MACHINE_SDCARD = 1
-BOARD_FLASH_TYPE ?= qspi_nor
-BOARD_FLASH_SIZE ?= 0x800000  # 8MB
+MICROPY_HW_FLASH_TYPE ?= qspi_nor
+MICROPY_HW_FLASH_SIZE ?= 0x800000  # 8MB
+
+MICROPY_HW_SDRAM_AVAIL = 1
+MICROPY_HW_SDRAM_SIZE  = 0x2000000  # 32MB

 JLINK_PATH ?= /media/RT1060-EVK/
 JLINK_COMMANDER_SCRIPT = $(BUILD)/script.jlink
--- a/ports/mimxrt/boards/MIMXRT1060_EVK/qspi_hyper_flash_config.c
+++ b/ports/mimxrt/boards/MIMXRT1060_EVK/qspi_hyper_flash_config.c
@ -37,7 +37,7 @@ const flexspi_nor_config_t qspiflash_config = {
            (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
        .sflashPadType = kSerialFlash_8Pads,
        .serialClkFreq = kFlexSpiSerialClk_133MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .dataValidTime = {16u, 16u},
        .lookupTable =
        {
--- a/ports/mimxrt/boards/MIMXRT1060_EVK/qspi_nor_flash_config.c
+++ b/ports/mimxrt/boards/MIMXRT1060_EVK/qspi_nor_flash_config.c
@ -37,7 +37,7 @@ const flexspi_nor_config_t qspiflash_config = {
            (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
        .sflashPadType = kSerialFlash_8Pads,
        .serialClkFreq = kFlexSpiSerialClk_133MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .dataValidTime = {16u, 16u},
        .lookupTable =
        {
--- a/ports/mimxrt/boards/MIMXRT1062.ld
+++ b/ports/mimxrt/boards/MIMXRT1062.ld
@ -1,16 +1,16 @@
 /* Memory configuration */
-#if BOARD_FLASH_RESERVED
-reserved_size = BOARD_FLASH_RESERVED;
+#if MICROPY_HW_FLASH_RESERVED
+reserved_size = MICROPY_HW_FLASH_RESERVED;
 #endif

-#if BOARD_FLASH_TYPE==qspi_nor
+#if MICROPY_HW_FLASH_TYPE==qspi_nor
 flash_start         = 0x60000000;
-#elif BOARD_FLASH_TYPE==hyperflash
+#elif MICROPY_HW_FLASH_TYPE==hyperflash
 flash_start         = 0x60000000;
 #else
-#error Unknown BOARD_FLASH_TYPE
+#error Unknown MICROPY_HW_FLASH_TYPE
 #endif
-flash_size          = BOARD_FLASH_SIZE;
+flash_size          = MICROPY_HW_FLASH_SIZE;
 flash_end           = DEFINED(reserved_size) ? ((flash_start) + (flash_size - reserved_size)) : ((flash_start) + (flash_size));
 flash_config_start  = flash_start;
 flash_config_size   = 0x00001000;
@ -29,11 +29,21 @@ dtcm_size           = 0x00020000;
 ocrm_start          = 0x20200000;
 ocrm_size           = 0x000C0000;

+#ifdef MICROPY_HW_SDRAM_AVAIL
+sdram_start         = 0x80000000;
+sdram_size          = MICROPY_HW_SDRAM_SIZE;
+#endif
+
 /* 32kiB stack. */
 __stack_size__ = 0x8000;
 _estack = __StackTop;
 _sstack = __StackLimit;

+#ifdef MICROPY_HW_SDRAM_AVAIL
+_gc_heap_start = ORIGIN(m_sdram);
+_gc_heap_end = ORIGIN(m_sdram) + LENGTH(m_sdram);
+#else
 /* Use second OCRAM bank for GC heap. */
 _gc_heap_start = ORIGIN(m_ocrm);
 _gc_heap_end = ORIGIN(m_ocrm) + LENGTH(m_ocrm);
+#endif
--- a/ports/mimxrt/boards/MIMXRT1064.ld
+++ b/ports/mimxrt/boards/MIMXRT1064.ld
@ -1,18 +1,18 @@
 /* Memory configuration */
-#if BOARD_FLASH_RESERVED
-reserved_size = BOARD_FLASH_RESERVED;
+#if MICROPY_HW_FLASH_RESERVED
+reserved_size = MICROPY_HW_FLASH_RESERVED;
 #endif

-#if BOARD_FLASH_TYPE==qspi_nor
+#if MICROPY_HW_FLASH_TYPE==qspi_nor
 flash_start         = 0x60000000;
-#elif BOARD_FLASH_TYPE==hyperflash
+#elif MICROPY_HW_FLASH_TYPE==hyperflash
 flash_start         = 0x60000000;
-#elif BOARD_FLASH_TYPE==internal
+#elif MICROPY_HW_FLASH_TYPE==internal
 flash_start         = 0x70000000;
 #else
-#error Unknown BOARD_FLASH_TYPE
+#error Unknown MICROPY_HW_FLASH_TYPE
 #endif
-flash_size          = BOARD_FLASH_SIZE;
+flash_size          = MICROPY_HW_FLASH_SIZE;
 flash_end           = DEFINED(reserved_size) ? ((flash_start) + (flash_size - reserved_size)) : ((flash_start) + (flash_size));
 flash_config_start  = flash_start;
 flash_config_size   = 0x00001000;
@ -31,11 +31,21 @@ dtcm_size           = 0x00020000;
 ocrm_start          = 0x20200000;
 ocrm_size           = 0x000C0000;

+#ifdef MICROPY_HW_SDRAM_AVAIL
+sdram_start         = 0x80000000;
+sdram_size          = MICROPY_HW_SDRAM_SIZE;
+#endif
+
 /* 24kiB stack. */
 __stack_size__ = 0x6000;
 _estack = __StackTop;
 _sstack = __StackLimit;

+#ifdef MICROPY_HW_SDRAM_AVAIL
+_gc_heap_start = ORIGIN(m_sdram);
+_gc_heap_end = ORIGIN(m_sdram) + LENGTH(m_sdram);
+#else
 /* Use second OCRAM bank for GC heap. */
 _gc_heap_start = ORIGIN(m_ocrm);
 _gc_heap_end = ORIGIN(m_ocrm) + LENGTH(m_ocrm);
+#endif
--- a/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h
+++ b/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h
@ -62,3 +62,48 @@
        .data2 = { GPIO_SD_B0_04_USDHC1_DATA2 }, \
        .data3 = { GPIO_SD_B0_05_USDHC1_DATA3 }, \
    }
+
+// --- SEMC --- //
+#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
+#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
+#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
+#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
+#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
+#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
+#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
+#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
+#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DATA08
+#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DATA09
+#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DATA10
+#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DATA11
+#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DATA12
+#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DATA13
+#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DATA14
+#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DATA15
+
+#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_10_SEMC_ADDR01
+#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_11_SEMC_ADDR02
+#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_12_SEMC_ADDR03
+#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_13_SEMC_ADDR04
+#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_14_SEMC_ADDR05
+#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_15_SEMC_ADDR06
+#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_16_SEMC_ADDR07
+#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_17_SEMC_ADDR08
+#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_18_SEMC_ADDR09
+#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_23_SEMC_ADDR10
+#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_19_SEMC_ADDR11
+#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_20_SEMC_ADDR12
+
+#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_21_SEMC_BA0
+#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_22_SEMC_BA1
+#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_24_SEMC_CAS
+#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_27_SEMC_CKE
+#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_26_SEMC_CLK
+#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_08_SEMC_DM00
+#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_38_SEMC_DM01
+#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_39_SEMC_DQS
+#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_25_SEMC_RAS
+#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_28_SEMC_WE
+
+#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_29_SEMC_CS0
--- a/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.mk
+++ b/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.mk
@ -3,8 +3,11 @@ MCU_VARIANT = MIMXRT1064DVL6A

 MICROPY_FLOAT_IMPL = double
 MICROPY_PY_MACHINE_SDCARD = 1
-BOARD_FLASH_TYPE ?= hyperflash
-BOARD_FLASH_SIZE ?= 0x4000000  # 64MB
+MICROPY_HW_FLASH_TYPE ?= hyperflash
+MICROPY_HW_FLASH_SIZE ?= 0x4000000  # 64MB
+
+MICROPY_HW_SDRAM_AVAIL = 1
+MICROPY_HW_SDRAM_SIZE  = 0x2000000  # 32MB

 JLINK_PATH ?= /media/RT1064-EVK/

--- a/ports/mimxrt/boards/MIMXRT1064_EVK/qspi_hyper_flash_config.c
+++ b/ports/mimxrt/boards/MIMXRT1064_EVK/qspi_hyper_flash_config.c
@ -37,7 +37,7 @@ const flexspi_nor_config_t qspiflash_config = {
            (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
        .sflashPadType = kSerialFlash_8Pads,
        .serialClkFreq = kFlexSpiSerialClk_133MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .dataValidTime = {16u, 16u},
        .lookupTable =
        {
--- a/ports/mimxrt/boards/MIMXRT1064_EVK/qspi_nor_flash_config.c
+++ b/ports/mimxrt/boards/MIMXRT1064_EVK/qspi_nor_flash_config.c
@ -37,7 +37,7 @@ const flexspi_nor_config_t qspiflash_config = {
            (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
        .sflashPadType = kSerialFlash_8Pads,
        .serialClkFreq = kFlexSpiSerialClk_133MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .dataValidTime = {16u, 16u},
        .lookupTable =
        {
--- a/ports/mimxrt/boards/TEENSY40/mpconfigboard.mk
+++ b/ports/mimxrt/boards/TEENSY40/mpconfigboard.mk
@ -3,9 +3,9 @@ MCU_VARIANT = MIMXRT1062DVJ6A

 MICROPY_FLOAT_IMPL = double
 MICROPY_PY_MACHINE_SDCARD = 1
-BOARD_FLASH_TYPE ?= qspi_nor
-BOARD_FLASH_SIZE ?= 0x200000  # 2MB
-BOARD_FLASH_RESERVED ?= 0x1000  # 4KB
+MICROPY_HW_FLASH_TYPE ?= qspi_nor
+MICROPY_HW_FLASH_SIZE ?= 0x200000  # 2MB
+MICROPY_HW_FLASH_RESERVED ?= 0x1000  # 4KB

 deploy: $(BUILD)/firmware.hex
 	teensy_loader_cli --mcu=imxrt1062 -v -w $<
--- a/ports/mimxrt/boards/TEENSY40/qspi_nor_flash_config.c
+++ b/ports/mimxrt/boards/TEENSY40/qspi_nor_flash_config.c
@ -53,7 +53,7 @@ const flexspi_nor_config_t qspiflash_config = {
        // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
        .sflashPadType = kSerialFlash_4Pads,
        .serialClkFreq = kFlexSpiSerialClk_60MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .lookupTable =
        {
            // 0 Read LUTs 0 -> 0
--- a/ports/mimxrt/boards/TEENSY41/mpconfigboard.mk
+++ b/ports/mimxrt/boards/TEENSY41/mpconfigboard.mk
@ -3,9 +3,9 @@ MCU_VARIANT = MIMXRT1062DVJ6A

 MICROPY_FLOAT_IMPL = double
 MICROPY_PY_MACHINE_SDCARD = 1
-BOARD_FLASH_TYPE ?= qspi_nor
-BOARD_FLASH_SIZE ?= 0x800000  # 8MB
-BOARD_FLASH_RESERVED ?= 0x1000  # 4KB
+MICROPY_HW_FLASH_TYPE ?= qspi_nor
+MICROPY_HW_FLASH_SIZE ?= 0x800000  # 8MB
+MICROPY_HW_FLASH_RESERVED ?= 0x1000  # 4KB

 deploy: $(BUILD)/firmware.hex
 	teensy_loader_cli --mcu=imxrt1062 -v -w $<
--- a/ports/mimxrt/boards/TEENSY41/qspi_nor_flash_config.c
+++ b/ports/mimxrt/boards/TEENSY41/qspi_nor_flash_config.c
@ -53,7 +53,7 @@ const flexspi_nor_config_t qspiflash_config = {
        // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
        .sflashPadType = kSerialFlash_4Pads,
        .serialClkFreq = kFlexSpiSerialClk_60MHz,
-        .sflashA1Size = BOARD_FLASH_SIZE,
+        .sflashA1Size = MICROPY_HW_FLASH_SIZE,
        .lookupTable =
        {
            // 0 Read LUTs 0 -> 0
--- a/ports/mimxrt/boards/common.ld
+++ b/ports/mimxrt/boards/common.ld
@ -45,12 +45,19 @@ MEMORY
  m_itcm         (RX) : ORIGIN = itcm_start,            LENGTH = itcm_size
  m_dtcm         (RW) : ORIGIN = dtcm_start,            LENGTH = dtcm_size
  m_ocrm         (RW) : ORIGIN = ocrm_start,            LENGTH = ocrm_size
+
+  #ifdef MICROPY_HW_SDRAM_AVAIL
+  m_sdram        (RX) : ORIGIN = sdram_start,           LENGTH = sdram_size
+  #endif
 }

 /* Define output sections */
 SECTIONS
 {
  __flash_start = flash_start;
+  #ifdef MICROPY_HW_SDRAM_AVAIL
+  __sdram_start = sdram_start;
+  #endif
  __vfs_start = ORIGIN(m_vfs);
  __vfs_end = __vfs_start + LENGTH(m_vfs);  
  
--- a/ports/mimxrt/boards/make-pins.py
+++ b/ports/mimxrt/boards/make-pins.py
@ -8,7 +8,7 @@ import sys
 import csv
 import re

-SUPPORTED_AFS = {"GPIO", "USDHC"}
+SUPPORTED_AFS = {"GPIO", "USDHC", "SEMC"}
 MAX_AF = 10  # AF0 .. AF9
 ADC_COL = 11

--- a/ports/mimxrt/mimxrt_flash.c
+++ b/ports/mimxrt/mimxrt_flash.c
@ -32,8 +32,6 @@
 #include "modmimxrt.h"
 #include BOARD_FLASH_OPS_HEADER_H

-// BOARD_FLASH_SIZE is defined in mpconfigport.h
-
 #define SECTOR_SIZE_BYTES (qspiflash_config.sectorSize)
 #define PAGE_SIZE_BYTES (qspiflash_config.pageSize)

--- a/ports/mimxrt/mimxrt_sdram.c
+++ b/ports/mimxrt/mimxrt_sdram.c
@ -0,0 +1,186 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Philipp Ebensberger
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#if MICROPY_HW_SDRAM_AVAIL
+
+#include "modmachine.h"
+#include "fsl_semc.h"
+#include "fsl_iomuxc.h"
+
+// Linker symbols
+extern uint8_t __sdram_start;
+
+
+void mimxrt_sdram_init(void) {
+    // Set Clocks
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);   // '29' PLL2 PFD2 frequency = 528MHz * 18 / 29 = 327.72MHz (with 528MHz = PLL2 frequency)
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);  // '0'  PLL2 PFD2 will be selected as alternative clock for SEMC root clock
+    CLOCK_SetMux(kCLOCK_SemcMux, 1);     // '1'  SEMC alternative clock will be used as SEMC clock root
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 1);     // '1'  divide by 2 -> SEMC clock = 163.86 MHz
+
+    // Set Pins
+
+    // Data Pins
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA00, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA00, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA01, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA01, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA02, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA02, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA03, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA03, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA04, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA04, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA05, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA05, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA06, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA06, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA07, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA07, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA08, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA08, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA09, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA09, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA10, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA10, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA11, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA11, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA12, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA12, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA13, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA13, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA14, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA14, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA15, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA15, 0xE1UL);
+
+    // Address Pins
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR00, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR00, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR01, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR01, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR02, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR02, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR03, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR03, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR04, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR04, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR05, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR05, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR06, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR06, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR07, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR07, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR08, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR08, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR09, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR09, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR10, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR10, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR11, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR11, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR12, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR12, 0xE1UL);
+
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM00, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM00, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_BA0, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA0, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_BA1, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA1, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CAS, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CAS, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_RAS, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_RAS, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CLK, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CLK, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CKE, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CKE, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_WE, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_WE, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM01, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM01, 0xE1UL);
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DQS, 1UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DQS, 0xE1UL);
+
+    // Chip Select Pins
+    #ifndef MIMXRT_IOMUXC_SEMC_CS0
+    #error No SEMC CS0 defined!
+    #endif
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS0, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS0, 0xE1UL);
+
+    #ifdef MIMXRT_IOMUXC_SEMC_CS1
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS1, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS1, 0xE1UL);
+    #endif
+
+    #ifdef MIMXRT_IOMUXC_SEMC_CS2
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS2, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS2, 0xE1UL);
+    #endif
+
+    #ifdef MIMXRT_IOMUXC_SEMC_CS3
+    IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS3, 0UL);
+    IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS3, 0xE1UL);
+    #endif
+
+    // Configure SEMC
+    semc_config_t semc_cfg;
+    SEMC_GetDefaultConfig(&semc_cfg);
+
+    semc_cfg.dqsMode = kSEMC_Loopbackdqspad;  // For more accurate timing.
+    SEMC_Init(SEMC, &semc_cfg);
+
+    uint32_t clock_freq = CLOCK_GetFreq(kCLOCK_SemcClk);
+    semc_sdram_config_t sdram_cfg = {
+        .csxPinMux = kSEMC_MUXCSX0,
+        .address = ((uint32_t)&__sdram_start),
+        .memsize_kbytes = (MICROPY_HW_SDRAM_SIZE >> 10),  // Right shift by 10 == division by 1024
+        .portSize = kSEMC_PortSize16Bit,
+        .burstLen = kSEMC_Sdram_BurstLen1,
+        .columnAddrBitNum = kSEMC_SdramColunm_9bit,
+        .casLatency = kSEMC_LatencyThree,
+        .tPrecharge2Act_Ns = 18,  // Trp 18ns
+        .tAct2ReadWrite_Ns = 18,  // Trcd 18ns
+        .tRefreshRecovery_Ns = (60 + 67),
+        .tWriteRecovery_Ns = 12,  // 12ns
+        .tCkeOff_Ns = 42,  // The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.
+        .tAct2Prechage_Ns = 42,  // Tras 42ns
+        .tSelfRefRecovery_Ns = 67,
+        .tRefresh2Refresh_Ns = 60,
+        .tAct2Act_Ns = 60,
+        .tPrescalePeriod_Ns = 160 * (1000000000 / clock_freq),
+        .tIdleTimeout_Ns = 0UL,
+        .refreshPeriod_nsPerRow = 64 * 1000000 / 8192,  // 64ms/8192
+        .refreshUrgThreshold = 64 * 1000000 / 8192,  // 64ms/8192
+        .refreshBurstLen = 1
+    };
+
+    (status_t)SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdram_cfg, clock_freq);
+}
+
+#endif
--- a/ports/mimxrt/modmachine.h
+++ b/ports/mimxrt/modmachine.h
@ -41,5 +41,6 @@ void machine_adc_init(void);
 void machine_pin_irq_deinit(void);
 void machine_timer_init_PIT(void);
 void machine_sdcard_init0(void);
+void mimxrt_sdram_init(void);

 #endif // MICROPY_INCLUDED_MIMXRT_MODMACHINE_H
--- a/ports/mimxrt/pin.h
+++ b/ports/mimxrt/pin.h
@ -67,6 +67,7 @@ enum {
    PIN_AF_MODE_ALT6,
    PIN_AF_MODE_ALT7,
    PIN_AF_MODE_ALT8,
+    PIN_AF_MODE_ALT9,
 };

 enum {