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mimxrt: Define UART 0 on MIMXRT boards. 

UART 0 is attached to the Debug USB port. The settings are
115200 Baud, 8N1.
For MIMXRT1010_EVK this is identical to UART1. For the other boards,
this is an additional UART.
This commit is contained in:
robert-hh 2021-11-03 15:57:48 +01:00
parent 1b7eee24eb
commit bc1b0fd2c1
6 changed files with 44 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h
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@ -9,12 +9,13 @@
#define MICROPY_HW_NUM_PIN_IRQS (2 * 32)
// Define mapping logical UART # to hardware UART #
// LPUART1 on D0/D1 -> 1
// LPUART3 on A0/D4 -> 3
// LPUART4 on D6/D7 -> 2
// LPUART1 on USB_DBG -> 0
// LPUART1 on D0/D1 -> 1
// LPUART3 on A0/D4 -> 3
// LPUART4 on D6/D7 -> 2
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
#define MICROPY_HW_UART_INDEX { 0, 1, 4 }
#define MICROPY_HW_UART_INDEX { 1, 1, 4, 3 }
#define IOMUX_TABLE_UART \
{ IOMUXC_GPIO_10_LPUART1_TXD }, { IOMUXC_GPIO_09_LPUART1_RXD }, \

17
ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h
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@ -10,16 +10,17 @@
#define MICROPY_HW_NUM_PIN_IRQS (3 * 32)
// Define mapping logical UART # to hardware UART #
// RX/TX HW-UART Logical UART
// D3/D5 LPUART1 Not usable, Since D3 is blocked.
// D0/D1 LPUART2 -> 1
// D6/D9 LPUART3 -> 2
// D10/D12 LPUART5 -> 3
// D14/D15 LPUART8 -> 4
// A0/A1 LPUART4 -> 5
// RX/TX HW-UART Logical UART
// DEBUG USB LPUART1 -> 0
// D3/D5 LPUART1 Not usable, Since D3 is blocked.
// D0/D1 LPUART2 -> 1
// D6/D9 LPUART3 -> 2
// D10/D12 LPUART5 -> 3
// D14/D15 LPUART8 -> 4
// A0/A1 LPUART4 -> 5
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
#define MICROPY_HW_UART_INDEX { 0, 2, 3, 5, 8, 4 }
#define MICROPY_HW_UART_INDEX { 1, 2, 3, 5, 8, 4 }
#define IOMUX_TABLE_UART \
{ IOMUXC_GPIO_AD_B0_06_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_07_LPUART1_RX }, \

13
ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h
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@ -9,16 +9,17 @@
#define MICROPY_HW_NUM_PIN_IRQS (4 * 32 + 3)
// Define mapping logical UART # to hardware UART #
// LPUART3 on D0/D1 -> 1
// LPUART2 on D7/D6 -> 2
// LPUART6 on D8/D9 -> 3
// LPUART8 on A1/A0 -> 4
// LPUART1 on USB_DBG -> 0
// LPUART3 on D0/D1 -> 1
// LPUART2 on D7/D6 -> 2
// LPUART6 on D8/D9 -> 3
// LPUART8 on A1/A0 -> 4
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
#define MICROPY_HW_UART_INDEX { 0, 3, 2, 6, 8 }
#define MICROPY_HW_UART_INDEX { 1, 3, 2, 6, 8 }
#define IOMUX_TABLE_UART \
{ 0 }, { 0 }, \
{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
{ 0 }, { 0 }, \

13
ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h
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@ -9,16 +9,17 @@
#define MICROPY_HW_NUM_PIN_IRQS (4 * 32 + 3)
// Define mapping logical UART # to hardware UART #
// LPUART3 on D0/D1 -> 1
// LPUART2 on D7/D6 -> 2
// LPUART6 on D8/D9 -> 3
// LPUART8 on A1/A0 -> 4
// LPUART1 on USB_DBG -> 0
// LPUART3 on D0/D1 -> 1
// LPUART2 on D7/D6 -> 2
// LPUART6 on D8/D9 -> 3
// LPUART8 on A1/A0 -> 4
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
#define MICROPY_HW_UART_INDEX { 0, 3, 2, 6, 8 }
#define MICROPY_HW_UART_INDEX { 1, 3, 2, 6, 8 }
#define IOMUX_TABLE_UART \
{ 0 }, { 0 }, \
{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
{ 0 }, { 0 }, \

13
ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h
View File

@ -9,16 +9,17 @@
#define MICROPY_HW_NUM_PIN_IRQS (4 * 32 + 3)
// Define mapping logical UART # to hardware UART #
// LPUART3 on D0/D1 -> 1
// LPUART2 on D7/D6 -> 2
// LPUART6 on D8/D9 -> 3
// LPUART8 on A1/A0 -> 4
// LPUART1 on USB_DBG -> 0
// LPUART3 on D0/D1 -> 1
// LPUART2 on D7/D6 -> 2
// LPUART6 on D8/D9 -> 3
// LPUART8 on A1/A0 -> 4
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
#define MICROPY_HW_UART_INDEX { 0, 3, 2, 6, 8 }
#define MICROPY_HW_UART_INDEX { 1, 3, 2, 6, 8 }
#define IOMUX_TABLE_UART \
{ 0 }, { 0 }, \
{ IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
{ IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
{ IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
{ 0 }, { 0 }, \

14
ports/mimxrt/machine_uart.c
View File

@ -269,7 +269,7 @@ STATIC mp_obj_t machine_uart_make_new(const mp_obj_type_t *type, size_t n_args,
// Get UART bus.
int uart_id = mp_obj_get_int(args[0]);
if (uart_id < 1 || uart_id > MICROPY_HW_UART_NUM) {
if (uart_id < 0 || uart_id > MICROPY_HW_UART_NUM || uart_index_table[uart_id] == 0) {
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("UART(%d) doesn't exist"), uart_id);
}
@ -286,11 +286,15 @@ STATIC mp_obj_t machine_uart_make_new(const mp_obj_type_t *type, size_t n_args,
LPUART_GetDefaultConfig(&self->config);
// Configure board-specific pin MUX based on the hardware device number.
lpuart_set_iomux(uart_hw_id);
bool uart_present = lpuart_set_iomux(uart_hw_id);
mp_map_t kw_args;
mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
return machine_uart_init_helper(self, n_args - 1, args + 1, &kw_args);
if (uart_present) {
mp_map_t kw_args;
mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
return machine_uart_init_helper(self, n_args - 1, args + 1, &kw_args);
} else {
return mp_const_none;
}
}
// uart.init(baud, [kwargs])