This commit adds support for machine.I2S on the mimxrt port. The I2S API
is consistent with the existing stm32, esp32, and rp2 implementations.
I2S features:
- controller transmit and controller receive
- 16-bit and 32-bit sample sizes
- mono and stereo formats
- sampling frequencies from 8kHz to 48kHz
- 3 modes of operation:
- blocking
- non-blocking with callback
- uasyncio
- configurable internal buffer
- optional MCK
Tested with the following development boards:
- MIMXRT1010_EVK, MIMXRT1015_EVK, MIMXRT1020_EVK, MIMXRT1050_EVK
- Teensy 4.0, Teensy 4.1
- Olimex RT1010
- Seeed ARCH MIX
Tested with the following I2S hardware peripherals:
- UDA1334
- GY-SPH0645LM4H
- WM8960 codec on board the MIMXRT boards and separate breakout board
- INMP441
- PCM5102
- SGTL5000 on the Teensy audio shield
Signed-off-by: Mike Teachman <mike.teachman@gmail.com>
Using the keyword argument cs=nnn in the constructor. The cs1
pin has to be defined in mpconfigboard.h.
Note: Only a few boards have the CS1 pin exposed to the connectors.
UART 0 is attached to the Debug USB port. The settings are
115200 Baud, 8N1.
For MIMXRT1010_EVK this is identical to UART1. For the other boards,
this is an additional UART.
Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the
duty cycle. The basic API is supported as documentated, except that
keyword parameters are accepted for both the instatiaton and the
PWM.init() call.
Extensions: support PWM for channel pairs. Channel pairs are declared by
supplying 2-element tuples for the pins. The two channels of a pair must
be the A/B channel of a FLEXPWM module. These form than a complementary
pair.
Additional supported keyword arguments:
- center=value Defines the center position of a pulse within the pulse
cycle. The align keyword is actually shortcut for center.
- sync=True|False: If set to True, the channels will be synchronized to a
submodule 0 channel, which has already to be enabled.
- align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized
channels are Center-Aligned or Edge-aligned. The channels must be either
complementary a channel pair or a group of synchronized channels. It may
as well be applied to a single channel, but withiout any benefit.
- invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the
first pin, bit 1 the second.
- deadtime=time_ns time of complementary channels for delaying the rising
slope.
- xor=0|1|2 xor causes the output of channel A and B to be xored. If
applied to a X channel, it shows the value oif A ^ B. If applied to an A
or B channel, both channel show the xored signal for xor=1. For xor=2,
the xored signal is split between channels A and B. See also the
Reference Manual, chapter about double pulses. The behavior of xor=2 can
also be achieved using the center method for locating a pulse within a
clock period.
The output is enabled for board pins only.
CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal
will not be routed to the output. That applies only to FLEXPWM pins. The
use of QTMR pins which are not board pins will be rejected.
As part of this commit, the _WFE() statement is removed from
ticks_delay_us64() to prevent PWM glitching during calls to sleep().
- Moves definition of BOARD_FLASH_SIZE and other header files related to
flash configuration into the Makefile.
- Adds board specific clock_config.h.
- Adds board.h, pin_mux.h, and peripherals.h as they are
required by NXP MCU SDK in order to use our own clock_config.h.
- Renames board specific FlexSPI configuration files.
- Updates flash frequency of MIMXRT1020_EVK
- Creates separated flash_config files for QSPI NOR and
QSPI Hyper flash.
- Unifies VFS start address to be @ 1M for 1010 and 1020 boards.
- Unifies 1050EVK boards
- Adds support to both NOR and HyperFlash on boards with
both capabilities.
- Adds automatic FlexRAM initialization to start-up code based on
linker script and NXP HAL.
- Applies code formatting to all files in mimxrt port.
With this change the flash configuration is restructured and
organized. This simplifies the configuration process and
provides a better overview of each board's settings. With the integration
of clock_config.h, board.h, pin_mux.h, and peripherals.h we gain better
control of the settings and clock configurations. Furthermore the
implementation of an explicit FlexRAM setup improves the system
performance and allows for performance tuning.
Signed-off-by: Philipp Ebensberger
Hyperflash is used by the MIMXRT1050_EVKB, MIMXRT1060_EVK and
MIMXRT1064_EVK boards.
This commit includes:
- add support for Hyperflash
- modify MIMXRT1060_EVK and MIMXRT1064_EVK to change from QSPI to
hyperflash.
- minor incidental changes to other boards so they still build
Note: Erasing a sector on the hyperflash is slow. It takes about a second,
which seems too long, but matches the data sheet.
This class supports SPI bus controller mode, with blocking transfers.
SPI device numbers start at 0, to comply with the pinout of the Teensy
boards. With the configured clock frequency the fastest baud rate is
33MHz. For messages longer 16 bytes DMA is used. The class uses the
existing framework with extmod/machine_spi.c.
Extended driver options:
- drive=n with n being between 1 and 6 or PIN.POWER_1 to PIN.POWER_6.
Since the pins used by the SPI are fixed, no Pin settings can be made.
Thus the drive option is added allowing to control ringing and crosstalk
on the connection.
- gap_ns=nnnnn is the time between sent data items in a frame given in ns.
Default is 2 clock cycles.
The implementation uses the LPUARTx devices. Up to 8 UARTs can be used,
given that the pins are accessible. E.g. 8 on Teensy 4.1, 5 on
MIMXRT1020_EVK.
For Tennsy 4.0 and 4.1 the UART numbers are as printed on the pinout 1..N.
The MIMXRT10xx-EVK boards have only one UART named, which gets the number
1. All other UART are assigned to different Pins:
MIMXRT1010-EVK:
D0/D1 UART 1
D6/D7 UART 2
A0/D4 UART 3
MIMXRT1020-EVK:
D0/D1 UART 1
D6/D9 UART 2
D10/D12 UART 3
D14/D15 UART 4
A0/A1 UART 5
MIMXRT1050-EVK, MIMXRT1060-EVK, MIMXRT1064-EVK:
D0/D1 UART 1
D7/D6 UART 2
D8/D9 UART 3
A1/A0 UART 4
This commit adds full support for a filesystem on all boards, with a block
device object mimxrt.Flash() and uos.VfsLfs2 enabled.
Main changes are:
- Refactoring of linker scripts to accomodate reserved area for VFS. VFS
will take up most of the available flash. 1M is reserved for code. 9K is
reserved for flash configuration, interrupts, etc.
- Addition of _boot.py with filesystem init code, called from main.c.
- Definition of the mimxrt module with a Flash class in modmimxrt.[ch].
- Implementation of a flash driver class in mimxrt_flash.c. All flashing
related functions are stored in ITCM RAM.
- Addition of the uos module with filesystem functions.
- Implementation of uos.urandom() for the sake of completeness of the uos
module.
It uses sample code from CircuitPython supplied under MIT license, which
uses the NXP SDK example code.
Done in collaboration with Philipp Ebensberger aka @alphaFred who
contributed the essential part to enable writing to flash while code is
executing, among other things.
- modified pin type from pin_obj_t to machine_pin_obj_t
- created machine_pin.c
- implemented basic version of make-pins.py to genertate pins.c/.h files
automatically; the only alternate function currently supported is GPIO
- added af.csv files for all supported MCUs
- replaced pins.c/pins.h files with pin.csv for all boards
- implemented on/off/high/low/value/init methods
- Implemented IN/OUT/OPEN_DRAIN modes
- modified LDFLAGS for DEBUG build to get usefull .elf file for debugging
Signed-off-by: Philipp Ebensberger
This commit implements an LED class with rudimentary parts of a pin C API
to support it. The LED class does not yet support setting an intensity.
This LED class is put in the machine module for the time being, until a
better place is found.
One LED is supported on TEENSY40 and MIMXRT1010_EVK boards.
