It can be enabled/disabled by a configuration switch. The code size
increase is 308 bytes, but it requires RAM space for buffers, the larger
UART object and root pointers.
Allowing to set a time and retrieve the time. It is based on systick_ms()
with the precision of the MCU clock. Unless that is based on a crystal,
the error seen was about 0.5% at room temperature.
It suuports 1 channel @ 10 bit for SAMD21, 2 channels @ 12 bit for SAMD51.
Instantiation by:
dac = machine.DAC(ch) # 0 or 1
Method write:
dac.write(value)
The output voltage range is 0..Vdd.
By reducing the methods to on(), off(), toggle() and call, and using the
method implementation of the machine.Pin class.
The code size reduction is 756 byte.
All board pins that have UART's assigned can be used. Baud rate range is
75 Baud to ~2 MBaud.
No flow control yet, and only RX is buffered. TX buffer and flow control
may be added later for SAMD51 with its larger RAM and Flash.
Its API conforms to the docs. There are 16 IRQ channels available, which
will be used as assignable to the GPIO numbers. In most cases, the irq
channel is GPIO_no % 16.
Changes are:
- Have two separate tables for SAM21 and SAMD51.
- Use a short table for SAMD21.
- Add a comment to each line telling what it's for, making further use
easier.
- Add preliminary handlers/entries for PendSV, EIC and Sercom. These will
be replaced later when the respecitve modules are added.
Features are:
- 3 to 5 different frequency groups.
- Freq range of 1Hz - 24 MHz.
- Duty rate stays stable on freq change.
Keyword options to the PWM constructor:
- device=n Select a specific PWM device. If no device is specified, a free
device is chosen, if available at that pin.
- freq=nnnn
- duty_u16=nnnn
- duty_ns=nnnn
- invert=True/False Allowing two outputs on the same device/channel to have
complementary signals.
If both freq and duty are provided, PWM output will start immediately.
Pins at the same device have the same frequency. If the PWM output number
exceeds the number of channels at the PWM device, the effctive channel_no
is output_no % channel_count. So with a channel count of 4, output 7 is
assigned to channel 3. Pins at a certain channel have the same frequency
and duty rate, but may be seperately inverted.
With the method read_u16(). Keyword arguments of the constructor are:
- bits=n The resolution; default is 12.
- average=n The average of samples, which are taken and cumulated. The
default value is 16. Averaging by hw is faster than averaging
in code.
The ADC runs at a clock freq 1.5 MHz. A single 12 bit conversion takes
8 microseconds.
The pin af table is a representation of the MUX table from the data sheet.
It provides information for each pin about the supported device functions.
That information is needed by pin.irq, machine.ADC, machine.PWM,
machine.UART, machine.SPI and machine.I2C. For each of these, the table
tells for each pin, which device number, af number and pad number is
assigned. Using the table gives a straight, uniform access to the
information, where the benefit outweights the size of the table, which is
not that large.
The tables are MCU-specific. It is not required to tell for each board,
which and where each of the above devices is available. That makes addding
boards easy.
Note: The information for DAC and I2S was not included, since it affects
only a few pins.
Changes in this commit are:
- Use mphal_xx functions whenever possible.
- Remove obsolete includes.
- Clean up traces of a non-functional pin.irq() from earlier builds.
Pin.irq() will be added in further commits in a working manner.
The changes in this commit are:
- Add an interface for pin open-drain mode.
- Improve ticks_us() by using the us-counter.
- Improve ticks_cpu() by using the CPU's SysTick.
Clock settings:
- GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51).
- GCLK1: 32768 Hz for driving the PLL.
- GCLK2: 48 MHz for tzhe peripheral clock.
- GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer.
- GCLK8: 1 kHz for WDT (SAMD21 only).
If a 32 kHz crystal is present, it will be used as clock source. Otherwise
the DFLL48M in open-loop mode is used.
GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified
range is 96 MHz - 120 MHz.
These two boards are used for testing, so it is favorable to have them
added early.
The full test set is:
- ADAFRUIT_FEATHER_M4_EXPRESS: SAMD51 with 32kHz crystal.
- ADAFRUIT_ITSYBITSY_M0_EXPRESS: SAMD21 without crystal.
- ADAFRUIT_ITSYBITSY_M4_EXPRESS: SAMD51 without crystal.
- SEEED_XIAO: SAM21 with 32kHz crystal.
Instead of being an explicit field, it's now a slot like all the other
methods.
This is a marginal code size improvement because most types have a make_new
(100/138 on PYBV11), however it improves consistency in how types are
declared, removing the special case for make_new.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Since commit e65d1e69e8 there is no longer an
io.FileIO class, so this option is no longer needed.
This option also controlled whether or not files supported being opened in
binary mode (eg 'rb'), and could, if disabled, lead to confusion as to why
opening a file in binary mode silently did the wrong thing (it would just
open in text mode if MICROPY_PY_IO_FILEIO was disabled).
The various VFS implementations (POSIX, FAT, LFS) were the only places
where enabling this option made a difference, and in almost all cases where
one of these filesystems were enabled, MICROPY_PY_IO_FILEIO was also
enabled. So it makes sense to just unconditionally enable this feature
(ability to open a file in binary mode) in all cases, and so just remove
this config option altogether. That makes configuration simpler and means
binary file support always exists (and opening a file in binary mode is
arguably more fundamental than opening in text mode, so if anything should
be configurable then it should be the ability to open in text mode).
Signed-off-by: Damien George <damien@micropython.org>
These were added in Python 3.5.
Enabled via MICROPY_PY_BUILTINS_BYTES_HEX, and enabled by default for all
ports that currently have ubinascii.
Rework ubinascii to use the implementation of these methods.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
For bare metal ARM & xtensa targets, passing -g will make the ELF file
larger but doesn't change the binary size. However, this means tools like
gdb, addr2line, etc can extract source-level information from the ELF.
Also standardise -ggdb to -g, these produce the exact same ELF file on
arm-none-eabi-gcc and will use DWARF format for all these ports.
This uses MP_REGISTER_ROOT_POINTER() to register the readline_history root
pointer array used by shared/readline.c and removes the registration from
all mpconfigport.h files.
This also required adding a new MICROPY_READLINE_HISTORY_SIZE config option
since not all ports used the same sized array.
Signed-off-by: David Lechner <david@pybricks.com>
This separates extmod source files from `py.mk`. Previously, `py.mk`
assumed that every consumer of the py/ directory also wanted to include
extmod/. However, this is not the case. For example, building mpy-cross
uses py/ but doesn't need extmod/.
This commit moves all extmod-specific items from `py.mk` to `extmod.mk` and
explicitly includes `extmod.mk` in ports that use it.
Signed-off-by: David Lechner <david@pybricks.com>
It's no longer needed because this macro is now processed after
preprocessing the source code via cpp (in the qstr extraction stage), which
means unused MP_REGISTER_MODULE's are filtered out by the preprocessor.
Signed-off-by: Damien George <damien@micropython.org>
For ports with MICROPY_VFS and MICROPY_PY_IO enabled their configuration
can now be simplified to use the defaults for mp_import_stat and
mp_builtin_open.
This commit makes no functional change, except for the following minor
points:
- the built-in "open" is removed from the minimal port (it previously did
nothing)
- the duplicate built-in "input" is removed from the esp32 port
- qemu-arm now delegates to VFS import/open
Signed-off-by: Damien George <damien@micropython.org>
