Changes in this commit:
- Move the pwm_seq array to the p_config data structure. That prevents
potential resource collisions between PWM devices.
- Rename the keyword argument 'id' to 'device'. That's consistent with the
SAMD port as the other port allowing to specify it.
This is a best-effort implementation of write polling. It's difficult to
do correctly because if there are multiple output streams (eg UART and USB
CDC) then some may not be writeable while others are. A full solution
should also have a return value from mp_hal_stdout_tx_strn(), returning the
number of bytes written to the stream(s). That's also hard to define.
The renesas-ra and stm32 ports already implement a similar best-effort
mechanism for write polling.
Fixes issue #11026.
Signed-off-by: Damien George <damien@micropython.org>
Prior to this change, setting of UART parameters like parity, stop bits or
data bits did not work correctly. As suggested by @iabdalkader, adding
__DSB() fixes the problem, making sure that changes to the UART LCR_H
register are seen by the peripheral.
Note: the FIFO is already enabled in the call to uart_init(), so the call
to uart_set_fifo_enabled() is not required, but kept for visibility.
Fixes issue #10976.
The following have been tested and are working:
- 550MHz CPU frequency
- UART REPL via ST-Link
- USB REPL and mass storage
- 3x LEDs and 1x user button
- Ethernet
Signed-off-by: Damien George <damien@micropython.org>
For builds with DEBUG=1 and MICROPY_HW_ENABLE_UART_REPL=1, calling
stdio_init_all() in main() detaches the UART input from REPL. This change
suppresses calling stdio_init_all() then.
Previously, setting MICROPY_HW_ENABLE_USBDEV to 0 caused build errors. The
change affects the nrf and samd ports as well, so MICROPY_HW_ENABLE_USBDEV
had to be explicitly enabled there.
The configuration options MICROPY_HW_ENABLE_USBDEV and
MICROPY_HW_ENABLE_UART_REPL are independent, and can be enabled or disabled
by a board.
Signed-off-by: Damien George <damien@micropython.org>
Changes in this commit:
- Add the timeout and timeout_char keyword options.
- Make uart.read() non-blocking.
- Add uart.any().
- Add ioctl MP_STREAM_POLL handling.
- Change uart.write() into non-busy waiting. uart.write() still waits until
all data has been sent, but calls MICROPY_EVENT_POLL_HOOK while waiting.
uart.write() uses DMA for transfer. One option would be to add a small
local buffer, such that transfers up to the size of the buffer could be
done without waiting.
- As a side effect to the change of uart.write(), uart.txdone() and ioctl
flush now report/wait correctly for the end of transmission.
- Change machine_hard_uart_buf_t in machine_hard_uart_obj_t to an instance
of that struct, rather than a pointer to one.
Even if boards do not have a clock crystal. In that case, the clock
quality will be very poor.
Always having machine.RTC means that the date/time can be set in a way that
is consistent with other ports.
This commit also removes the special code in modutime.c for devices without
the RTC class.
Signed-off-by: Damien George <damien@micropython.org>
These have the same frequency, but can have different duty cycle and
polarity.
pwm.deinit() stops all channels of a module, but does not release the
module. pwm.init() without arguments restarts all outputs.
Using extmod/machine_pwm.c for the Python bindings and the existing
softpwm.c driver, by just adding the interface.
Properties:
- Frequency range 1-3906 Hz.
- All PWM outputs run at the same frequency but can have different duty
cycles.
- Limited to the P0.x pins.
Since it uses the existing softpwm.c mechanism, it will be affected by
playing music with the music class.
This is a breaking change, making the hardware PWM on the nrf port
compatible with the other ports providing machine.PWM.
Frequency range 4Hz - ~5.4 MHz. The base clock range is 125kHz to 16 MHz,
and the divider range is 3 - 32767.
The hardware supports up to four outputs per PWM device with different duty
cycles, but only one output is (and was) supported.
Borrowing an idea from the mimxrt port (also stm32 port): in the loader
input file memmap_mp.ld calculate __GcHeapStart and __GcHeapEnd as the
unused RAM. Then in main.c use these addresses as arguments to gc_init().
The benefits of this change are:
1) When libraries are added or removed in the future changing BSS usage,
main.c's sizing of the GC heap does not need to be changed.
2) Currently these changes make the GC area about 30 KBytes larger, eg on
PICO_W the GC heap increases from 166016 to 192448 bytes. Without that
change this RAM would never get used.
3) If someone wants to disable one or more SRAM blocks on the RP2040 to
reduce power consumption it will be easy: just change the MEMORY section
in memmap_mp.ld. For instance to not use SRAM2 and SRAM3 change it to:
MEMORY
{
FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k
RAM(rwx) : ORIGIN = 0x21000000, LENGTH = 128k
SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
}
Then to turn off clocks for SRAM2 and SRAM3 from MicroPython, set the
appropriate bits in WAKE_EN0 and SLEEP_EN0.
Tested by running the firmware.uf2 file on PICO_W and displaying
micropython.mem_info(). Confirmed GC total size approximately matched the
size calculated by the loader.
Signed-off-by: cpottle9 <cpottle9@outlook.com>
This function seems to work fine in multi-core applications now.
The delay is now in units of microseconds instead of depending on the clock
speed, and is adjustable by board configuration headers.
Also added documentation.
These changes allow the firmware to support both the REV-1 and REV-2
versions of the board:
- Freeze the new device drivers used in REV-2.
- Add a board-level module that abstracts the IMU chipset.
Changes are:
- Freeze micropython-lib time module to get strftime.
- Reserve the last 1MB of QSPI flash for (optional) WiFi firmware storage.
- Disable SD card mount on boot.
- Enable high-speed BLE firmware download.
This is for boards without networking support so that the default boot.py
continues to work.
Also update boot.py to use network.country and network.hostname instead.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This removes the previous WiFi driver from drivers/cyw43 (but leaves behind
the BT driver), and makes the stm32 port (i.e. PYBD and Portenta) use the
new "lib/cyw43-driver" open-source driver already in use by the rp2 port.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Rather than duplicating the implementation of `network`, this allows
ESP8266 to use the shared one in extmod. In particular this gains access
to network.hostname and network.country.
Other than adding these two methods, there is no other user-visible change.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Rather than duplicating the implementation of `network`, this allows ESP32
to use the shared one in extmod. In particular this gains access to
network.hostname and network.country.
Set default hostnames for various ESP32 boards.
Other than adding these two methods and the change to the default hostname,
there is no other user-visible change.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This provides a standard interface to setting the global networking config
for all interfaces and interface types.
For ports that already use either a static hostname (mimxrt, rp2) they will
now use the configured value. The default is configured by the port
(or optionally the board).
For interfaces that previously supported .config(hostname), this is still
supported but now implemented using the global network.hostname.
Similarly, pyb.country and rp2.country are now deprecated, but the methods
still exist (and forward to network.hostname).
Because ESP32/ESP8266 do not use extmod/modnetwork.c they are not affected
by this commit.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Makefile's support "else ifdef", so use it to make the logic clearer.
Also dedent some associated lines for consistency.
Signed-off-by: Damien George <damien@micropython.org>
This matches the behavior of the makefile ports but implemented for CMake,
making it easy to specify custom board definitions.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This matches the behavior of the makefile ports but implemented for CMake,
making it easy to specify custom board definitions.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This allows:
$ make BOARD_DIR=path/to/board
to infer BOARD=board, rather than the previous behavior that required
additionally setting BOARD explicitly.
Also makes the same change for VARIANT_DIR -> VARIANT on Unix.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Signed-off-by: Damien George <damien@micropython.org>
This RNG passes many of the Diehard tests and also the AIS31 test suite.
The RNG is quite slow, delivering 200bytes/s.
Tested on boards with and without a crystal.
It turned out that the result of calling ticks_us() was always either odd
or even, depending on some internal state during boot. So the us-counter
was set to a 2 MHz input and the result shifted by 1. The counting period
is still long enough, since internally a (now) 63 bit value is used for us.
By using the phase jitter between the DFLL48M clock and the FDPLL96M clock.
Even if both use the same reference source, they have a different jitter.
SysTick is driven by FDPLL96M, the us counter by DFLL48M. As a random
source, the us counter is read out on every SysTick and the value is used
to accumulate a simple multiply, add and xor register. According to tests
it creates about 30 bit random bit-flips per second. That mechanism will
pass quite a few RNG tests, has a suitable frequency distribution and
serves better than just the time after boot to seed the PRNG.
Allowing to increase the clock a little bit to 54Mhz. Not much of a gain,
but useful for generating a RNG entropy source from the jitter between
DFLL48M and FDPLL96M.
Remove two SPARKFUN_SAMD51_THINGS_PLUS pin definitions. There were
definitions of TXD and RXD, but these pins do not exist on the board. They
were only shown in the schematics.
Also remove any reference to LED_. This is just a text change, no
functional change.
For compatibility with other ports. Code increase up to ~1250 bytes for
SAMD21. The feature is configurable via MICROPY_PY_MACHINE_PIN_BOARD_CPU
in case flash memory is tight.
This further aligns the features available on Pico and Pico W boards.
os.dupterm is generally useful, but can still be disabled by a board if
needed. hashlib.sha1 requires mbedtls for the implementation, but that's
always available (due to ucryptolib's requirements). The entire hashlib
module can still be disabled by an individual board if needed.
Fixes issue #7881.
Signed-off-by: Damien George <damien@micropython.org>
Before, both uwTick and mp_hal_ticks_ms() were used as clock source. That
assumes, that these two are synchronous and start with the same value,
which may be not the case for all ports. If the lag between uwTick and
mp_hal_ticks_ms() is larger than the timer interval, the timer would either
rush up until the times are synchronous, or not start until uwTick wraps
over.
As suggested by @dpgeorge, MICROPY_SOFT_TIMER_TICKS_MS is now used in
softtimer.c, which has to be defined in a port's mpconfigport.h with
the variable that holds the SysTick counter.
Note that it's not possible to switch everything in softtimer.c to use
mp_hal_ticks_ms() because the logic in SysTick_Handler that schedules
soft_timer_handler() uses (eg on mimxrt) the uwTick variable directly
(named systick_ms there), and mp_hal_ticks_ms() uses a different source
timer. Thus it is made fully configurable.
The default now includes all sub-components (security, l2cap, etc)
and using the kwarg options is no longer supported.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
The default now includes all sub-components (security, l2cap, etc)
and using the kwarg options is no longer supported.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Prior to this commit, on Pico W (where the CYW43 driver is enabled) the PIO
instruction memory was not released on soft reset, so using PIO after a
soft reset would eventually (after a few soft resets) lead to ENOMEM when
allocating a PIO program.
This commit fixes that by tracking the use of PIO memory by this module and
freeing it on soft reset.
Similarly, use of the state machines themselves are tracked and released on
soft reset.
Fixes issue #9003.
Signed-off-by: Damien George <damien@micropython.org>
Make this more generally useful and in line with what the mingw
and unix ports do: 16bit dig size to work on 32bit ports, a
self-contained qstrdefs.preprocessed.h because makemanifest.py
uses that, and a dev variant which effectively puts this to use:
previously the uasyncio module wasn't frozen but instead tests
ran by importing it from the extmod/ directory.
The mpversion.h file must exist before py/ source can be preprocessed,
but this went unnoticed because micropython.vcxproj always calls
MakeVersionHdr before MakeQstrDefs.
The variant.props may have incompatible build options which break
the mpy-cross build and in any case mpy-cross has nothing to do
with variant support.
This is in line with the change made for other ports in d53c3b6a: since
the default output directory already includes the variant name in it
there's no need to add it to the executable as well.
This will ensure that any board with networking support gets:
- webrepl
- mip
- urequests
- ntptime
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This drops the `.cpu` directive from the ARM gchelper_*.s files. Having
this directive breaks the linker when targeting older CPUs (e.g. `-mthumb
-mthumb-interwork` for `-mcpu=arm7tdmi`). The actual target CPU should be
determined by the compiler options.
The exact CPU doesn't actually matter, but rather the supported assembly
instruction set. So the files are renamed to *_thumb1.s and *thumb2.s to
indicate the instruction set support instead of the CPU support.
Signed-off-by: David Lechner <david@pybricks.com>
Prior to this commit, Pin(Pin.OPEN_DRAIN, value=0) would not set the
initial value of the open-drain pin to low, instead it would be high.
Signed-off-by: Damien George <damien@micropython.org>
The mp_plat_print output is already being used by the subsequent call to
mp_obj_print_exception(). And this eliminates all references to printf for
this port (at least in non-debug builds).
Signed-off-by: Damien George <damien@micropython.org>
The delay is 1 ms. It avoids the crashes reported by the
issues #8289, #8792 and #9236 with esp-idf versions >= 4.2, but does
not solve an underlying problem in the esp-idf.
The major setting is about the PHY interface configuration. The
configuration matches the Olimex ESP32 Gateway as well.
Tested with esp-idf v4.2.4 and Olimex ESP32 POE boards.
`esp_eth_ioctl(ETH_CMD_S_MAC_ADDR)` sets the MAC address of the hardware
device, but we also need to notify the upper layers of the change so that
e.g. DHCP work properly.
Add support for various SPI-based ethernet chips (W5500, KSZ8851SNL,
DM9051) to the ESP32 port. This leverages the existing support in ESP-IDF
for these chips -- which configures these chips in "MAC raw" mode -- and
the existing support for network.LAN in the ESP32 port. In particular,
this doesn't leverage the wiznet5k support that is used on the rp2 and
stm32 ports (because that's for native use of lwIP).
Tested on the POE Featherwing (with the SJIRQ solder jumper bridged) and a
ESP32-S3 feather.
A note about the interrupt pin: The W5500 implementation within ESP-IDF
relies on hardware interrupt, and requires the interrupt pin from the W5500
to be wired to a GPIO. This is not the case by default on the Adafruit
Ethernet FeatherWing, which makes it not directly compatible with this
implementation.
Both the direction and the Pin used for ref_clk can now be configured. It
Requires at least idf v4.4. The new keyword arguments to the constructor
are:
- ref_clk_mode=mode: with mode being Pin.IN or Pin.OUT. If it is not set,
then the default configuration is used, which may be configured by
kconfig settings.
- ref_clk=pin_obj: which defines the Pin used for ref_clk. This is either
Pin(0), Pin(16) or Pin(17). No check is done for the pin number. If it
is the wrong one, it simply will not work. Besides that, no harm.
LAN8710 uses the same drivers as LAN8720, so this commit just adds the
names. Alternatively, both could be summarised under LAN87xx, like the
esp-idf does.
Pin defines are:
- For Pico define board pins and the default LED pin (WL_GPIO25).
- For Pico-W define board pins, external pins and the default
LED pin (WL_GPIO0).
- For the Nano-RP2040, define board pins, external pins and
the default LED pin (GPIO25)
- For all other boards, the pins.csv defines the LED pin (if any)
for backwards compatibility with code that assumes there's always
an LED pin.
This commit adds support for generating named pin mappings for all pins
including CPU, board-defined, LED and externally controlled pins. CPU pins
are mapped to `pin_GPIO<n>`, externally-controlled pins are mapped to
`pin_EXT_GPIO<n>`, and defined conditionally (up to 10 pins, and can be
expanded in the future), and they are non-const to allow `machine-pin.c` to
write the pin object fields. Both CPU and externally controlled pins are
generated even if there's no board CSV file; if one exists it will just be
added to board pins.
Handle externally controlled GPIO pins more generically, by removing all
CYW43-specific code from `machine_pin.c`, and adding hooks to initialise,
configure, read and write external pins. This allows any driver for an
on-board module which controls GPIO pins (such as CYW43 or NINA), to
provide its own implementation of those hooks and work seamlessly with
`machine_pin.c`.
This commit uses the REGION_ALIAS GNU linker command to simplify the linker
snippets and consolidate the duplication.
Signed-off-by: Damien George <damien@micropython.org>
To allow the USB to work in cases where there is a lot of filesystem
access, in particular on boot.
For example, registering of the USB CDC interface may fail if:
- the board file system is lfs2 (default), and
- sys.path contains entries for the local file system (default), and
- files are imported by boot.py or main.py from frozen bytecode of the file
system (common) and the file system contains many files, like 100.
In that case the board is very busy with scanning LFS, and registering the
USB interface seems to time out. This commit fixes this by allowing the
USB to make progress during filesystem reads.
Also switch existing MICROPY_EVENT_POLL_HOOK uses in this file to
MICROPY_EVENT_POLL_HOOK_FAST now that the latter macro exists.
When switching from a special function like SPI to an input or output,
there was a brief period after the function was disabled but before the
pin's I/O state was configured, in which the state would be poorly defined.
This fixes the problem by switching off the special function after fully
configuring the I/O state.
Fixes#10226.
Signed-off-by: Paul Grayson <pdg@alum.mit.edu>
There were several places where 32-bit integer could overflow with
frequencies of 2^28 Hz or above (~268 MHz). This fixes those overflows and
also introduces rounding for more accurate duty_ns computations.
Signed-off-by: Paul Grayson <pdg@alum.mit.edu>
This changes the freq() and duty_u16() functions to use more simpler, more
accurate formulas, in particular increasing the frequency accuracy from a
few percent to a fraction of a percent in many cases.
Signed-off-by: Paul Grayson <pdg@alum.mit.edu>
This commit prevents the device from "hanging" when using lightsleep while
the WiFi chip is active.
Whenever the WiFi chip wants to interrupt the microcontroller to notify it
for a new package, it sets the CYW43_PIN_WL_HOST_WAKE pin to high,
triggering an IRQ. However, as polling the chip cannot happen in an
interrupt handler, it subsequently notifies the pendsv-service to do a poll
as soon as the interrupt handler ended. In order to prevent a new
interrupt from happening immediately afterwards, even before the poll has
run, the IRQ handler disables interrupts from the pin.
The first problem occurs, when a WiFi package arrives while the main loop
is in cyw43-code. In order to prevent concurrent access of the hardware,
the network code blocks pendsv from running again while entering lwIP code.
The same holds for direct cyw43 code (like changing the cyw43-gpios, i.e.
the LED on the Pico W). While the pendsv is disabled, interrupts can still
occur to schedule a poll (and disable further interrupts), but it will not
run. This can happen while the microcontroller is anywhere in rp2040 code.
In order to preserve power while waiting for cyw43 responses,
cyw43_configport.h defines CYW43_DO_IOCTL_WAIT and
CYW43_SDPCM_SEND_COMMON_WAIT to __WFI(). While this might work in most
cases, there are 2 edge cases where it fails:
- When an interrupt has already been received by the cyw43 stack, for
example due to an incoming ethernet packet.
- When the interrupt from the cyw43 response comes before the
microcontroller entered the __WFI() instruction.
When that happens, wfi will just block forever as no further interrupts are
received. The only way to safely use wfi to wake up from an interrupt is
inside a critical section, as this delays interrupts until the wfi is
entered, possibly resuming immediately until interrupts are reenabled and
the interrupt handler is run. Additionally this critical section needs to
check whether the interrupt has already been disabled and pendsv was
triggered, as in such a case, wfi can never be woken up, and needs to be
skipped, because there is already a package from the network chip waiting.
Note that this turns cyw43_yield into a nop (and thereby the cyw43-loops
into busy waits) from the second time onwards, as after the first call, a
pendsv request will definitely be pending. More logic could be added, to
explicitly enable the interrupt in this case.
Regarding lightsleep, this code has a similar problem. When an interrupt
occurs during lightsleep, the IRQ and pendsv handler and thereby poll are
run immediately, with the clocks still disabled, causing the SPI transfers
to fail. If we don't want to add complex logic inside the IRQ handler we
need to protect the whole lightsleep procedure form interrupts with a
critical section, exiting out early if an interrupt is pending for whatever
reason. Only then we can start to shut down clocks and only enable
interrupts when the system is ready again. Other interrupt handlers might
also be happy, that they are only run when the system is fully operational.
Tested on a Pico W, calling machine.lightsleep() within an endless loop and
pinging from the outside.
This required to add two functions down the stack to uart.c and ra.sci.c.
- One for telling, whther the transmission is busy.
- One for reporting the size of the TX buffer.
Tested with a EK-RA6M2 board.
See the previous commit, except in this case the customisation didn't
actually do anything so can just be removed.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This was previously implemented by adding additional members to the
mp_obj_type_t defined for each NIC, which is difficult to do cleanly with
the new object type slots mechanism. The way this works is also not
supported on GCC 8.x and below.
Instead replace it with the type protocol, which is a much simpler way of
achieving the same thing.
This affects the WizNet (in non-LWIP mode) and Nina NIC drivers.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
Changes in this commit:
- Clear and mask D2 EXTIs.
- Set correct voltage scaling level for standby mode.
- Disable debug MCU (if debugging is disabled), for all MCU series.
It keeps compatibility with the XIAO bootloader by:
- using Soft Device 7.3.0
- reserving 48k memory for the bootloader.
So on double reset a drive pops for uploading an uf2 image or a nrfutil zip
pkg file. Instructions to create it from a hex file are included. The
bootloader can as well be activated with the touch 1200 option of nrfutil.
The script download_ble_stack.sh has been adapted to get the version 7.3.0
soft device files. It may have to be executed once before building.
The file system is set to 256k and the pin definitions are adapted.
Besides that, it has the common functionality and omissions. The on-board
sensors and additional flash can be supported by Python scripts.
This was introduced by 35fb90bd57, but
it is much simpler and essentially the same to just use
`tud_cdc_n_connected()`.
The only difference is that tud_cdc_n_connected() only checks for DTR,
but this is correct anyway: DTR indicates device presence, RTS indicates
that the host wants to receive data.
Signed-off-by: Damien Tournoud <damien@platform.sh>
usocket_events_deinit will only be available if MICROPY_PY_USOCKET_EVENTS
is enabled (which is only enabled when webrepl is enabled).
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
ADC: The argument of vref=num is an integer. Values for num are:
SAMD21:
0 INT1V 1.0V voltage reference
1 INTVCC0 1/1.48 Analog voltage supply
2 INTVCC1 1/2 Analog voltage supply (only for VDDANA > 2.0V)
3 VREFA External reference
4 VREFB External reference
SAMD51:
0 INTREF internal bandgap reference
1 INTVCC1 Analog voltage supply
2 INTVCC0 1/2 Analog voltage supply (only for VDDANA > 2.0v)
3 AREFA External reference A
4 AREFB External reference B
5 AREFC External reference C (ADC1 only)
DAC: The argument of vref=num is an integer. Suitable values:
SAMD21:
0 INT1V Internal voltage reference
1 VDDANA Analog voltage supply
2 VREFA External reference
SAMD51:
0 INTREF Internal bandgap reference
1 VDDANA Analog voltage supply
2 VREFAU Unbuffered external voltage reference (not buffered in DAC)
4 VREFAB Buffered external voltage reference (buffered in DAC).
Changes in this commit:
- Do not deinit IRQ when uart.deinit() is called with an inactive object.
- Remove using it for the finaliser. There is another machanism for soft
reset, and it is not needed otherwise.
- Do not tag the UART buffers with MP_STATE_PORT, it is not required.
Clearing the DRE flag for the transmit interrupt at the end of a
uart.write() also cleared the RXC flag disabling the receive interrupt.
This commit also changes the flag set/clear mechanism in the driver for SPI
as well, even if it did not cause a problem there. But at least it saves a
few bytes of code.
Applies to both SPI and I2C. The underflow caused high baudrate settings
resulting in the lowest possible baudrate. The overflow resulted in
erratic baudrates, not just the lowest possible.
The datasheet on page 55 shows PF0 (SDA) and PF1 (SCL) are the pins for
I2C2, but these pins do not work. Checking the MBED pinout for the
NUCLEO-F429ZI shows:
I2C1: PB8 (SCL) and PB9 (SDA).
I2C2: PB10 (SCL) and PB11 (SDA).
Both of these work and can be scanned and find devices connected to them.
Signed-off-by: Dale Weber <hybotics.sd@gmail.com>.
This changes the signatures of QSPI write_cmd_data, write_cmd_addr_data and
read_cmd_qaddr_qdata so they return an error code. The softqspi and stm32
hardware qspi driver are updated to follow this new signature. Also the
spiflash driver is updated to use these new return values.
Signed-off-by: Damien George <damien@micropython.org>
The assertion that is added here (to gc.c) fails when running this new test
if ALLOC_TABLE_GAP_BYTE is set to 0.
Signed-off-by: Jeff Epler <jepler@gmail.com>
Signed-off-by: Damien George <damien@micropython.org>
The STM32H7xx HAL LPUART AF macros are missing the number, this HAL is the
only one that's inconsistent in the way it defines LPUART AF macros, so we
only need to define them for H7.
Prior to this commit, only sector 0 was erase/write protected, which may
not be enough to protect all of mboot (especially if mboot lives at a
higher address than the start of flash).
This commit makes sure all internal flash sectors that mboot lives in are
protected from erasing and writing. The linker script must define
_mboot_writable_flash_start for this to work.
Signed-off-by: Damien George <damien@micropython.org>
The original ESP32 only supports timer source clock APB so it doesn't need
and doesn't have a clk_src field.
The ESP32C3 supports timer source clock APB and XTAL so it does have a
clk_src field, and this needs to be configured to get the correct period.
Fixes#8084.
Follow up to 8a91c719 to no longer explicitly disable BLE in
mpconfigport.h.
This work was funded through GitHub Sponsors.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
For STM32L4, hardware I2C can be implemented by using TIMINGR.
This commit enables:
- Use of hardware I2C in machine.I2C.
- Specifying a frequency greater than or equal to 400KHz with pyb.I2C.
For STM32L4 series, the internal sensors are connected to:
- ADC1_IN0: Internal voltage reference
- ADC1_IN17: Temperature sensor
- ADC1_IN18: VBAT battery voltage monitoring
but ADC_CHANNEL_VREFINT, ADC_CHANNEL_VBAT, ADC_CHANNEL_TEMPSENSOR are not
defined as 0, 17, 18.
This commit converts channel 0, 17, 18 to ADC_CHANNEL_x in
adc_get_internal_channel().
Prior to this commit, the actual I2C frequency can be faster than specified
one and it may exceed the I2C's specification for Fast Mode. The frequency
of SCL should be less than or equal to 400KHz in Fast Mode.
This commit fixes this issue for F4 MCUs by rounding up the division in the
frequency calculation.
Excuting the code:
i2c = I2C(1, I2C.CONTROLLER, dma=True)
tmp = i2c.recv(1, i2c_addr)
recv_data = bytearray(56)
i2c.recv(recv_data, i2c_addr)
The second i2c.recv() fails with OSError: [Errno 110] ETIMEDOUT. When
receiving greater than or equal to 2 bytes at first i2c.recv(), the second
i2c.recv() succeeds. This issue does not occur without DMA.
Details of change: when executing I2C with DMA:
- Bit 11 of I2Cx_CR2 (DMA Request Enable) should be 1 to indicate that DMA
transfer is enabled. This bit is set after I2C event interrupt is
enabled in HAL_I2C_Master_Transmit_DMA()/HAL_I2C_Master_Receive_DMA(), so
DMA Request Enable bit might be 0 in IRQHandler.
- In case of data receive:
- When only 1 byte receiption, clear I2Cx_CR1's bit 10 (ACK).
- When only 2 byte receiption, clear I2Cx_CR1's bit 10 (ACK) and set
bit 11 (POS).
- When greater than or equal to 2 byte receiption, bit 12 of I2Cx_CR2
(DMA Last Transfer) should set to generate NACK when DMA transfer
completed.
Otherwise, the I2C bus may be busy after received data from peripheral.
Instead of defining `MICROPY_PY_BTREE` in `mpconfigport.h` we can define
it via CMake similar to how other ports that use Makefiles define it in
`mpconfigport.mk`.
Signed-off-by: David Lechner <david@pybricks.com>
The RT1176 has two cores, but the actual firmware supports only the CM7.
There are currently no good plans on how to use the CM4.
The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards,
with the following extensions:
- Use 64 MB RAM for the heap.
- Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1)
being the 1GB interface.
The dual LAN port interface can eventually be adapted as well for the
RT1062 MCU.
This work was done in collaboration with @alphaFred.
Avoids the 'warning: Wildcards in project items are not supported'
message from the C++ project system in Visual Studio, while otherwise
remaining completely functional.
A board can now name the CDC ports, eg:
#define MICROPY_HW_USB_CDC_NUM (3)
#define MICROPY_HW_USB_INTERFACE_CDC0_STRING "REPL"
#define MICROPY_HW_USB_INTERFACE_CDC1_STRING "GDB Server"
#define MICROPY_HW_USB_INTERFACE_CDC2_STRING "UART Port"
Signed-off-by: Damien George <damien@micropython.org>
The PWM module now detects if the pin is open drain and if so switches it
to hardware open drain before starting the PWM.
The code that was explicitly turning off the open drain output during PWM
is also removed.
Together these changes allow driving external transistor high-current
switches with PWM.
Signed-off-by: Trammell hudson <hudson@trmm.net>
Changes in this commit:
- Change file system size from 128KB to 64KB in ra6m1_ek.ld.
- Change EK-RA6M1's file system size in renesas-ra port document.
Signed-off-by: Takeo Takahashi <takeo.takahashi.xv@renesas.com>
Changes in this commit:
- Add FLASH_FS region to linker script.
- Add flash storage start & end symbols to linker script.
- Use flash storage start & end symbols in flashbdev.c
Signed-off-by: Takeo Takahashi <takeo.takahashi.xv@renesas.com>
App the mp_ prefix to usbd_ symbols and files which are defined here and
not in TinyUSB.
rp2 only for now. This includes some groundwork for dynamic USB devices
(defined in Python).
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Seems unused outside of spi.c, spi_obj[] array is the expected way to
iterate these.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
This changes the CustomEvent for stdout to use the existing `detail`
property of CustomEvent instead of adding a `data` property.
Signed-off-by: David Lechner <david@pybricks.com>
mip-cmdline adds command-line support to mip, useful for the unix port, via
micropython -m mip ...
Signed-off-by: Damien George <damien@micropython.org>
This commit executes __WFI() on core 0 only to avoid core1 locking up since
it doesn't enable any interrupts by default (except for `SIO_IRQ_PROC1`).
This fixes a lockup when calling `cyw43_do_ioctl` from core1.
Fixes issue #9597.
If USB CDC is connected and the board sends data, but the host does not
receive the data, the device locks up. This is fixed in this commit by
having a timeout of 500ms, after which time the transmission is skipped.
If USB CDC is connected and the board sends data, but the host does not
receive the data, the device locks up. This is fixed in this commit by
having a timeout of 500ms, after which time the transmission is skipped.
If USB CDC is connected and the board sends data, but the host does not
receive the data, the device locks up. This is fixed in this commit by
having a timeout of 500ms, after which time the transmission is skipped.
If USB CDC is connected and the board sends data, but the host does not
receive the data, the device locks up. This is fixed in this commit by
having a timeout of 500ms, after which time the transmission is skipped.
Fixes issue #9634.
Most of the content of README.md became obsolete and was replaced by the
documentation of MicroPython. Instead, README.md now shows build
instructions like the other ports.
Including the uasyncio scripts and the drivers for DHT, DS18x20 and
onewire. The uasyncio scripts need about 8k of flash and are not included
for the SAMD21 boards by default.
Emscripten strongly advises the use of optimisation when compiling with
ASYNCIFY enabled. Testing the difference betwen O3 and Os for various
configurations gives:
flags firmware.wasm micropython.js perf
-O3 -s ASYNCIFY 1342003 212845 0 (baseline)
-O3 -s ASYNCIFY -s WASM=0 - 7064750 -30%
-O3 367131 196569 +140%
-O3 -s WASM=0 - 2818260 +30%
-Os -s ASYNCIFY 1135450 213064 +40%
-Os -s ASYNCIFY -s WASM=0 - 6239768 -30%
-Os 295028 196569 +180%
-Os -s WASM=0 - 2271358 +30%
The first row is prior to this commit. The second and third columns show
firmware size (add them to get the total size). The fourth column shows
the approximate change in performance compared to the baseline. The
performance was measured using run-perfbench.py and the error was large, up
to 20%, although general trends in the change in performance could still be
seen.
In summary, using using Os instead of O3 makes it a little bit faster in
all cases, and smaller output (wasm/js) in all cases.
Signed-off-by: Damien George <damien@micropython.org>
This simplifies the config file. This is not a no-op, it does enable a few
new features to bring the port in line with this config level.
Signed-off-by: Damien George <damien@micropython.org>
Checks are added for pwm.freq(), pwm_duty(), pwm_duty_u10() and
pwm.duty_u16(). This avoids a core dump on ESP32C3, and misleading error
messages on Xtensa ESP32 devices.
Set the size of machine_pin_irq_handler array to GPIO_NUM_MAX:
- Min GPIO_NUM_MAX is 22 for IDF_TARGET_ESP32C3.
- Max GPIO_NUM_MAX is 49 for IDF_TARGET_ESP32S3.
The MP_REGISTER_ROOT_POINTER entry must be hard-coded, because the location
that it's evaluated by the compiler does not include the relevant IDF
header to get a definition of GPIO_NUM_MAX.
Each SoC family has its own clocks and timings/timeouts. For I2C, the
default source clock is either APB (ESP32, ESP32-S2) or XTAL (ESP32-S3,
ESP32-C3) as shown in the datasheets. Since
machine_i2c.c/machine_hw_i2c_init() uses the default clk_flags (0), the
alternate low-power clock source is never selected in ESP-IDF
i2c.c/i2c_param_config(). There is not an API in i2c.c to get the source
clock frequency, so a compile-time value is used based on SoC family.
Also, the maximum timeout is different across the SoC families, so use the
I2C_LL_MAX_TIMEOUT constant to eliminate the warning from
i2c_set_timeout().
With these changes, the following results were obtained. The I2C SCL
frequencies were measured with a Saleae logic analyzer.
ESP32 (TTGO T Dislay)
I2C(0, scl=22, sda=21, freq=101781) Measured: 100KHz
I2C(0, scl=22, sda=21, freq=430107) Measured: 400KHz
I2C(0, scl=22, sda=21, freq=1212121) Measured: 941KHz
ESP32-S3 (TTGO T-QT)
I2C(0, scl=34, sda=33, freq=111111) Measured: 107KHz
I2C(0, scl=34, sda=33, freq=444444) Measured: 400KHz
I2C(0, scl=34, sda=33, freq=1111111) Measured: 842KHz
ESP32-C3 (XIAO ESP32C3)
I2C(0, scl=7, sda=6, freq=107816) Measured: 103KHz
I2C(0, scl=7, sda=6, freq=444444) Measured: 380KHz
I2C(0, scl=7, sda=6, freq=1176470) Measured: 800KHz
(ESP32-S2 board was not available for testing.)
So that it doesn't clash with the extmod version.
Also make the default for this enabled, so that most boards do not need to
configure it.
Signed-off-by: Damien George <damien@micropython.org>
This issue affected i.MX RT 1052, 1062 and 1064. It seems to be addressed
by Errata ERR006223, which also mentions i.MX RT101x and 102x, but these
devices worked well even without the change. As a side effect, the current
consumption at an idle REPL drops significantly with this fix.
Fixes issue #7235.
Protect SerCom (UART, SPI, I2C) objects from getting freed by the GC when
they go out of scope without being deinitialized. Otherwise the ISR of a
Sercom may access an invalid data structure.
Any update of freq or duty_cycle requires the previous PWM cycle to be
finished. Otherwise the new settings are not accepted.
Other changes in this commit:
- Report the set duty cycles even when the PWM is not yet started.
- pwm.freq(0) stops the pwm device, instead of raising an expception.
- Clear the duty cycle value cache on soft reset.
Changes are:
- Remove the LED_Pxxx definitions from pins.csv, now that the LED class is
gone.
- Remove the '-' lines.
- Add default lines for USB and SWCLK, SWDIO.
Pin numbers are now the MCU port numbers in the range:
PA0..PA31: 0..31
PB0..PB31: 32..63
PC0..PC31: 64..95
PD0..PD31: 96..127
Pins can be denoted by the GPIO port number, the name as defined in
pins.csv or a string in the form Pxnn, like "PA16" or "PD03".
The pins.c and pins.h files are now obsolete. The pin objects are part of
the AF table.
As result of a simplification, the code now supports using pin names or
numbers instead of pin objects for modules like UART, SPI, PWM, I2C, ADC,
pininfo.
