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stm32/mboot: Add support for G0 MCUs.

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Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George 2023-03-21 17:43:11 +11:00
parent c7923b1139
commit 31638473b7
4 changed files with 28 additions and 3 deletions
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1
ports/stm32/boards/stm32g0b1xe.ld
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@ -3,6 +3,7 @@ MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 352K
FLASH_APP (rx) : ORIGIN = 0x08008000, LENGTH = 320K
FLASH_FS (rx) : ORIGIN = 0x08058000, LENGTH = 160K /* starting @ 352K */
}

4
ports/stm32/i2cslave.h
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@ -43,6 +43,10 @@ static inline void i2c_slave_init(i2c_slave_t *i2c, int irqn, int irq_pri, int a
RCC->APB1ENR |= 1 << (RCC_APB1ENR_I2C1EN_Pos + i2c_idx);
volatile uint32_t tmp = RCC->APB1ENR; // Delay after enabling clock
(void)tmp;
#elif defined(STM32G0)
RCC->APBENR1 |= 1 << (RCC_APBENR1_I2C1EN_Pos + i2c_idx);
volatile uint32_t tmp = RCC->APBENR1; // Delay after enabling clock
(void)tmp;
#elif defined(STM32H7)
RCC->APB1LENR |= 1 << (RCC_APB1LENR_I2C1EN_Pos + i2c_idx);
volatile uint32_t tmp = RCC->APB1LENR; // Delay after enabling clock

7
ports/stm32/mboot/Makefile
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@ -134,7 +134,12 @@ SRC_C += \
SRC_O += \
$(STARTUP_FILE) \
$(SYSTEM_FILE) \
ports/stm32/resethandler.o \
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f0 g0 l0))
SRC_O += ports/stm32/resethandler_m0.o
else
SRC_O += ports/stm32/resethandler.o
endif
ifeq ($(MBOOT_ENABLE_PACKING), 1)

19
ports/stm32/mboot/main.c
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@ -371,6 +371,9 @@ void SystemClock_Config(void) {
#if defined(STM32F4) || defined(STM32F7)
#define AHBxENR AHB1ENR
#define AHBxENR_GPIOAEN_Pos RCC_AHB1ENR_GPIOAEN_Pos
#elif defined(STM32G0)
#define AHBxENR IOPENR
#define AHBxENR_GPIOAEN_Pos RCC_IOPENR_GPIOAEN_Pos
#elif defined(STM32H7)
#define AHBxENR AHB4ENR
#define AHBxENR_GPIOAEN_Pos RCC_AHB4ENR_GPIOAEN_Pos
@ -406,7 +409,9 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed) {
/******************************************************************************/
// FLASH
#if defined(STM32WB)
#if defined(STM32G0)
#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
#elif defined(STM32WB)
#define FLASH_END FLASH_END_ADDR
#endif
@ -426,6 +431,8 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed) {
#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/04*016Kg,01*064Kg,07*128Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT
#elif defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx)
#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/04*032Kg,01*128Kg,07*256Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT
#elif defined(STM32G0)
#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/256*02Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT
#elif defined(STM32H743xx)
#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/16*128Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT
#elif defined(STM32H750xx)
@ -1349,7 +1356,9 @@ void stm32_main(uint32_t initial_r0) {
#endif
#endif
#if __CORTEX_M >= 0x03
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
#endif
#if USE_CACHE && defined(STM32F7)
SCB_EnableICache();
@ -1547,7 +1556,13 @@ void I2Cx_EV_IRQHandler(void) {
#if !USE_USB_POLLING
#if defined(STM32WB)
#if defined(STM32G0)
void USB_UCPD1_2_IRQHandler(void) {
HAL_PCD_IRQHandler(&pcd_fs_handle);
}
#elif defined(STM32WB)
void USB_LP_IRQHandler(void) {
HAL_PCD_IRQHandler(&pcd_fs_handle);