circuitpython/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h

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2020-01-29 22:40:34 -05:00
#define MICROPY_HW_BOARD_NAME "i.MX RT1010 EVK"
#define MICROPY_HW_MCU_NAME "MIMXRT1011DAE5A"
// i.MX RT1010 EVK has 1 board LED
#define MICROPY_HW_LED1_PIN (pin_GPIO_11)
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin))
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))
#define MICROPY_HW_NUM_PIN_IRQS (2 * 32)
// Define mapping logical UART # to hardware UART #
// LPUART1 on USB_DBG -> 0
// LPUART1 on D0/D1 -> 1
// LPUART3 on A0/D4 -> 3
// LPUART4 on D6/D7 -> 2
#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
#define MICROPY_HW_UART_INDEX { 1, 1, 4, 3 }
#define IOMUX_TABLE_UART \
{ IOMUXC_GPIO_10_LPUART1_TXD }, { IOMUXC_GPIO_09_LPUART1_RXD }, \
{ 0 }, { 0 }, \
mimxrt: Support PWM using the FLEXPWM and QTMR modules. Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the duty cycle. The basic API is supported as documentated, except that keyword parameters are accepted for both the instatiaton and the PWM.init() call. Extensions: support PWM for channel pairs. Channel pairs are declared by supplying 2-element tuples for the pins. The two channels of a pair must be the A/B channel of a FLEXPWM module. These form than a complementary pair. Additional supported keyword arguments: - center=value Defines the center position of a pulse within the pulse cycle. The align keyword is actually shortcut for center. - sync=True|False: If set to True, the channels will be synchronized to a submodule 0 channel, which has already to be enabled. - align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized channels are Center-Aligned or Edge-aligned. The channels must be either complementary a channel pair or a group of synchronized channels. It may as well be applied to a single channel, but withiout any benefit. - invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the first pin, bit 1 the second. - deadtime=time_ns time of complementary channels for delaying the rising slope. - xor=0|1|2 xor causes the output of channel A and B to be xored. If applied to a X channel, it shows the value oif A ^ B. If applied to an A or B channel, both channel show the xored signal for xor=1. For xor=2, the xored signal is split between channels A and B. See also the Reference Manual, chapter about double pulses. The behavior of xor=2 can also be achieved using the center method for locating a pulse within a clock period. The output is enabled for board pins only. CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal will not be routed to the output. That applies only to FLEXPWM pins. The use of QTMR pins which are not board pins will be rejected. As part of this commit, the _WFE() statement is removed from ticks_delay_us64() to prevent PWM glitching during calls to sleep().
2021-07-26 06:48:25 -04:00
{ 0 }, { 0 }, \
{ IOMUXC_GPIO_AD_02_LPUART4_TXD }, { IOMUXC_GPIO_AD_01_LPUART4_RXD },
#define MICROPY_HW_SPI_INDEX { 1 }
#define IOMUX_TABLE_SPI \
{ IOMUXC_GPIO_AD_06_LPSPI1_SCK }, { IOMUXC_GPIO_AD_05_LPSPI1_PCS0 }, \
{ IOMUXC_GPIO_AD_04_LPSPI1_SDO }, { IOMUXC_GPIO_AD_03_LPSPI1_SDI }, \
{ IOMUXC_GPIO_AD_02_LPSPI1_PCS1 }
#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx }
#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx }
// Define mapping hardware I2C # to logical I2C #
// SDA/SCL HW-I2C Logical I2C
// D14/D15 LPI2C1 -> 0
// D0/D1 LPI2C2 -> 1
// D6/D7 LPI2C2 -> 1 Alternatively possible GPIO_AD_01, GPIO_AD_02
#define MICROPY_HW_I2C_INDEX { 1, 2 }
#define IOMUX_TABLE_I2C \
{ IOMUXC_GPIO_02_LPI2C1_SCL }, { IOMUXC_GPIO_01_LPI2C1_SDA }, \
{ IOMUXC_GPIO_10_LPI2C2_SCL }, { IOMUXC_GPIO_09_LPI2C2_SDA },
#define MICROPY_PY_MACHINE_I2S (1)
#define MICROPY_HW_I2S_NUM (1)
#define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux }
#define I2S_CLOCK_PRE_DIV { 0, kCLOCK_Sai1PreDiv }
#define I2S_CLOCK_DIV { 0, kCLOCK_Sai1Div }
#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir }
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx }
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx }
#define I2S_WM8960_RX_MODE (1)
#define I2S_AUDIO_PLL_CLOCK (2U)
#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
{ \
.hw_id = _hwid, \
.fn = _fn, \
.mode = _mode, \
.name = MP_QSTR_##_pin, \
.iomux = {_iomux}, \
}
#define I2S_GPIO_MAP \
{ \
I2S_GPIO(1, MCK, TX, GPIO_08, IOMUXC_GPIO_08_SAI1_MCLK), \
I2S_GPIO(1, SCK, RX, GPIO_01, IOMUXC_GPIO_01_SAI1_RX_BCLK), \
I2S_GPIO(1, WS, RX, GPIO_02, IOMUXC_GPIO_02_SAI1_RX_SYNC), \
I2S_GPIO(1, SD, RX, GPIO_03, IOMUXC_GPIO_03_SAI1_RX_DATA00), \
I2S_GPIO(1, SCK, TX, GPIO_06, IOMUXC_GPIO_06_SAI1_TX_BCLK), \
I2S_GPIO(1, WS, TX, GPIO_07, IOMUXC_GPIO_07_SAI1_TX_SYNC), \
I2S_GPIO(1, SD, TX, GPIO_04, IOMUXC_GPIO_04_SAI1_TX_DATA00), \
}