2016-11-03 18:50:59 -04:00
|
|
|
/*
|
2017-08-27 15:02:50 -04:00
|
|
|
* This file is part of the MicroPython project, http://micropython.org/
|
2016-11-03 18:50:59 -04:00
|
|
|
*
|
|
|
|
* The MIT License (MIT)
|
|
|
|
*
|
2017-06-06 16:16:34 -04:00
|
|
|
* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
|
2020-06-03 18:40:05 -04:00
|
|
|
* SPDX-FileCopyrightText: Copyright (c) 2016 Damien P. George
|
2016-11-03 18:50:59 -04:00
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
|
|
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <stdint.h>
|
|
|
|
|
|
|
|
#include "py/runtime.h"
|
2020-08-18 16:08:33 -04:00
|
|
|
#include "common-hal/pwmio/PWMOut.h"
|
|
|
|
#include "shared-bindings/pwmio/PWMOut.h"
|
2018-02-09 19:37:18 -05:00
|
|
|
#include "shared-bindings/microcontroller/Processor.h"
|
2021-08-11 15:10:51 -04:00
|
|
|
#include "shared_timers.h"
|
2019-02-16 20:54:16 -05:00
|
|
|
#include "timer_handler.h"
|
2018-02-09 19:37:18 -05:00
|
|
|
|
|
|
|
#include "atmel_start_pins.h"
|
|
|
|
#include "hal/utils/include/utils_repeat_macro.h"
|
2021-08-11 15:10:51 -04:00
|
|
|
#include "samd/pins.h"
|
2018-06-15 19:16:21 -04:00
|
|
|
#include "samd/timers.h"
|
2022-05-27 15:59:54 -04:00
|
|
|
#include "supervisor/shared/translate/translate.h"
|
2016-11-03 18:50:59 -04:00
|
|
|
|
2017-01-26 21:05:46 -05:00
|
|
|
#undef ENABLE
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
#define _TCC_SIZE(unused, n) TCC##n##_SIZE,
|
|
|
|
#define TCC_SIZES { REPEAT_MACRO(_TCC_SIZE, 0, TCC_INST_NUM) }
|
2021-01-09 15:04:23 -05:00
|
|
|
static const uint8_t tcc_sizes[TCC_INST_NUM] = TCC_SIZES;
|
2017-06-09 18:29:02 -04:00
|
|
|
|
2018-02-09 03:22:29 -05:00
|
|
|
static uint32_t tcc_periods[TCC_INST_NUM];
|
|
|
|
static uint32_t tc_periods[TC_INST_NUM];
|
|
|
|
|
|
|
|
uint32_t target_tcc_frequencies[TCC_INST_NUM];
|
|
|
|
uint8_t tcc_refcount[TCC_INST_NUM];
|
2017-01-26 21:05:46 -05:00
|
|
|
|
|
|
|
// This bitmask keeps track of which channels of a TCC are currently claimed.
|
2018-02-09 03:22:29 -05:00
|
|
|
#ifdef SAMD21
|
2018-09-11 19:45:22 -04:00
|
|
|
uint8_t tcc_channels[3]; // Set by pwmout_reset() to {0xf0, 0xfc, 0xfc} initially.
|
2018-02-09 03:22:29 -05:00
|
|
|
#endif
|
2020-06-18 15:13:59 -04:00
|
|
|
#ifdef SAM_D5X_E5X
|
2018-09-11 19:45:22 -04:00
|
|
|
uint8_t tcc_channels[5]; // Set by pwmout_reset() to {0xc0, 0xf0, 0xf8, 0xfc, 0xfc} initially.
|
2018-02-09 19:37:18 -05:00
|
|
|
#endif
|
2017-01-26 21:05:46 -05:00
|
|
|
|
2020-03-10 14:12:01 -04:00
|
|
|
|
2020-08-18 16:08:33 -04:00
|
|
|
void common_hal_pwmio_pwmout_never_reset(pwmio_pwmout_obj_t *self) {
|
2020-03-10 14:12:01 -04:00
|
|
|
timer_never_reset(self->timer->index, self->timer->is_tc);
|
2019-01-25 21:31:27 -05:00
|
|
|
|
|
|
|
never_reset_pin_number(self->pin->number);
|
|
|
|
}
|
|
|
|
|
2017-01-26 21:05:46 -05:00
|
|
|
void pwmout_reset(void) {
|
2018-02-09 03:22:29 -05:00
|
|
|
// Reset all timers
|
|
|
|
for (int i = 0; i < TCC_INST_NUM; i++) {
|
2018-02-09 19:37:18 -05:00
|
|
|
target_tcc_frequencies[i] = 0;
|
|
|
|
tcc_refcount[i] = 0;
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
for (int i = 0; i < TCC_INST_NUM; i++) {
|
2021-08-11 12:58:31 -04:00
|
|
|
if (!timer_ok_to_reset(i, false)) {
|
2019-01-25 21:31:27 -05:00
|
|
|
continue;
|
|
|
|
}
|
2021-08-11 15:10:51 -04:00
|
|
|
tcc_channels[i] = 0xff << tcc_cc_num[i];
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
static uint8_t tcc_channel(const pin_timer_t *t) {
|
2018-02-09 03:22:29 -05:00
|
|
|
// For the SAMD51 this hardcodes the use of OTMX == 0x0, the output matrix mapping, which uses
|
|
|
|
// SAMD21-style modulo mapping.
|
2018-02-09 19:37:18 -05:00
|
|
|
return t->wave_output % tcc_cc_num[t->index];
|
|
|
|
}
|
|
|
|
|
2021-11-10 09:42:21 -05:00
|
|
|
STATIC bool channel_ok(const pin_timer_t *t) {
|
2018-02-09 19:37:18 -05:00
|
|
|
uint8_t channel_bit = 1 << tcc_channel(t);
|
|
|
|
return (!t->is_tc && ((tcc_channels[t->index] & channel_bit) == 0)) ||
|
2021-04-30 11:47:37 -04:00
|
|
|
t->is_tc;
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self,
|
|
|
|
const mcu_pin_obj_t *pin,
|
|
|
|
uint16_t duty,
|
|
|
|
uint32_t frequency,
|
|
|
|
bool variable_frequency) {
|
2016-11-03 18:50:59 -04:00
|
|
|
self->pin = pin;
|
2017-01-26 21:05:46 -05:00
|
|
|
self->variable_frequency = variable_frequency;
|
2019-10-22 13:37:36 -04:00
|
|
|
self->duty_cycle = duty;
|
2016-11-03 18:50:59 -04:00
|
|
|
|
2018-02-09 19:37:18 -05:00
|
|
|
if (pin->timer[0].index >= TC_INST_NUM &&
|
|
|
|
pin->timer[1].index >= TCC_INST_NUM
|
2021-04-30 11:47:37 -04:00
|
|
|
#ifdef SAM_D5X_E5X
|
2018-02-09 19:37:18 -05:00
|
|
|
&& pin->timer[2].index >= TCC_INST_NUM
|
2021-04-30 11:47:37 -04:00
|
|
|
#endif
|
2018-02-09 19:37:18 -05:00
|
|
|
) {
|
2019-01-25 21:31:27 -05:00
|
|
|
return PWMOUT_INVALID_PIN;
|
2016-11-03 18:50:59 -04:00
|
|
|
}
|
|
|
|
|
2021-04-20 11:22:21 -04:00
|
|
|
uint32_t system_clock = common_hal_mcu_processor_get_frequency();
|
2021-04-30 11:47:37 -04:00
|
|
|
if (frequency == 0 || frequency > system_clock / 2) {
|
2019-01-25 21:31:27 -05:00
|
|
|
return PWMOUT_INVALID_FREQUENCY;
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
2016-11-03 18:50:59 -04:00
|
|
|
|
2017-01-26 21:05:46 -05:00
|
|
|
// Figure out which timer we are using.
|
2016-11-03 18:50:59 -04:00
|
|
|
|
2018-02-09 19:37:18 -05:00
|
|
|
// First see if a tcc is already going with the frequency we want and our
|
2018-09-11 19:45:22 -04:00
|
|
|
// channel is unused. tc's don't have enough channels to share.
|
2021-04-30 11:47:37 -04:00
|
|
|
const pin_timer_t *timer = NULL;
|
2018-02-09 19:37:18 -05:00
|
|
|
uint8_t mux_position = 0;
|
|
|
|
if (!variable_frequency) {
|
|
|
|
for (uint8_t i = 0; i < TCC_INST_NUM && timer == NULL; i++) {
|
|
|
|
if (target_tcc_frequencies[i] != frequency) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
for (uint8_t j = 0; j < NUM_TIMERS_PER_PIN && timer == NULL; j++) {
|
2021-04-30 11:47:37 -04:00
|
|
|
const pin_timer_t *t = &pin->timer[j];
|
2018-02-09 19:37:18 -05:00
|
|
|
if (t->index != i || t->is_tc || t->index >= TCC_INST_NUM) {
|
|
|
|
continue;
|
|
|
|
}
|
2021-04-30 11:47:37 -04:00
|
|
|
Tcc *tcc = tcc_insts[t->index];
|
2018-02-09 19:37:18 -05:00
|
|
|
if (tcc->CTRLA.bit.ENABLE == 1 && channel_ok(t)) {
|
|
|
|
timer = t;
|
|
|
|
mux_position = j;
|
2018-09-11 19:45:22 -04:00
|
|
|
// Claim channel.
|
|
|
|
tcc_channels[timer->index] |= (1 << tcc_channel(timer));
|
2020-05-21 12:08:26 -04:00
|
|
|
tcc_refcount[timer->index]++;
|
2018-02-09 19:37:18 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// No existing timer has been found, so find a new one to use and set it up.
|
|
|
|
if (timer == NULL) {
|
|
|
|
// By default, with fixed frequency we want to share a TCC because its likely we'll have
|
|
|
|
// other outputs at the same frequency. If the frequency is variable then we'll only have
|
|
|
|
// one output so we start with the TCs to see if they work.
|
|
|
|
int8_t direction = -1;
|
|
|
|
uint8_t start = NUM_TIMERS_PER_PIN - 1;
|
2018-05-14 13:49:45 -04:00
|
|
|
bool found = false;
|
2018-02-09 19:37:18 -05:00
|
|
|
if (variable_frequency) {
|
|
|
|
direction = 1;
|
|
|
|
start = 0;
|
|
|
|
}
|
2018-02-16 13:05:28 -05:00
|
|
|
for (int8_t i = start; i >= 0 && i < NUM_TIMERS_PER_PIN && timer == NULL; i += direction) {
|
2021-04-30 11:47:37 -04:00
|
|
|
const pin_timer_t *t = &pin->timer[i];
|
2018-02-09 19:37:18 -05:00
|
|
|
if ((!t->is_tc && t->index >= TCC_INST_NUM) ||
|
|
|
|
(t->is_tc && t->index >= TC_INST_NUM)) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (t->is_tc) {
|
2018-05-14 13:49:45 -04:00
|
|
|
found = true;
|
2021-04-30 11:47:37 -04:00
|
|
|
Tc *tc = tc_insts[t->index];
|
2018-02-09 19:37:18 -05:00
|
|
|
if (tc->COUNT16.CTRLA.bit.ENABLE == 0 && t->wave_output == 1) {
|
|
|
|
timer = t;
|
|
|
|
mux_position = i;
|
|
|
|
}
|
|
|
|
} else {
|
2021-04-30 11:47:37 -04:00
|
|
|
Tcc *tcc = tcc_insts[t->index];
|
2018-02-09 19:37:18 -05:00
|
|
|
if (tcc->CTRLA.bit.ENABLE == 0 && channel_ok(t)) {
|
|
|
|
timer = t;
|
|
|
|
mux_position = i;
|
|
|
|
}
|
|
|
|
}
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
2018-02-09 19:37:18 -05:00
|
|
|
|
|
|
|
if (timer == NULL) {
|
2018-05-14 13:49:45 -04:00
|
|
|
if (found) {
|
2019-01-25 21:31:27 -05:00
|
|
|
return PWMOUT_ALL_TIMERS_ON_PIN_IN_USE;
|
2018-05-14 13:49:45 -04:00
|
|
|
}
|
2019-01-25 21:31:27 -05:00
|
|
|
return PWMOUT_ALL_TIMERS_IN_USE;
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
2017-06-12 18:37:09 -04:00
|
|
|
|
2017-01-26 21:05:46 -05:00
|
|
|
uint8_t resolution = 0;
|
2018-02-09 19:37:18 -05:00
|
|
|
if (timer->is_tc) {
|
2017-01-26 21:05:46 -05:00
|
|
|
resolution = 16;
|
|
|
|
} else {
|
2017-06-09 18:29:02 -04:00
|
|
|
// TCC resolution varies so look it up.
|
2021-01-09 15:04:23 -05:00
|
|
|
resolution = tcc_sizes[timer->index];
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
// First determine the divisor that gets us the highest resolution.
|
|
|
|
uint32_t top;
|
|
|
|
uint8_t divisor;
|
|
|
|
for (divisor = 0; divisor < 8; divisor++) {
|
|
|
|
top = (system_clock / prescaler[divisor] / frequency) - 1;
|
|
|
|
if (top < (1u << resolution)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2016-12-01 16:47:18 -05:00
|
|
|
|
2019-02-19 21:18:21 -05:00
|
|
|
set_timer_handler(timer->is_tc, timer->index, TC_HANDLER_NO_INTERRUPT);
|
2018-02-13 21:17:20 -05:00
|
|
|
// We use the zeroeth clock on either port to go full speed.
|
2019-02-19 21:18:21 -05:00
|
|
|
turn_on_clocks(timer->is_tc, timer->index, 0);
|
2018-02-09 19:37:18 -05:00
|
|
|
|
|
|
|
if (timer->is_tc) {
|
|
|
|
tc_periods[timer->index] = top;
|
2021-04-30 11:47:37 -04:00
|
|
|
Tc *tc = tc_insts[timer->index];
|
2018-02-09 19:37:18 -05:00
|
|
|
#ifdef SAMD21
|
|
|
|
tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 |
|
2021-04-30 11:47:37 -04:00
|
|
|
TC_CTRLA_PRESCALER(divisor) |
|
|
|
|
TC_CTRLA_WAVEGEN_MPWM;
|
2018-02-09 19:37:18 -05:00
|
|
|
tc->COUNT16.CC[0].reg = top;
|
|
|
|
#endif
|
2020-06-18 15:13:59 -04:00
|
|
|
#ifdef SAM_D5X_E5X
|
2018-02-13 02:41:26 -05:00
|
|
|
|
|
|
|
tc->COUNT16.CTRLA.bit.SWRST = 1;
|
|
|
|
while (tc->COUNT16.CTRLA.bit.SWRST == 1) {
|
|
|
|
}
|
|
|
|
tc_set_enable(tc, false);
|
2018-02-09 19:37:18 -05:00
|
|
|
tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 | TC_CTRLA_PRESCALER(divisor);
|
|
|
|
tc->COUNT16.WAVE.reg = TC_WAVE_WAVEGEN_MPWM;
|
|
|
|
tc->COUNT16.CCBUF[0].reg = top;
|
2018-02-13 17:22:55 -05:00
|
|
|
tc->COUNT16.CCBUF[1].reg = 0;
|
2018-02-09 19:37:18 -05:00
|
|
|
#endif
|
|
|
|
|
|
|
|
tc_set_enable(tc, true);
|
2017-01-26 21:05:46 -05:00
|
|
|
} else {
|
2018-02-09 19:37:18 -05:00
|
|
|
tcc_periods[timer->index] = top;
|
2021-04-30 11:47:37 -04:00
|
|
|
Tcc *tcc = tcc_insts[timer->index];
|
2018-02-13 17:22:55 -05:00
|
|
|
tcc_set_enable(tcc, false);
|
2018-02-09 19:37:18 -05:00
|
|
|
tcc->CTRLA.bit.PRESCALER = divisor;
|
|
|
|
tcc->PER.bit.PER = top;
|
|
|
|
tcc->WAVE.bit.WAVEGEN = TCC_WAVE_WAVEGEN_NPWM_Val;
|
|
|
|
tcc_set_enable(tcc, true);
|
|
|
|
target_tcc_frequencies[timer->index] = frequency;
|
|
|
|
tcc_refcount[timer->index]++;
|
|
|
|
if (variable_frequency) {
|
|
|
|
// We're changing frequency so claim all of the channels.
|
|
|
|
tcc_channels[timer->index] = 0xff;
|
|
|
|
} else {
|
|
|
|
tcc_channels[timer->index] |= (1 << tcc_channel(timer));
|
|
|
|
}
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
2016-11-03 18:50:59 -04:00
|
|
|
}
|
2017-01-26 21:05:46 -05:00
|
|
|
|
2018-02-09 19:37:18 -05:00
|
|
|
self->timer = timer;
|
2017-01-26 21:05:46 -05:00
|
|
|
|
2018-07-31 17:01:01 -04:00
|
|
|
gpio_set_pin_function(pin->number, GPIO_PIN_FUNCTION_E + mux_position);
|
2017-01-26 21:05:46 -05:00
|
|
|
|
2020-08-18 16:08:33 -04:00
|
|
|
common_hal_pwmio_pwmout_set_duty_cycle(self, duty);
|
2019-01-25 21:31:27 -05:00
|
|
|
return PWMOUT_OK;
|
2016-11-03 18:50:59 -04:00
|
|
|
}
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t *self) {
|
2020-02-28 23:32:24 -05:00
|
|
|
return self->pin == NULL;
|
2017-10-02 20:49:40 -04:00
|
|
|
}
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t *self) {
|
2020-08-18 16:08:33 -04:00
|
|
|
if (common_hal_pwmio_pwmout_deinited(self)) {
|
2017-10-02 20:49:40 -04:00
|
|
|
return;
|
|
|
|
}
|
2023-02-17 19:13:18 -05:00
|
|
|
timer_reset_ok(self->timer->index, self->timer->is_tc);
|
2021-04-30 11:47:37 -04:00
|
|
|
const pin_timer_t *t = self->timer;
|
2018-02-09 19:37:18 -05:00
|
|
|
if (t->is_tc) {
|
2021-04-30 11:47:37 -04:00
|
|
|
Tc *tc = tc_insts[t->index];
|
2018-02-09 19:37:18 -05:00
|
|
|
tc_set_enable(tc, false);
|
|
|
|
tc->COUNT16.CTRLA.bit.SWRST = true;
|
2018-02-13 19:44:04 -05:00
|
|
|
tc_wait_for_sync(tc);
|
2018-02-09 19:37:18 -05:00
|
|
|
} else {
|
|
|
|
tcc_refcount[t->index]--;
|
|
|
|
tcc_channels[t->index] &= ~(1 << tcc_channel(t));
|
|
|
|
if (tcc_refcount[t->index] == 0) {
|
|
|
|
target_tcc_frequencies[t->index] = 0;
|
2021-04-30 11:47:37 -04:00
|
|
|
Tcc *tcc = tcc_insts[t->index];
|
2018-02-09 19:37:18 -05:00
|
|
|
tcc_set_enable(tcc, false);
|
|
|
|
tcc->CTRLA.bit.SWRST = true;
|
|
|
|
while (tcc->SYNCBUSY.bit.SWRST != 0) {
|
|
|
|
/* Wait for sync */
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
}
|
2016-11-03 18:50:59 -04:00
|
|
|
}
|
2018-08-31 17:46:03 -04:00
|
|
|
reset_pin_number(self->pin->number);
|
2020-02-28 23:32:24 -05:00
|
|
|
self->pin = NULL;
|
2016-11-03 18:50:59 -04:00
|
|
|
}
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
extern void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t duty) {
|
2019-10-25 13:50:27 -04:00
|
|
|
// Store the unadjusted duty cycle. It turns out the the process of adjusting and calculating
|
2019-10-22 13:37:36 -04:00
|
|
|
// the duty cycle here and reading it back is lossy - the value will decay over time.
|
2019-10-25 13:50:27 -04:00
|
|
|
// Track it here so that if frequency is changed we can use this value to recalculate the
|
2019-10-22 13:37:36 -04:00
|
|
|
// proper duty cycle.
|
|
|
|
// See https://github.com/adafruit/circuitpython/issues/2086 for more details
|
|
|
|
self->duty_cycle = duty;
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
const pin_timer_t *t = self->timer;
|
2017-01-26 21:05:46 -05:00
|
|
|
if (t->is_tc) {
|
2018-02-09 19:37:18 -05:00
|
|
|
uint16_t adjusted_duty = tc_periods[t->index] * duty / 0xffff;
|
|
|
|
#ifdef SAMD21
|
|
|
|
tc_insts[t->index]->COUNT16.CC[t->wave_output].reg = adjusted_duty;
|
|
|
|
#endif
|
2020-06-18 15:13:59 -04:00
|
|
|
#ifdef SAM_D5X_E5X
|
2021-04-30 11:47:37 -04:00
|
|
|
Tc *tc = tc_insts[t->index];
|
|
|
|
while (tc->COUNT16.SYNCBUSY.bit.CC1 != 0) {
|
|
|
|
}
|
2018-02-13 17:22:55 -05:00
|
|
|
tc->COUNT16.CCBUF[1].reg = adjusted_duty;
|
2018-02-09 19:37:18 -05:00
|
|
|
#endif
|
2016-11-03 18:50:59 -04:00
|
|
|
} else {
|
2021-04-30 11:47:37 -04:00
|
|
|
uint32_t adjusted_duty = ((uint64_t)tcc_periods[t->index]) * duty / 0xffff;
|
2018-02-09 19:37:18 -05:00
|
|
|
uint8_t channel = tcc_channel(t);
|
2021-04-30 11:47:37 -04:00
|
|
|
Tcc *tcc = tcc_insts[t->index];
|
2019-02-28 19:53:35 -05:00
|
|
|
|
|
|
|
// Write into the CC buffer register, which will be transferred to the
|
|
|
|
// CC register on an UPDATE (when period is finished).
|
|
|
|
// Do clock domain syncing as necessary.
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
while (tcc->SYNCBUSY.reg != 0) {
|
|
|
|
}
|
2019-02-28 19:53:35 -05:00
|
|
|
|
|
|
|
// Lock out double-buffering while updating the CCB value.
|
|
|
|
tcc->CTRLBSET.bit.LUPD = 1;
|
2018-02-13 19:44:04 -05:00
|
|
|
#ifdef SAMD21
|
|
|
|
tcc->CCB[channel].reg = adjusted_duty;
|
|
|
|
#endif
|
2020-06-18 15:13:59 -04:00
|
|
|
#ifdef SAM_D5X_E5X
|
2018-02-13 17:22:55 -05:00
|
|
|
tcc->CCBUF[channel].reg = adjusted_duty;
|
2018-02-13 19:44:04 -05:00
|
|
|
#endif
|
2019-02-28 19:53:35 -05:00
|
|
|
tcc->CTRLBCLR.bit.LUPD = 1;
|
2016-11-03 18:50:59 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) {
|
|
|
|
const pin_timer_t *t = self->timer;
|
2017-01-26 21:05:46 -05:00
|
|
|
if (t->is_tc) {
|
2021-04-30 11:47:37 -04:00
|
|
|
Tc *tc = tc_insts[t->index];
|
2018-02-13 19:44:04 -05:00
|
|
|
tc_wait_for_sync(tc);
|
2018-02-09 19:37:18 -05:00
|
|
|
uint16_t cv = tc->COUNT16.CC[t->wave_output].reg;
|
|
|
|
return cv * 0xffff / tc_periods[t->index];
|
2017-01-26 21:05:46 -05:00
|
|
|
} else {
|
2021-04-30 11:47:37 -04:00
|
|
|
Tcc *tcc = tcc_insts[t->index];
|
2018-02-09 19:37:18 -05:00
|
|
|
uint8_t channel = tcc_channel(t);
|
2017-01-26 21:05:46 -05:00
|
|
|
uint32_t cv = 0;
|
2019-02-28 19:53:35 -05:00
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
while (tcc->SYNCBUSY.bit.CTRLB) {
|
|
|
|
}
|
2019-02-28 19:53:35 -05:00
|
|
|
|
2018-02-09 19:37:18 -05:00
|
|
|
#ifdef SAMD21
|
2019-02-28 19:53:35 -05:00
|
|
|
// If CCBV (CCB valid) is set, the CCB value hasn't yet been copied
|
|
|
|
// to the CC value.
|
2018-02-09 19:37:18 -05:00
|
|
|
if ((tcc->STATUS.vec.CCBV & (1 << channel)) != 0) {
|
|
|
|
cv = tcc->CCB[channel].reg;
|
|
|
|
} else {
|
|
|
|
cv = tcc->CC[channel].reg;
|
|
|
|
}
|
|
|
|
#endif
|
2020-06-18 15:13:59 -04:00
|
|
|
#ifdef SAM_D5X_E5X
|
2018-02-09 19:37:18 -05:00
|
|
|
if ((tcc->STATUS.vec.CCBUFV & (1 << channel)) != 0) {
|
|
|
|
cv = tcc->CCBUF[channel].reg;
|
2017-01-26 21:05:46 -05:00
|
|
|
} else {
|
2018-02-09 19:37:18 -05:00
|
|
|
cv = tcc->CC[channel].reg;
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
2018-02-09 19:37:18 -05:00
|
|
|
#endif
|
2017-06-06 16:16:34 -04:00
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
uint32_t duty_cycle = ((uint64_t)cv) * 0xffff / tcc_periods[t->index];
|
2017-06-06 16:16:34 -04:00
|
|
|
|
|
|
|
return duty_cycle;
|
2016-11-03 18:50:59 -04:00
|
|
|
}
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self,
|
|
|
|
uint32_t frequency) {
|
2021-04-20 11:22:21 -04:00
|
|
|
uint32_t system_clock = common_hal_mcu_processor_get_frequency();
|
2021-04-30 11:47:37 -04:00
|
|
|
if (frequency == 0 || frequency > system_clock / 2) {
|
2022-05-13 15:33:43 -04:00
|
|
|
mp_arg_error_invalid(MP_QSTR_frequency);
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
2021-04-30 11:47:37 -04:00
|
|
|
const pin_timer_t *t = self->timer;
|
2017-01-26 21:05:46 -05:00
|
|
|
uint8_t resolution;
|
|
|
|
if (t->is_tc) {
|
|
|
|
resolution = 16;
|
|
|
|
} else {
|
2021-01-09 15:04:23 -05:00
|
|
|
// TCC resolution varies so look it up.
|
|
|
|
resolution = tcc_sizes[t->index];
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
uint32_t new_top;
|
|
|
|
uint8_t new_divisor;
|
|
|
|
for (new_divisor = 0; new_divisor < 8; new_divisor++) {
|
|
|
|
new_top = (system_clock / prescaler[new_divisor] / frequency) - 1;
|
|
|
|
if (new_top < (1u << resolution)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (t->is_tc) {
|
2021-04-30 11:47:37 -04:00
|
|
|
Tc *tc = tc_insts[t->index];
|
2018-02-09 19:37:18 -05:00
|
|
|
uint8_t old_divisor = tc->COUNT16.CTRLA.bit.PRESCALER;
|
|
|
|
if (new_divisor != old_divisor) {
|
2018-02-13 19:44:04 -05:00
|
|
|
tc_set_enable(tc, false);
|
2018-02-09 19:37:18 -05:00
|
|
|
tc->COUNT16.CTRLA.bit.PRESCALER = new_divisor;
|
2018-02-13 19:44:04 -05:00
|
|
|
tc_set_enable(tc, true);
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
2018-02-09 19:37:18 -05:00
|
|
|
tc_periods[t->index] = new_top;
|
|
|
|
#ifdef SAMD21
|
|
|
|
tc->COUNT16.CC[0].reg = new_top;
|
|
|
|
#endif
|
2020-06-18 15:13:59 -04:00
|
|
|
#ifdef SAM_D5X_E5X
|
2021-04-30 11:47:37 -04:00
|
|
|
while (tc->COUNT16.SYNCBUSY.reg != 0) {
|
|
|
|
}
|
2018-02-09 19:37:18 -05:00
|
|
|
tc->COUNT16.CCBUF[0].reg = new_top;
|
|
|
|
#endif
|
2017-01-26 21:05:46 -05:00
|
|
|
} else {
|
2021-04-30 11:47:37 -04:00
|
|
|
Tcc *tcc = tcc_insts[t->index];
|
2018-02-09 19:37:18 -05:00
|
|
|
uint8_t old_divisor = tcc->CTRLA.bit.PRESCALER;
|
|
|
|
if (new_divisor != old_divisor) {
|
2018-02-13 19:44:04 -05:00
|
|
|
tcc_set_enable(tcc, false);
|
2018-02-09 19:37:18 -05:00
|
|
|
tcc->CTRLA.bit.PRESCALER = new_divisor;
|
2018-02-13 19:44:04 -05:00
|
|
|
tcc_set_enable(tcc, true);
|
2018-02-09 19:37:18 -05:00
|
|
|
}
|
2021-04-30 11:47:37 -04:00
|
|
|
while (tcc->SYNCBUSY.reg != 0) {
|
|
|
|
}
|
2018-02-09 19:37:18 -05:00
|
|
|
tcc_periods[t->index] = new_top;
|
2018-02-13 19:44:04 -05:00
|
|
|
#ifdef SAMD21
|
|
|
|
tcc->PERB.bit.PERB = new_top;
|
|
|
|
#endif
|
2020-06-18 15:13:59 -04:00
|
|
|
#ifdef SAM_D5X_E5X
|
2018-02-09 19:37:18 -05:00
|
|
|
tcc->PERBUF.bit.PERBUF = new_top;
|
2018-02-13 19:44:04 -05:00
|
|
|
#endif
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
|
2020-08-18 16:08:33 -04:00
|
|
|
common_hal_pwmio_pwmout_set_duty_cycle(self, self->duty_cycle);
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) {
|
2018-02-09 19:37:18 -05:00
|
|
|
uint32_t system_clock = common_hal_mcu_processor_get_frequency();
|
2021-04-30 11:47:37 -04:00
|
|
|
const pin_timer_t *t = self->timer;
|
2017-01-26 21:05:46 -05:00
|
|
|
uint8_t divisor;
|
2018-02-09 19:37:18 -05:00
|
|
|
uint32_t top;
|
2017-01-26 21:05:46 -05:00
|
|
|
if (t->is_tc) {
|
2018-02-09 19:37:18 -05:00
|
|
|
divisor = tc_insts[t->index]->COUNT16.CTRLA.bit.PRESCALER;
|
|
|
|
top = tc_periods[t->index];
|
2017-01-26 21:05:46 -05:00
|
|
|
} else {
|
2018-02-09 19:37:18 -05:00
|
|
|
divisor = tcc_insts[t->index]->CTRLA.bit.PRESCALER;
|
|
|
|
top = tcc_periods[t->index];
|
2017-01-26 21:05:46 -05:00
|
|
|
}
|
|
|
|
return (system_clock / prescaler[divisor]) / (top + 1);
|
|
|
|
}
|
|
|
|
|
2021-04-30 11:47:37 -04:00
|
|
|
bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) {
|
2017-01-26 21:05:46 -05:00
|
|
|
return self->variable_frequency;
|
2016-11-03 18:50:59 -04:00
|
|
|
}
|
2021-07-21 19:27:09 -04:00
|
|
|
|
|
|
|
const mcu_pin_obj_t *common_hal_pwmio_pwmout_get_pin(pwmio_pwmout_obj_t *self) {
|
|
|
|
return self->pin;
|
|
|
|
}
|