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codeformat: Fix filename matching 

In #4683, tannewt noticed that uncrustify was not running on some
file in common-hal.

I investigated and found that it was not being run on a bunch of paths.

Rather than make incremental changes, I rewrote list_files to work
bsaed on regular expressions; these regular expressions are created from
the same git-style glob patterns.

I spot-checked some specific filenames after this change, and all looks good:

```
$ python3 tools/codeformat.py -v --dry-run tests/basics/int_small.py ports/raspberrypi/common-hal/pulseio/PulseIn.c extmod/virtpin.c tests/thread/thread_exit1.py  ports/raspberrypi/background.h extmod/re1.5/recursiveloop.c
tools/codeformat.py -v --dry-run tests/basics/int_small.py ports/raspberrypi/common-hal/pulseio/PulseIn.c extmod/virtpin.c tests/thread/thread_exit1.py ports/raspberrypi/background.h extmod/re1.5/recursiveloop.c
uncrustify -c /home/jepler/src/circuitpython/tools/uncrustify.cfg -lC --no-backup extmod/virtpin.c ports/raspberrypi/background.h ports/raspberrypi/common-hal/pulseio/PulseIn.c
black --fast --line-length=99 -v tests/thread/thread_exit1.py
```
recursiveloop and int_small are excluded, while PulseIn, virtpin,
and background are included.

Testing running from a subdirectory (not _specifically_ supported though):
```
(cd ports && python3 ../tools/codeformat.py -v --dry-run raspberrypi/common-hal/pulseio/PulseIn.c ../extmod/virtpin.c)
../tools/codeformat.py -v --dry-run raspberrypi/common-hal/pulseio/PulseIn.c ../extmod/virtpin.c
uncrustify -c /home/jepler/src/circuitpython/tools/uncrustify.cfg -lC --no-backup ../extmod/virtpin.c raspberrypi/common-hal/pulseio/PulseIn.
```

As a side-effect, a bunch more files are re-formatted now. :-P
This commit is contained in:
Jeff Epler 2021-04-30 10:47:37 -05:00
parent 353e55d710
commit e95e921ca1
76 changed files with 2179 additions and 2152 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
devices/ble_hci/common-hal/_bleio/PacketBuffer.c
View File

@ -245,8 +245,8 @@ mp_int_t common_hal_bleio_packet_buffer_get_outgoing_packet_length(bleio_packet_
bleio_connection_internal_t *connection = bleio_conn_handle_to_connection(self->conn_handle);
if (connection) {
return MIN(MIN(common_hal_bleio_connection_get_max_packet_length(connection),
self->max_packet_size),
self->characteristic->max_length);
self->max_packet_size),
self->characteristic->max_length);
}
}
// There's no current connection, so we don't know the MTU, and

2
ports/atmel-samd/boards/adafruit_slide_trinkey_m0/pins.c
View File

@ -1,7 +1,7 @@
#include "shared-bindings/board/__init__.h"
STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
//{ MP_ROM_QSTR(MP_QSTR_TOUCH), MP_ROM_PTR(&pin_PA07) },
// { MP_ROM_QSTR(MP_QSTR_TOUCH), MP_ROM_PTR(&pin_PA07) },
{ MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_PA06) },
{ MP_ROM_QSTR(MP_QSTR_POTENTIOMETER), MP_ROM_PTR(&pin_PA07) },
};

110
ports/atmel-samd/common-hal/audioio/AudioOut.c
View File

@ -57,7 +57,7 @@
#ifdef SAMD21
static void ramp_value(uint16_t start, uint16_t end) {
start = DAC->DATA.reg;
int32_t diff = (int32_t) end - start;
int32_t diff = (int32_t)end - start;
int32_t step = 49;
int32_t steps = diff / step;
if (diff < 0) {
@ -76,7 +76,7 @@ static void ramp_value(uint16_t start, uint16_t end) {
#ifdef SAM_D5X_E5X
static void ramp_value(uint16_t start, uint16_t end) {
int32_t diff = (int32_t) end - start;
int32_t diff = (int32_t)end - start;
int32_t step = 49;
int32_t steps = diff / step;
if (diff < 0) {
@ -102,10 +102,12 @@ void audioout_reset(void) {
return;
#endif
#ifdef SAMD21
while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {}
while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {
}
#endif
#ifdef SAM_D5X_E5X
while (DAC->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) {}
while (DAC->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) {
}
#endif
if (DAC->CTRLA.bit.ENABLE) {
ramp_value(0x8000, 0);
@ -116,8 +118,8 @@ void audioout_reset(void) {
}
// Caller validates that pins are free.
void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
const mcu_pin_obj_t* left_channel, const mcu_pin_obj_t* right_channel, uint16_t quiescent_value) {
void common_hal_audioio_audioout_construct(audioio_audioout_obj_t *self,
const mcu_pin_obj_t *left_channel, const mcu_pin_obj_t *right_channel, uint16_t quiescent_value) {
#ifdef SAM_D5X_E5X
bool dac_clock_enabled = hri_mclk_get_APBDMASK_DAC_bit(MCLK);
#endif
@ -174,7 +176,8 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
_gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC);
DAC->CTRLA.bit.SWRST = 1;
while (DAC->CTRLA.bit.SWRST == 1) {}
while (DAC->CTRLA.bit.SWRST == 1) {
}
// Make sure there are no outstanding access errors. (Reading DATA can cause this.)
#ifdef SAM_D5X_E5X
PAC->INTFLAGD.reg = PAC_INTFLAGD_DAC;
@ -191,15 +194,15 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI;
// We disable the voltage pump because we always run at 3.3v.
DAC->CTRLB.reg = DAC_CTRLB_REFSEL_AVCC |
DAC_CTRLB_LEFTADJ |
DAC_CTRLB_EOEN |
DAC_CTRLB_VPD;
DAC_CTRLB_LEFTADJ |
DAC_CTRLB_EOEN |
DAC_CTRLB_VPD;
#endif
#ifdef SAM_D5X_E5X
DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI0;
DAC->DACCTRL[0].reg = DAC_DACCTRL_CCTRL_CC12M |
DAC_DACCTRL_ENABLE |
DAC_DACCTRL_LEFTADJ;
DAC_DACCTRL_ENABLE |
DAC_DACCTRL_LEFTADJ;
DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU;
#endif
}
@ -207,8 +210,8 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
if (channel1_enabled) {
DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI1;
DAC->DACCTRL[1].reg = DAC_DACCTRL_CCTRL_CC12M |
DAC_DACCTRL_ENABLE |
DAC_DACCTRL_LEFTADJ;
DAC_DACCTRL_ENABLE |
DAC_DACCTRL_LEFTADJ;
DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU;
}
#endif
@ -216,12 +219,16 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
// Re-enable the DAC
DAC->CTRLA.bit.ENABLE = 1;
#ifdef SAMD21
while (DAC->STATUS.bit.SYNCBUSY == 1) {}
while (DAC->STATUS.bit.SYNCBUSY == 1) {
}
#endif
#ifdef SAM_D5X_E5X
while (DAC->SYNCBUSY.bit.ENABLE == 1) {}
while (channel0_enabled && DAC->STATUS.bit.READY0 == 0) {}
while (channel1_enabled && DAC->STATUS.bit.READY1 == 0) {}
while (DAC->SYNCBUSY.bit.ENABLE == 1) {
}
while (channel0_enabled && DAC->STATUS.bit.READY0 == 0) {
}
while (channel1_enabled && DAC->STATUS.bit.READY1 == 0) {
}
#endif
// Use a timer to coordinate when DAC conversions occur.
@ -302,11 +309,11 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
// Leave the DMA setup to playback.
}
bool common_hal_audioio_audioout_deinited(audioio_audioout_obj_t* self) {
bool common_hal_audioio_audioout_deinited(audioio_audioout_obj_t *self) {
return self->left_channel == NULL;
}
void common_hal_audioio_audioout_deinit(audioio_audioout_obj_t* self) {
void common_hal_audioio_audioout_deinit(audioio_audioout_obj_t *self) {
if (common_hal_audioio_audioout_deinited(self)) {
return;
}
@ -320,10 +327,12 @@ void common_hal_audioio_audioout_deinit(audioio_audioout_obj_t* self) {
DAC->CTRLA.bit.ENABLE = 0;
#ifdef SAMD21
while (DAC->STATUS.bit.SYNCBUSY == 1) {}
while (DAC->STATUS.bit.SYNCBUSY == 1) {
}
#endif
#ifdef SAM_D5X_E5X
while (DAC->SYNCBUSY.bit.ENABLE == 1) {}
while (DAC->SYNCBUSY.bit.ENABLE == 1) {
}
#endif
disable_event_channel(self->tc_to_dac_event_channel);
@ -338,7 +347,7 @@ void common_hal_audioio_audioout_deinit(audioio_audioout_obj_t* self) {
#endif
}
static void set_timer_frequency(Tc* timer, uint32_t frequency) {
static void set_timer_frequency(Tc *timer, uint32_t frequency) {
uint32_t system_clock = 48000000;
uint32_t new_top;
uint8_t new_divisor;
@ -359,8 +368,8 @@ static void set_timer_frequency(Tc* timer, uint32_t frequency) {
tc_wait_for_sync(timer);
}
void common_hal_audioio_audioout_play(audioio_audioout_obj_t* self,
mp_obj_t sample, bool loop) {
void common_hal_audioio_audioout_play(audioio_audioout_obj_t *self,
mp_obj_t sample, bool loop) {
if (common_hal_audioio_audioout_get_playing(self)) {
common_hal_audioio_audioout_stop(self);
}
@ -377,40 +386,40 @@ void common_hal_audioio_audioout_play(audioio_audioout_obj_t* self,
}
#ifdef SAMD21
result = audio_dma_setup_playback(&self->left_dma, sample, loop, true, 0,
false /* output unsigned */,
(uint32_t) &DAC->DATABUF.reg,
DAC_DMAC_ID_EMPTY);
false /* output unsigned */,
(uint32_t)&DAC->DATABUF.reg,
DAC_DMAC_ID_EMPTY);
#endif
#ifdef SAM_D5X_E5X
uint32_t left_channel_reg = (uint32_t) &DAC->DATABUF[0].reg;
uint32_t left_channel_reg = (uint32_t)&DAC->DATABUF[0].reg;
uint8_t tc_trig_id = TC0_DMAC_ID_OVF + 3 * self->tc_index;
uint8_t left_channel_trigger = tc_trig_id;
uint32_t right_channel_reg = 0;
uint8_t right_channel_trigger = tc_trig_id;
if (self->left_channel == &pin_PA05) {
left_channel_reg = (uint32_t) &DAC->DATABUF[1].reg;
left_channel_reg = (uint32_t)&DAC->DATABUF[1].reg;
} else if (self->right_channel == &pin_PA05) {
right_channel_reg = (uint32_t) &DAC->DATABUF[1].reg;
right_channel_reg = (uint32_t)&DAC->DATABUF[1].reg;
}
if (self->right_channel == &pin_PA02) {
right_channel_reg = (uint32_t) &DAC->DATABUF[0].reg;
right_channel_reg = (uint32_t)&DAC->DATABUF[0].reg;
}
if(right_channel_reg == left_channel_reg + 2 && audiosample_bits_per_sample(sample) == 16) {
if (right_channel_reg == left_channel_reg + 2 && audiosample_bits_per_sample(sample) == 16) {
result = audio_dma_setup_playback(&self->left_dma, sample, loop, false, 0,
false /* output unsigned */,
left_channel_reg,
left_channel_trigger);
false /* output unsigned */,
left_channel_reg,
left_channel_trigger);
} else {
result = audio_dma_setup_playback(&self->left_dma, sample, loop, true, 0,
false /* output unsigned */,
left_channel_reg,
left_channel_trigger);
false /* output unsigned */,
left_channel_reg,
left_channel_trigger);
if (right_channel_reg != 0 && result == AUDIO_DMA_OK) {
result = audio_dma_setup_playback(&self->right_dma, sample, loop, true, 1,
false /* output unsigned */,
right_channel_reg,
right_channel_trigger);
false /* output unsigned */,
right_channel_reg,
right_channel_trigger);
}
}
#endif
@ -425,21 +434,22 @@ void common_hal_audioio_audioout_play(audioio_audioout_obj_t* self,
mp_raise_RuntimeError(translate("Unable to allocate buffers for signed conversion"));
}
}
Tc* timer = tc_insts[self->tc_index];
Tc *timer = tc_insts[self->tc_index];
set_timer_frequency(timer, audiosample_sample_rate(sample));
timer->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
while (timer->COUNT16.STATUS.bit.STOP == 1) {}
while (timer->COUNT16.STATUS.bit.STOP == 1) {
}
self->playing = true;
}
void common_hal_audioio_audioout_pause(audioio_audioout_obj_t* self) {
void common_hal_audioio_audioout_pause(audioio_audioout_obj_t *self) {
audio_dma_pause(&self->left_dma);
#ifdef SAM_D5X_E5X
audio_dma_pause(&self->right_dma);
#endif
}
void common_hal_audioio_audioout_resume(audioio_audioout_obj_t* self) {
void common_hal_audioio_audioout_resume(audioio_audioout_obj_t *self) {
// Clear any overrun/underrun errors
#ifdef SAMD21
DAC->INTFLAG.reg = DAC_INTFLAG_UNDERRUN;
@ -454,12 +464,12 @@ void common_hal_audioio_audioout_resume(audioio_audioout_obj_t* self) {
#endif
}
bool common_hal_audioio_audioout_get_paused(audioio_audioout_obj_t* self) {
bool common_hal_audioio_audioout_get_paused(audioio_audioout_obj_t *self) {
return audio_dma_get_paused(&self->left_dma);
}
void common_hal_audioio_audioout_stop(audioio_audioout_obj_t* self) {
Tc* timer = tc_insts[self->tc_index];
void common_hal_audioio_audioout_stop(audioio_audioout_obj_t *self) {
Tc *timer = tc_insts[self->tc_index];
timer->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;
audio_dma_stop(&self->left_dma);
#ifdef SAM_D5X_E5X
@ -470,7 +480,7 @@ void common_hal_audioio_audioout_stop(audioio_audioout_obj_t* self) {
ramp_value(self->quiescent_value, self->quiescent_value);
}
bool common_hal_audioio_audioout_get_playing(audioio_audioout_obj_t* self) {
bool common_hal_audioio_audioout_get_playing(audioio_audioout_obj_t *self) {
bool now_playing = audio_dma_get_playing(&self->left_dma);
if (self->playing && !now_playing) {
common_hal_audioio_audioout_stop(self);

38
ports/atmel-samd/common-hal/busio/I2C.c
View File

@ -41,8 +41,8 @@
// Number of times to try to send packet if failed.
#define ATTEMPTS 2
Sercom *samd_i2c_get_sercom(const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda,
uint8_t *sercom_index, uint32_t *sda_pinmux, uint32_t *scl_pinmux) {
Sercom *samd_i2c_get_sercom(const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda,
uint8_t *sercom_index, uint32_t *sda_pinmux, uint32_t *scl_pinmux) {
*sda_pinmux = 0;
*scl_pinmux = 0;
for (int i = 0; i < NUM_SERCOMS_PER_PIN; i++) {
@ -50,7 +50,7 @@ Sercom *samd_i2c_get_sercom(const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda,
if (*sercom_index >= SERCOM_INST_NUM) {
continue;
}
Sercom* potential_sercom = sercom_insts[*sercom_index];
Sercom *potential_sercom = sercom_insts[*sercom_index];
if (potential_sercom->I2CM.CTRLA.bit.ENABLE != 0 ||
sda->sercom[i].pad != 0) {
continue;
@ -68,15 +68,15 @@ Sercom *samd_i2c_get_sercom(const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda,
}
void common_hal_busio_i2c_construct(busio_i2c_obj_t *self,
const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda, uint32_t frequency, uint32_t timeout) {
const mcu_pin_obj_t *scl, const mcu_pin_obj_t *sda, uint32_t frequency, uint32_t timeout) {
uint8_t sercom_index;
uint32_t sda_pinmux, scl_pinmux;
Sercom* sercom = samd_i2c_get_sercom(scl, sda, &sercom_index, &sda_pinmux, &scl_pinmux);
Sercom *sercom = samd_i2c_get_sercom(scl, sda, &sercom_index, &sda_pinmux, &scl_pinmux);
if (sercom == NULL) {
mp_raise_ValueError(translate("Invalid pins"));
}
#if CIRCUITPY_REQUIRE_I2C_PULLUPS
#if CIRCUITPY_REQUIRE_I2C_PULLUPS
// Test that the pins are in a high state. (Hopefully indicating they are pulled up.)
gpio_set_pin_function(sda->number, GPIO_PIN_FUNCTION_OFF);
gpio_set_pin_function(scl->number, GPIO_PIN_FUNCTION_OFF);
@ -99,7 +99,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self,
reset_pin_number(scl->number);
mp_raise_RuntimeError(translate("No pull up found on SDA or SCL; check your wiring"));
}
#endif
#endif
gpio_set_pin_function(sda->number, sda_pinmux);
gpio_set_pin_function(scl->number, scl_pinmux);
@ -164,10 +164,10 @@ bool common_hal_busio_i2c_probe(busio_i2c_obj_t *self, uint8_t addr) {
bool common_hal_busio_i2c_try_lock(busio_i2c_obj_t *self) {
bool grabbed_lock = false;
CRITICAL_SECTION_ENTER()
if (!self->has_lock) {
grabbed_lock = true;
self->has_lock = true;
}
if (!self->has_lock) {
grabbed_lock = true;
self->has_lock = true;
}
CRITICAL_SECTION_LEAVE();
return grabbed_lock;
}
@ -181,7 +181,7 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) {
}
uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr,
const uint8_t *data, size_t len, bool transmit_stop_bit) {
const uint8_t *data, size_t len, bool transmit_stop_bit) {
uint16_t attempts = ATTEMPTS;
int32_t status;
@ -189,8 +189,8 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr,
struct _i2c_m_msg msg;
msg.addr = addr;
msg.len = len;
msg.flags = transmit_stop_bit ? I2C_M_STOP : 0;
msg.buffer = (uint8_t *) data;
msg.flags = transmit_stop_bit ? I2C_M_STOP : 0;
msg.buffer = (uint8_t *)data;
status = _i2c_m_sync_transfer(&self->i2c_desc.device, &msg);
// Give up after ATTEMPTS tries.
@ -207,16 +207,16 @@ uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr,
}
uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr,
uint8_t *data, size_t len) {
uint8_t *data, size_t len) {
uint16_t attempts = ATTEMPTS;
int32_t status;
do {
struct _i2c_m_msg msg;
msg.addr = addr;
msg.len = len;
msg.flags = I2C_M_STOP | I2C_M_RD;
msg.buffer = data;
msg.addr = addr;
msg.len = len;
msg.flags = I2C_M_STOP | I2C_M_RD;
msg.buffer = data;
status = _i2c_m_sync_transfer(&self->i2c_desc.device, &msg);
// Give up after ATTEMPTS tries.

54
ports/atmel-samd/common-hal/busio/SPI.c
View File

@ -43,7 +43,7 @@
bool never_reset_sercoms[SERCOM_INST_NUM];
void never_reset_sercom(Sercom* sercom) {
void never_reset_sercom(Sercom *sercom) {
// Reset all SERCOMs except the ones being used by on-board devices.
Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
for (int i = 0; i < SERCOM_INST_NUM; i++) {
@ -54,7 +54,7 @@ void never_reset_sercom(Sercom* sercom) {
}
}
void allow_reset_sercom(Sercom* sercom) {
void allow_reset_sercom(Sercom *sercom) {
// Reset all SERCOMs except the ones being used by on-board devices.
Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
for (int i = 0; i < SERCOM_INST_NUM; i++) {
@ -72,11 +72,11 @@ void reset_sercoms(void) {
if (never_reset_sercoms[i]) {
continue;
}
#ifdef MICROPY_HW_APA102_SERCOM
#ifdef MICROPY_HW_APA102_SERCOM
if (sercom_instances[i] == MICROPY_HW_APA102_SERCOM) {
continue;
}
#endif
#endif
// SWRST is same for all modes of SERCOMs.
sercom_instances[i]->SPI.CTRLA.bit.SWRST = 1;
}
@ -84,9 +84,9 @@ void reset_sercoms(void) {
void common_hal_busio_spi_construct(busio_spi_obj_t *self,
const mcu_pin_obj_t * clock, const mcu_pin_obj_t * mosi,
const mcu_pin_obj_t * miso) {
Sercom* sercom = NULL;
const mcu_pin_obj_t *clock, const mcu_pin_obj_t *mosi,
const mcu_pin_obj_t *miso) {
Sercom *sercom = NULL;
uint8_t sercom_index;
uint32_t clock_pinmux = 0;
bool mosi_none = mosi == NULL;
@ -121,16 +121,16 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
if (sercom_index >= SERCOM_INST_NUM) {
continue;
}
Sercom* potential_sercom = sercom_insts[sercom_index];
Sercom *potential_sercom = sercom_insts[sercom_index];
if (
#if defined(MICROPY_HW_APA102_SCK) && defined(MICROPY_HW_APA102_MOSI) && !CIRCUITPY_BITBANG_APA102
#if defined(MICROPY_HW_APA102_SCK) && defined(MICROPY_HW_APA102_MOSI) && !CIRCUITPY_BITBANG_APA102
(potential_sercom->SPI.CTRLA.bit.ENABLE != 0 &&
potential_sercom != status_apa102.spi_desc.dev.prvt &&
!apa102_sck_in_use)
#else
#else
potential_sercom->SPI.CTRLA.bit.ENABLE != 0
#endif
) {
#endif
) {
continue;
}
clock_pinmux = PINMUX(clock->number, (i == 0) ? MUX_C : MUX_D);
@ -172,7 +172,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self,
if (sercom != NULL) {
break;
}
}
}
}
if (sercom == NULL) {
mp_raise_ValueError(translate("Invalid pins"));
@ -259,10 +259,10 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) {
}
bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
uint8_t baud_reg_value = samd_peripherals_spi_baudrate_to_baud_reg_value(baudrate);
void * hw = self->spi_desc.dev.prvt;
void *hw = self->spi_desc.dev.prvt;
// If the settings are already what we want then don't reset them.
if (hri_sercomspi_get_CTRLA_CPHA_bit(hw) == phase &&
hri_sercomspi_get_CTRLA_CPOL_bit(hw) == polarity &&
@ -290,10 +290,10 @@ bool common_hal_busio_spi_configure(busio_spi_obj_t *self,
bool common_hal_busio_spi_try_lock(busio_spi_obj_t *self) {
bool grabbed_lock = false;
CRITICAL_SECTION_ENTER()
if (!self->has_lock) {
grabbed_lock = true;
self->has_lock = true;
}
if (!self->has_lock) {
grabbed_lock = true;
self->has_lock = true;
}
CRITICAL_SECTION_LEAVE();
return grabbed_lock;
}
@ -307,7 +307,7 @@ void common_hal_busio_spi_unlock(busio_spi_obj_t *self) {
}
bool common_hal_busio_spi_write(busio_spi_obj_t *self,
const uint8_t *data, size_t len) {
const uint8_t *data, size_t len) {
if (len == 0) {
return true;
}
@ -323,7 +323,7 @@ bool common_hal_busio_spi_write(busio_spi_obj_t *self,
}
bool common_hal_busio_spi_read(busio_spi_obj_t *self,
uint8_t *data, size_t len, uint8_t write_value) {
uint8_t *data, size_t len, uint8_t write_value) {
if (len == 0) {
return true;
}
@ -350,7 +350,7 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou
status = sercom_dma_transfer(self->spi_desc.dev.prvt, data_out, data_in, len);
} else {
struct spi_xfer xfer;
xfer.txbuf = (uint8_t*) data_out;
xfer.txbuf = (uint8_t *)data_out;
xfer.rxbuf = data_in;
xfer.size = len;
status = spi_m_sync_transfer(&self->spi_desc, &xfer);
@ -358,16 +358,16 @@ bool common_hal_busio_spi_transfer(busio_spi_obj_t *self, const uint8_t *data_ou
return status >= 0; // Status is number of chars read or an error code < 0.
}
uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t* self) {
uint32_t common_hal_busio_spi_get_frequency(busio_spi_obj_t *self) {
return samd_peripherals_spi_baud_reg_value_to_baudrate(hri_sercomspi_read_BAUD_reg(self->spi_desc.dev.prvt));
}
uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t* self) {
void * hw = self->spi_desc.dev.prvt;
uint8_t common_hal_busio_spi_get_phase(busio_spi_obj_t *self) {
void *hw = self->spi_desc.dev.prvt;
return hri_sercomspi_get_CTRLA_CPHA_bit(hw);
}
uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t* self) {
void * hw = self->spi_desc.dev.prvt;
uint8_t common_hal_busio_spi_get_polarity(busio_spi_obj_t *self) {
void *hw = self->spi_desc.dev.prvt;
return hri_sercomspi_get_CTRLA_CPOL_bit(hw);
}

2
ports/atmel-samd/common-hal/busio/SPI.h
View File

@ -43,7 +43,7 @@ typedef struct {
} busio_spi_obj_t;
void reset_sercoms(void);
void never_reset_sercom(Sercom* sercom);
void never_reset_sercom(Sercom *sercom);
#endif // MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_BUSIO_SPI_H

2
ports/atmel-samd/common-hal/busio/UART.h
View File

@ -43,7 +43,7 @@ typedef struct {
uint32_t baudrate;
uint32_t timeout_ms;
uint32_t buffer_length;
uint8_t* buffer;
uint8_t *buffer;
} busio_uart_obj_t;
#endif // MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_BUSIO_UART_H

42
ports/atmel-samd/common-hal/canio/CAN.c
View File

@ -40,15 +40,14 @@
#include "genhdr/candata.h"
STATIC Can * const can_insts[] = CAN_INSTS;
STATIC Can *const can_insts[] = CAN_INSTS;
STATIC canio_can_obj_t *can_objs[MP_ARRAY_SIZE(can_insts)];
// This must be placed in the first 64kB of RAM
STATIC COMPILER_SECTION(".canram") canio_can_state_t can_state[MP_ARRAY_SIZE(can_insts)];
void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mcu_pin_obj_t *rx, int baudrate, bool loopback, bool silent)
{
void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mcu_pin_obj_t *rx, int baudrate, bool loopback, bool silent) {
mcu_pin_function_t *tx_function = mcu_find_pin_function(can_tx, tx, -1, MP_QSTR_tx);
int instance = tx_function->instance;
@ -56,7 +55,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
const uint32_t can_frequency = CONF_CAN0_FREQUENCY;
#define DIV_ROUND(a, b) (((a) + (b)/2) / (b))
#define DIV_ROUND(a, b) (((a) + (b) / 2) / (b))
#define DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
uint32_t clocks_per_bit = DIV_ROUND(can_frequency, baudrate);
@ -97,7 +96,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
NVIC_ClearPendingIRQ(CAN0_IRQn);
NVIC_EnableIRQ(CAN0_IRQn);
hri_can_write_ILE_reg(self->hw, CAN_ILE_EINT0);
#ifdef CAN1_GCLK_ID
#ifdef CAN1_GCLK_ID
} else if (instance == 1) {
hri_mclk_set_AHBMASK_CAN1_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, CAN1_GCLK_ID, CONF_GCLK_CAN1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
@ -106,7 +105,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
NVIC_ClearPendingIRQ(CAN1_IRQn);
NVIC_EnableIRQ(CAN1_IRQn);
hri_can_write_ILE_reg(self->hw, CAN_ILE_EINT0);
#endif
#endif
}
self->hw->CCCR.bit.FDOE = 0; // neither FD nor Bit Rate Switch enabled
@ -237,12 +236,12 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
NVIC_DisableIRQ(CAN0_IRQn);
NVIC_ClearPendingIRQ(CAN0_IRQn);
NVIC_EnableIRQ(CAN0_IRQn);
#ifdef CAN1_GCLK_ID
#ifdef CAN1_GCLK_ID
} else if (instance == 1) {
NVIC_DisableIRQ(CAN1_IRQn);
NVIC_ClearPendingIRQ(CAN1_IRQn);
NVIC_EnableIRQ(CAN1_IRQn);
#endif
#endif
}
hri_can_write_ILE_reg(self->hw, CAN_ILE_EINT0);
@ -255,23 +254,19 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, mcu_pin_obj_t *tx, mc
can_objs[instance] = self;
}
bool common_hal_canio_can_loopback_get(canio_can_obj_t *self)
{
bool common_hal_canio_can_loopback_get(canio_can_obj_t *self) {
return self->loopback;
}
int common_hal_canio_can_baudrate_get(canio_can_obj_t *self)
{
int common_hal_canio_can_baudrate_get(canio_can_obj_t *self) {
return self->baudrate;
}
int common_hal_canio_can_transmit_error_count_get(canio_can_obj_t *self)
{
int common_hal_canio_can_transmit_error_count_get(canio_can_obj_t *self) {
return self->hw->ECR.bit.TEC;
}
int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self)
{
int common_hal_canio_can_receive_error_count_get(canio_can_obj_t *self) {
return self->hw->ECR.bit.REC;
}
@ -313,11 +308,11 @@ static void maybe_auto_restart(canio_can_obj_t *self) {
}
}
void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in)
{
void common_hal_canio_can_send(canio_can_obj_t *self, mp_obj_t message_in) {
maybe_auto_restart(self);
canio_message_obj_t *message = message_in;;
canio_message_obj_t *message = message_in;
;
// We have just one dedicated TX buffer, use it!
canio_can_tx_buffer_t *ent = &self->state->tx_buffer[0];
@ -365,8 +360,7 @@ void common_hal_canio_can_check_for_deinit(canio_can_obj_t *self) {
}
}
void common_hal_canio_can_deinit(canio_can_obj_t *self)
{
void common_hal_canio_can_deinit(canio_can_obj_t *self) {
if (self->hw) {
hri_can_set_CCCR_INIT_bit(self->hw);
self->hw = 0;
@ -384,11 +378,11 @@ void common_hal_canio_can_deinit(canio_can_obj_t *self)
void common_hal_canio_reset(void) {
memset(can_state, 0, sizeof(can_state));
for (size_t i=0; i<MP_ARRAY_SIZE(can_insts); i++) {
for (size_t i = 0; i < MP_ARRAY_SIZE(can_insts); i++) {
hri_can_set_CCCR_INIT_bit(can_insts[i]);
}
for (size_t i=0; i<MP_ARRAY_SIZE(can_objs); i++) {
for (size_t i = 0; i < MP_ARRAY_SIZE(can_objs); i++) {
if (can_objs[i]) {
common_hal_canio_can_deinit(can_objs[i]);
can_objs[i] = NULL;
@ -399,7 +393,7 @@ void common_hal_canio_reset(void) {
STATIC void can_handler(int i) {
canio_can_obj_t *self = can_objs[i];
(void) self;
(void)self;
Can *hw = can_insts[i];
uint32_t ir = hri_can_read_IR_reg(hw);

14
ports/atmel-samd/common-hal/canio/CAN.h
View File

@ -42,11 +42,11 @@ typedef struct canio_can_obj {
Can *hw;
canio_can_state_t *state;
int baudrate;
uint8_t rx_pin_number:8;
uint8_t tx_pin_number:8;
bool loopback:1;
bool silent:1;
bool auto_restart:1;
bool fifo0_in_use:1;
bool fifo1_in_use:1;
uint8_t rx_pin_number : 8;
uint8_t tx_pin_number : 8;
bool loopback : 1;
bool silent : 1;
bool auto_restart : 1;
bool fifo0_in_use : 1;
bool fifo1_in_use : 1;
} canio_can_obj_t;

34
ports/atmel-samd/common-hal/canio/Listener.c
View File

@ -73,7 +73,7 @@ STATIC bool extended_filter_in_use(CanMramXidfe *filter) {
STATIC size_t num_filters_needed(size_t nmatch, canio_match_obj_t **matches, bool extended) {
size_t num_half_filters_needed = 1;
for(size_t i=0; i<nmatch; i++) {
for (size_t i = 0; i < nmatch; i++) {
if (extended != matches[i]->extended) {
continue;
}
@ -89,13 +89,13 @@ STATIC size_t num_filters_needed(size_t nmatch, canio_match_obj_t **matches, boo
STATIC size_t num_filters_available(canio_can_obj_t *can, bool extended) {
size_t available = 0;
if (extended) {
for(size_t i = 0; i < MP_ARRAY_SIZE(can->state->extended_rx_filter); i++) {
for (size_t i = 0; i < MP_ARRAY_SIZE(can->state->extended_rx_filter); i++) {
if (!extended_filter_in_use(&can->state->extended_rx_filter[i])) {
available++;
}
}
} else {
for(size_t i = 0; i < MP_ARRAY_SIZE(can->state->standard_rx_filter); i++) {
for (size_t i = 0; i < MP_ARRAY_SIZE(can->state->standard_rx_filter); i++) {
if (!standard_filter_in_use(&can->state->standard_rx_filter[i])) {
available++;
}
@ -119,13 +119,13 @@ STATIC void clear_filters(canio_listener_obj_t *self) {
prevent_config_change(can);
// For each filter entry, if it pointed at this FIFO set it to DISABLE
for(size_t i = 0; i < MP_ARRAY_SIZE(can->state->extended_rx_filter); i++) {
for (size_t i = 0; i < MP_ARRAY_SIZE(can->state->extended_rx_filter); i++) {
int val = CAN_XIDFE_0_EFEC_STF0M_Val + fifo;
if (can->state->extended_rx_filter[i].XIDFE_0.bit.EFEC == val) {
can->state->extended_rx_filter[i].XIDFE_0.bit.EFEC = CAN_XIDFE_0_EFEC_DISABLE_Val;
}
}
for(size_t i = 0; i < MP_ARRAY_SIZE(can->state->standard_rx_filter); i++) {
for (size_t i = 0; i < MP_ARRAY_SIZE(can->state->standard_rx_filter); i++) {
int val = CAN_SIDFE_0_SFEC_STF1M_Val + fifo;
if (can->state->standard_rx_filter[i].SIDFE_0.bit.SFEC == val) {
can->state->standard_rx_filter[i].SIDFE_0.bit.SFEC = CAN_SIDFE_0_SFEC_DISABLE_Val;
@ -212,7 +212,7 @@ void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **
// step 1: single id standard matches
// we have to gather up pairs and stuff them in a single filter entry
for(size_t i = 0; i<nmatch; i++) {
for (size_t i = 0; i < nmatch; i++) {
canio_match_obj_t *match = matches[i];
if (match->extended) {
continue;
@ -230,13 +230,13 @@ void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **
}
// step 1.5. odd single id standard match
if (first_id != NO_ID) {
install_standard_filter(standard, first_id, first_id, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_DUAL_Val);
standard = next_standard_filter(self, standard);
first_id = NO_ID;
install_standard_filter(standard, first_id, first_id, CAN_SIDFE_0_SFEC_STF0M_Val + fifo, CAN_SIDFE_0_SFT_DUAL_Val);
standard = next_standard_filter(self, standard);
first_id = NO_ID;
}
// step 2: standard mask filter
for(size_t i = 0; i<nmatch; i++) {
for (size_t i = 0; i < nmatch; i++) {
canio_match_obj_t *match = matches[i];
if (match->extended) {
continue;
@ -250,7 +250,7 @@ void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **
// step 3: single id extended matches
// we have to gather up pairs and stuff them in a single filter entry
for(size_t i = 0; i<nmatch; i++) {
for (size_t i = 0; i < nmatch; i++) {
canio_match_obj_t *match = matches[i];
if (!match->extended) {
continue;
@ -268,13 +268,13 @@ void set_filters(canio_listener_obj_t *self, size_t nmatch, canio_match_obj_t **
}
// step 3.5. odd single id standard match
if (first_id != NO_ID) {
install_extended_filter(extended, first_id, first_id, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_DUAL_Val);
extended = next_extended_filter(self, extended);
first_id = NO_ID;
install_extended_filter(extended, first_id, first_id, CAN_XIDFE_0_EFEC_STF0M_Val + fifo, CAN_XIDFE_1_EFT_DUAL_Val);
extended = next_extended_filter(self, extended);
first_id = NO_ID;
}
// step 4: extended mask filters
for(size_t i = 0; i<nmatch; i++) {
for (size_t i = 0; i < nmatch; i++) {
canio_match_obj_t *match = matches[i];
if (!match->extended) {
continue;
@ -294,13 +294,13 @@ void common_hal_canio_listener_construct(canio_listener_obj_t *self, canio_can_o
if (!can->fifo0_in_use) {
self->fifo_idx = 0;
self->fifo = can->state->rx0_fifo;
self->hw = (canio_rxfifo_reg_t*)&can->hw->RXF0C;
self->hw = (canio_rxfifo_reg_t *)&can->hw->RXF0C;
can->hw->IR.reg = CAN_IR_RF0N | CAN_IR_RF0W | CAN_IR_RF0F | CAN_IR_RF0L;
can->fifo0_in_use = true;
} else if (!can->fifo1_in_use) {
self->fifo_idx = 1;
self->fifo = can->state->rx1_fifo;
self->hw = (canio_rxfifo_reg_t*)&can->hw->RXF1C;
self->hw = (canio_rxfifo_reg_t *)&can->hw->RXF1C;
can->fifo1_in_use = true;
can->hw->IR.reg = CAN_IR_RF1N | CAN_IR_RF1W | CAN_IR_RF1F | CAN_IR_RF1L;
} else {

6
ports/atmel-samd/common-hal/canio/Listener.h
View File

@ -30,9 +30,9 @@
#include "shared-module/canio/Match.h"
typedef struct {
__IO CAN_RXF0C_Type RXFC; /**< \brief (R/W 32) Rx FIFO n Configuration */
__I CAN_RXF0S_Type RXFS; /**< \brief (R/ 32) Rx FIFO n Status */
__IO CAN_RXF0A_Type RXFA; /**< \brief (R/W 32) Rx FIFO n Acknowledge */
__IO CAN_RXF0C_Type RXFC; /**< \brief (R/W 32) Rx FIFO n Configuration */
__I CAN_RXF0S_Type RXFS; /**< \brief (R/ 32) Rx FIFO n Status */
__IO CAN_RXF0A_Type RXFA; /**< \brief (R/W 32) Rx FIFO n Acknowledge */
} canio_rxfifo_reg_t;
typedef struct canio_listener_obj {

22
ports/atmel-samd/common-hal/countio/Counter.c
View File

@ -8,8 +8,8 @@
#include "py/runtime.h"
#include "supervisor/shared/translate.h"
void common_hal_countio_counter_construct(countio_counter_obj_t* self,
const mcu_pin_obj_t* pin_a) {
void common_hal_countio_counter_construct(countio_counter_obj_t *self,
const mcu_pin_obj_t *pin_a) {
if (!pin_a->has_extint) {
mp_raise_RuntimeError(translate("Pin must support hardware interrupts"));
}
@ -31,7 +31,7 @@ void common_hal_countio_counter_construct(countio_counter_obj_t* self,
gpio_set_pin_function(self->pin_a, GPIO_PIN_FUNCTION_A);
gpio_set_pin_pull_mode(self->pin_a, GPIO_PULL_UP);
set_eic_channel_data(self->eic_channel_a, (void*) self);
set_eic_channel_data(self->eic_channel_a, (void *)self);
self->count = 0;
@ -44,11 +44,11 @@ void common_hal_countio_counter_construct(countio_counter_obj_t* self,
}
bool common_hal_countio_counter_deinited(countio_counter_obj_t* self) {
bool common_hal_countio_counter_deinited(countio_counter_obj_t *self) {
return self->pin_a == NO_PIN;
}
void common_hal_countio_counter_deinit(countio_counter_obj_t* self) {
void common_hal_countio_counter_deinit(countio_counter_obj_t *self) {
if (common_hal_countio_counter_deinited(self)) {
return;
}
@ -62,21 +62,21 @@ void common_hal_countio_counter_deinit(countio_counter_obj_t* self) {
}
mp_int_t common_hal_countio_counter_get_count(countio_counter_obj_t* self) {
mp_int_t common_hal_countio_counter_get_count(countio_counter_obj_t *self) {
return self->count;
}
void common_hal_countio_counter_set_count(countio_counter_obj_t* self,
mp_int_t new_count) {
void common_hal_countio_counter_set_count(countio_counter_obj_t *self,
mp_int_t new_count) {
self->count = new_count;
}
void common_hal_countio_counter_reset(countio_counter_obj_t* self){
self->count = 0;
void common_hal_countio_counter_reset(countio_counter_obj_t *self) {
self->count = 0;
}
void counter_interrupt_handler(uint8_t channel) {
countio_counter_obj_t* self = get_eic_channel_data(channel);
countio_counter_obj_t *self = get_eic_channel_data(channel);
self->count += 1;

2
ports/atmel-samd/common-hal/countio/Counter.h
View File

@ -9,7 +9,7 @@
typedef struct {
mp_obj_base_t base;
uint8_t pin_a;
uint8_t eic_channel_a:4;
uint8_t eic_channel_a : 4;
mp_int_t count;
} countio_counter_obj_t;

2
ports/atmel-samd/common-hal/countio/__init__.c
View File

@ -1 +1 @@
//No countio module functions
// No countio module functions

33
ports/atmel-samd/common-hal/digitalio/DigitalInOut.c
View File

@ -37,7 +37,7 @@
#include "supervisor/shared/translate.h"
digitalinout_result_t common_hal_digitalio_digitalinout_construct(
digitalio_digitalinout_obj_t* self, const mcu_pin_obj_t* pin) {
digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) {
claim_pin(pin);
self->pin = pin;
self->output = false;
@ -50,15 +50,15 @@ digitalinout_result_t common_hal_digitalio_digitalinout_construct(
}
void common_hal_digitalio_digitalinout_never_reset(
digitalio_digitalinout_obj_t *self) {
digitalio_digitalinout_obj_t *self) {
never_reset_pin_number(self->pin->number);
}
bool common_hal_digitalio_digitalinout_deinited(digitalio_digitalinout_obj_t* self) {
bool common_hal_digitalio_digitalinout_deinited(digitalio_digitalinout_obj_t *self) {
return self->pin == NULL;
}
void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t* self) {
void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self) {
if (common_hal_digitalio_digitalinout_deinited(self)) {
return;
}
@ -67,15 +67,15 @@ void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t* self
}
void common_hal_digitalio_digitalinout_switch_to_input(
digitalio_digitalinout_obj_t* self, digitalio_pull_t pull) {
digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) {
self->output = false;
// This also sets direction to input.
common_hal_digitalio_digitalinout_set_pull(self, pull);
}
digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output(
digitalio_digitalinout_obj_t* self, bool value,
digitalio_drive_mode_t drive_mode) {
digitalio_digitalinout_obj_t *self, bool value,
digitalio_drive_mode_t drive_mode) {
const uint8_t pin = self->pin->number;
gpio_set_pin_pull_mode(pin, GPIO_PULL_OFF);
// Turn on "strong" pin driving (more current available). See DRVSTR doc in datasheet.
@ -90,12 +90,12 @@ digitalinout_result_t common_hal_digitalio_digitalinout_switch_to_output(
}
digitalio_direction_t common_hal_digitalio_digitalinout_get_direction(
digitalio_digitalinout_obj_t* self) {
digitalio_digitalinout_obj_t *self) {
return self->output ? DIRECTION_OUTPUT : DIRECTION_INPUT;
}
void common_hal_digitalio_digitalinout_set_value(
digitalio_digitalinout_obj_t* self, bool value) {
digitalio_digitalinout_obj_t *self, bool value) {
const uint8_t pin = self->pin->number;
const uint8_t port = GPIO_PORT(pin);
const uint32_t pin_mask = 1U << GPIO_PIN(pin);
@ -116,7 +116,7 @@ void common_hal_digitalio_digitalinout_set_value(
}
bool common_hal_digitalio_digitalinout_get_value(
digitalio_digitalinout_obj_t* self) {
digitalio_digitalinout_obj_t *self) {
const uint8_t pin = self->pin->number;
if (!self->output) {
return gpio_get_pin_level(pin);
@ -130,8 +130,8 @@ bool common_hal_digitalio_digitalinout_get_value(
}
digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode(
digitalio_digitalinout_obj_t* self,
digitalio_drive_mode_t drive_mode) {
digitalio_digitalinout_obj_t *self,
digitalio_drive_mode_t drive_mode) {
bool value = common_hal_digitalio_digitalinout_get_value(self);
self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN;
// True is implemented differently between modes so reset the value to make
@ -143,7 +143,7 @@ digitalinout_result_t common_hal_digitalio_digitalinout_set_drive_mode(
}
digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode(
digitalio_digitalinout_obj_t* self) {
digitalio_digitalinout_obj_t *self) {
if (self->open_drain) {
return DRIVE_MODE_OPEN_DRAIN;
} else {
@ -152,7 +152,7 @@ digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode(
}
void common_hal_digitalio_digitalinout_set_pull(
digitalio_digitalinout_obj_t* self, digitalio_pull_t pull) {
digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) {
enum gpio_pull_mode asf_pull = GPIO_PULL_OFF;
switch (pull) {
case PULL_UP:
@ -171,7 +171,7 @@ void common_hal_digitalio_digitalinout_set_pull(
}
digitalio_pull_t common_hal_digitalio_digitalinout_get_pull(
digitalio_digitalinout_obj_t* self) {
digitalio_digitalinout_obj_t *self) {
uint32_t pin = self->pin->number;
if (self->output) {
mp_raise_AttributeError(translate("Cannot get pull while in output mode"));
@ -179,7 +179,8 @@ digitalio_pull_t common_hal_digitalio_digitalinout_get_pull(
} else {
if (hri_port_get_PINCFG_PULLEN_bit(PORT, GPIO_PORT(pin), GPIO_PIN(pin)) == 0) {
return PULL_NONE;
} if (hri_port_get_OUT_reg(PORT, GPIO_PORT(pin), 1U << GPIO_PIN(pin)) > 0) {
}
if (hri_port_get_OUT_reg(PORT, GPIO_PORT(pin), 1U << GPIO_PIN(pin)) > 0) {
return PULL_UP;
} else {
return PULL_DOWN;

2
ports/atmel-samd/common-hal/digitalio/DigitalInOut.h
View File

@ -32,7 +32,7 @@
typedef struct {
mp_obj_base_t base;
const mcu_pin_obj_t * pin;
const mcu_pin_obj_t *pin;
bool output;
bool open_drain;
} digitalio_digitalinout_obj_t;

4
ports/atmel-samd/common-hal/displayio/ParallelBus.h
View File

@ -31,14 +31,14 @@
typedef struct {
mp_obj_base_t base;
uint8_t* bus;
uint8_t *bus;
digitalio_digitalinout_obj_t command;
digitalio_digitalinout_obj_t chip_select;
digitalio_digitalinout_obj_t reset;
digitalio_digitalinout_obj_t write;
digitalio_digitalinout_obj_t read;
uint8_t data0_pin;
PortGroup* write_group;
PortGroup *write_group;
uint32_t write_mask;
} displayio_parallelbus_obj_t;

54
ports/atmel-samd/common-hal/imagecapture/ParallelImageCapture.c
View File

@ -54,14 +54,12 @@ void common_hal_imagecapture_parallelimagecapture_construct(imagecapture_paralle
const mcu_pin_obj_t *data_clock,
const mcu_pin_obj_t *vertical_sync,
const mcu_pin_obj_t *horizontal_reference,
int data_count)
{
int data_count) {
if (data0->number != PIN_PCC_D0) {
mp_raise_ValueError_varg(translate("Invalid %q pin"), MP_QSTR_data0);
}
// The peripheral supports 8, 10, 12, or 14 data bits, but the code only supports 8 at present
if (data_count != 8)
{
if (data_count != 8) {
mp_raise_ValueError_varg(translate("Invalid data_count %d"), data_count);
}
if (vertical_sync && vertical_sync->number != PIN_PCC_DEN1) {
@ -74,7 +72,7 @@ void common_hal_imagecapture_parallelimagecapture_construct(imagecapture_paralle
mp_raise_ValueError_varg(translate("Invalid %q pin"), MP_QSTR_data_clock);
}
// technically, 0 was validated as free already but check again
for (int i=0; i<data_count; i++) {
for (int i = 0; i < data_count; i++) {
if (!pin_number_is_free(data0->number + i)) {
mp_raise_ValueError_varg(translate("data pin #%d in use"), i);
}
@ -87,8 +85,8 @@ void common_hal_imagecapture_parallelimagecapture_construct(imagecapture_paralle
// Accumulate 4 bytes into RHR register (two 16-bit pixels)
PCC->MR.reg = PCC_MR_CID(0x1) | // Clear on falling DEN1 (VSYNC)
PCC_MR_ISIZE(0x0) | // Input data bus is 8 bits
PCC_MR_DSIZE(0x2); // "4 data" at a time (accumulate in RHR)
PCC_MR_ISIZE(0x0) | // Input data bus is 8 bits
PCC_MR_DSIZE(0x2); // "4 data" at a time (accumulate in RHR)
PCC->MR.bit.PCEN = 1; // Enable PCC
@ -100,62 +98,59 @@ void common_hal_imagecapture_parallelimagecapture_construct(imagecapture_paralle
gpio_set_pin_direction(PIN_PCC_CLK, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PIN_PCC_CLK, GPIO_PULL_OFF);
gpio_set_pin_function(PIN_PCC_CLK, GPIO_PIN_FUNCTION_PCC);
//claim_pin_number(PIN_PCC_CLK);
// claim_pin_number(PIN_PCC_CLK);
if (vertical_sync) {
gpio_set_pin_direction(PIN_PCC_DEN1, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PIN_PCC_DEN1, GPIO_PULL_OFF);
gpio_set_pin_function(PIN_PCC_DEN1, GPIO_PIN_FUNCTION_PCC); // VSYNC
//claim_pin_number(PIN_PCC_DEN1);
// claim_pin_number(PIN_PCC_DEN1);
}
if (horizontal_reference) {
gpio_set_pin_direction(PIN_PCC_DEN2, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PIN_PCC_DEN2, GPIO_PULL_OFF);
gpio_set_pin_function(PIN_PCC_DEN2, GPIO_PIN_FUNCTION_PCC); // HSYNC
//claim_pin_number(PIN_PCC_DEN2);
// claim_pin_number(PIN_PCC_DEN2);
}
for (int i=0; i<data_count; i++) {
gpio_set_pin_direction(PIN_PCC_D0+i, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PIN_PCC_D0+i, GPIO_PULL_OFF);
gpio_set_pin_function(PIN_PCC_D0+i, GPIO_PIN_FUNCTION_PCC);
//claim_pin_number(PIN_PCC_D0+i);
for (int i = 0; i < data_count; i++) {
gpio_set_pin_direction(PIN_PCC_D0 + i, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(PIN_PCC_D0 + i, GPIO_PULL_OFF);
gpio_set_pin_function(PIN_PCC_D0 + i, GPIO_PIN_FUNCTION_PCC);
// claim_pin_number(PIN_PCC_D0+i);
}
}
void common_hal_imagecapture_parallelimagecapture_deinit(imagecapture_parallelimagecapture_obj_t *self)
{
void common_hal_imagecapture_parallelimagecapture_deinit(imagecapture_parallelimagecapture_obj_t *self) {
if (common_hal_imagecapture_parallelimagecapture_deinited(self)) {
return;
}
reset_pin_number(self->vertical_sync);
reset_pin_number(self->horizontal_reference);
reset_pin_number(PIN_PCC_CLK);
for (int i=0; i<self->data_count; i++) {
for (int i = 0; i < self->data_count; i++) {
reset_pin_number(PIN_PCC_D0 + i);
}
self->data_count = 0;
}
bool common_hal_imagecapture_parallelimagecapture_deinited(imagecapture_parallelimagecapture_obj_t *self)
{
bool common_hal_imagecapture_parallelimagecapture_deinited(imagecapture_parallelimagecapture_obj_t *self) {
return self->data_count == 0;
}
static void setup_dma(DmacDescriptor* descriptor, size_t count, uint32_t *buffer) {
static void setup_dma(DmacDescriptor *descriptor, size_t count, uint32_t *buffer) {
descriptor->BTCTRL.reg = DMAC_BTCTRL_VALID |
DMAC_BTCTRL_BLOCKACT_NOACT |
DMAC_BTCTRL_EVOSEL_BLOCK |
DMAC_BTCTRL_DSTINC |
DMAC_BTCTRL_BEATSIZE_WORD;
DMAC_BTCTRL_BLOCKACT_NOACT |
DMAC_BTCTRL_EVOSEL_BLOCK |
DMAC_BTCTRL_DSTINC |
DMAC_BTCTRL_BEATSIZE_WORD;
descriptor->BTCNT.reg = count;
descriptor->DSTADDR.reg = (uint32_t)buffer + 4*count;
descriptor->DSTADDR.reg = (uint32_t)buffer + 4 * count;
descriptor->SRCADDR.reg = (uint32_t)&PCC->RHR.reg;
descriptor->DESCADDR.reg = 0;
}
#include <string.h>
void common_hal_imagecapture_parallelimagecapture_capture(imagecapture_parallelimagecapture_obj_t *self, void *buffer, size_t bufsize)
{
void common_hal_imagecapture_parallelimagecapture_capture(imagecapture_parallelimagecapture_obj_t *self, void *buffer, size_t bufsize) {
uint8_t dma_channel = dma_allocate_channel();
@ -171,8 +166,7 @@ void common_hal_imagecapture_parallelimagecapture_capture(imagecapture_paralleli
const volatile uint32_t *vsync_reg = &PORT->Group[(self->vertical_sync / 32)].IN.reg;
uint32_t vsync_bit = 1 << (self->vertical_sync % 32);
while (*vsync_reg & vsync_bit)
{
while (*vsync_reg & vsync_bit) {
// Wait for VSYNC low (frame end)
RUN_BACKGROUND_TASKS;

111
ports/atmel-samd/common-hal/neopixel_write/__init__.c
View File

@ -44,71 +44,72 @@
__attribute__((naked,noinline,aligned(16)))
static void neopixel_send_buffer_core(volatile uint32_t *clraddr, uint32_t pinMask,
const uint8_t *ptr, int numBytes);
const uint8_t *ptr, int numBytes);
static void neopixel_send_buffer_core(volatile uint32_t *clraddr, uint32_t pinMask,
const uint8_t *ptr, int numBytes) {
asm volatile(" push {r4, r5, r6, lr};"
" add r3, r2, r3;"
"loopLoad:"
" ldrb r5, [r2, #0];" // r5 := *ptr
" add r2, #1;" // ptr++
" movs r4, #128;" // r4-mask, 0x80
"loopBit:"
" str r1, [r0, #4];" // set
#ifdef SAMD21
" movs r6, #3; d2: sub r6, #1; bne d2;" // delay 3
#endif
#ifdef SAM_D5X_E5X
" movs r6, #3; d2: subs r6, #1; bne d2;" // delay 3
#endif
" tst r4, r5;" // mask&r5
" bne skipclr;"
" str r1, [r0, #0];" // clr
"skipclr:"
#ifdef SAMD21
" movs r6, #6; d0: sub r6, #1; bne d0;" // delay 6
#endif
#ifdef SAM_D5X_E5X
" movs r6, #6; d0: subs r6, #1; bne d0;" // delay 6
#endif
" str r1, [r0, #0];" // clr (possibly again, doesn't matter)
#ifdef SAMD21
" asr r4, r4, #1;" // mask >>= 1
#endif
#ifdef SAM_D5X_E5X
" asrs r4, r4, #1;" // mask >>= 1
#endif
" beq nextbyte;"
" uxtb r4, r4;"
#ifdef SAMD21
" movs r6, #2; d1: sub r6, #1; bne d1;" // delay 2
#endif
#ifdef SAM_D5X_E5X
" movs r6, #2; d1: subs r6, #1; bne d1;" // delay 2
#endif
" b loopBit;"
"nextbyte:"
" cmp r2, r3;"
" bcs neopixel_stop;"
" b loopLoad;"
"neopixel_stop:"
" pop {r4, r5, r6, pc};"
"");
const uint8_t *ptr, int numBytes) {
asm volatile (" push {r4, r5, r6, lr};"
" add r3, r2, r3;"
"loopLoad:"
" ldrb r5, [r2, #0];" // r5 := *ptr
" add r2, #1;" // ptr++
" movs r4, #128;" // r4-mask, 0x80
"loopBit:"
" str r1, [r0, #4];" // set
#ifdef SAMD21
" movs r6, #3; d2: sub r6, #1; bne d2;" // delay 3
#endif
#ifdef SAM_D5X_E5X
" movs r6, #3; d2: subs r6, #1; bne d2;" // delay 3
#endif
" tst r4, r5;" // mask&r5
" bne skipclr;"
" str r1, [r0, #0];" // clr
"skipclr:"
#ifdef SAMD21
" movs r6, #6; d0: sub r6, #1; bne d0;" // delay 6
#endif
#ifdef SAM_D5X_E5X
" movs r6, #6; d0: subs r6, #1; bne d0;" // delay 6
#endif
" str r1, [r0, #0];" // clr (possibly again, doesn't matter)
#ifdef SAMD21
" asr r4, r4, #1;" // mask >>= 1
#endif
#ifdef SAM_D5X_E5X
" asrs r4, r4, #1;" // mask >>= 1
#endif
" beq nextbyte;"
" uxtb r4, r4;"
#ifdef SAMD21
" movs r6, #2; d1: sub r6, #1; bne d1;" // delay 2
#endif
#ifdef SAM_D5X_E5X
" movs r6, #2; d1: subs r6, #1; bne d1;" // delay 2
#endif
" b loopBit;"
"nextbyte:"
" cmp r2, r3;"
" bcs neopixel_stop;"
" b loopLoad;"
"neopixel_stop:"
" pop {r4, r5, r6, pc};"
"");
}
uint64_t next_start_raw_ticks = 0;
void common_hal_neopixel_write(const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, uint32_t numBytes) {
void common_hal_neopixel_write(const digitalio_digitalinout_obj_t *digitalinout, uint8_t *pixels, uint32_t numBytes) {
// This is adapted directly from the Adafruit NeoPixel library SAMD21G18A code:
// https://github.com/adafruit/Adafruit_NeoPixel/blob/master/Adafruit_NeoPixel.cpp
// and the asm version from https://github.com/microsoft/uf2-samdx1/blob/master/inc/neopixel.h
uint32_t pinMask;
PortGroup* port;
uint32_t pinMask;
PortGroup *port;
// Wait to make sure we don't append onto the last transmission. This should only be a tick or
// two.
while (port_get_raw_ticks(NULL) < next_start_raw_ticks) {}
while (port_get_raw_ticks(NULL) < next_start_raw_ticks) {
}
// Turn off interrupts of any kind during timing-sensitive code.
mp_hal_disable_all_interrupts();
@ -136,8 +137,8 @@ void common_hal_neopixel_write(const digitalio_digitalinout_obj_t* digitalinout,
#endif
uint32_t pin = digitalinout->pin->number;
port = &PORT->Group[GPIO_PORT(pin)]; // Convert GPIO # to port register
pinMask = (1UL << (pin % 32)); // From port_pin_set_output_level ASF code.
port = &PORT->Group[GPIO_PORT(pin)]; // Convert GPIO # to port register
pinMask = (1UL << (pin % 32)); // From port_pin_set_output_level ASF code.
volatile uint32_t *clr = &(port->OUTCLR.reg);
neopixel_send_buffer_core(clr, pinMask, pixels, numBytes);

6
ports/atmel-samd/common-hal/nvm/ByteArray.c
View File

@ -38,18 +38,18 @@ uint32_t common_hal_nvm_bytearray_get_length(nvm_bytearray_obj_t *self) {
}
bool common_hal_nvm_bytearray_set_bytes(nvm_bytearray_obj_t *self,
uint32_t start_index, uint8_t* values, uint32_t len) {
uint32_t start_index, uint8_t *values, uint32_t len) {
// We don't use features that use any advanced NVMCTRL features so we can fake the descriptor
// whenever we need it instead of storing it long term.
struct flash_descriptor desc;
desc.dev.hw = NVMCTRL;
bool status = flash_write(&desc, (uint32_t) self->start_address + start_index, values, len) == ERR_NONE;
bool status = flash_write(&desc, (uint32_t)self->start_address + start_index, values, len) == ERR_NONE;
assert_heap_ok();
return status;
}
// NVM memory is memory mapped so reading it is easy.
void common_hal_nvm_bytearray_get_bytes(nvm_bytearray_obj_t *self,
uint32_t start_index, uint32_t len, uint8_t* values) {
uint32_t start_index, uint32_t len, uint8_t *values) {
memcpy(values, self->start_address + start_index, len);
}

2
ports/atmel-samd/common-hal/nvm/ByteArray.h
View File

@ -31,7 +31,7 @@
typedef struct {
mp_obj_base_t base;
uint8_t* start_address;
uint8_t *start_address;
uint32_t len;
} nvm_bytearray_obj_t;

4
ports/atmel-samd/common-hal/os/__init__.c
View File

@ -60,13 +60,13 @@ STATIC MP_DEFINE_ATTRTUPLE(
(mp_obj_t)&os_uname_info_release_obj,
(mp_obj_t)&os_uname_info_version_obj,
(mp_obj_t)&os_uname_info_machine_obj
);
);
mp_obj_t common_hal_os_uname(void) {
return (mp_obj_t)&os_uname_info_obj;
}
bool common_hal_os_urandom(uint8_t* buffer, uint32_t length) {
bool common_hal_os_urandom(uint8_t *buffer, uint32_t length) {
#ifdef SAM_D5X_E5X
hri_mclk_set_APBCMASK_TRNG_bit(MCLK);
struct rand_sync_desc random;

55
ports/atmel-samd/common-hal/ps2io/Ps2.c
View File

@ -63,18 +63,18 @@
#define ERROR_TX_RTS 0x1000
#define ERROR_TX_NORESP 0x2000
static void ps2_set_config(ps2io_ps2_obj_t* self) {
static void ps2_set_config(ps2io_ps2_obj_t *self) {
uint32_t sense_setting = EIC_CONFIG_SENSE0_FALL_Val;
set_eic_handler(self->channel, EIC_HANDLER_PS2);
turn_on_eic_channel(self->channel, sense_setting);
}
static void disable_interrupt(ps2io_ps2_obj_t* self) {
static void disable_interrupt(ps2io_ps2_obj_t *self) {
uint32_t mask = 1 << self->channel;
EIC->INTENCLR.reg = mask << EIC_INTENSET_EXTINT_Pos;
}
static void resume_interrupt(ps2io_ps2_obj_t* self) {
static void resume_interrupt(ps2io_ps2_obj_t *self) {
disable_interrupt(self);
self->state = STATE_IDLE;
@ -86,14 +86,14 @@ static void resume_interrupt(ps2io_ps2_obj_t* self) {
ps2_set_config(self);
}
static void clk_hi(ps2io_ps2_obj_t* self) {
static void clk_hi(ps2io_ps2_obj_t *self) {
// External pull-up
// Must set pull after setting direction.
gpio_set_pin_direction(self->clk_pin, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(self->clk_pin, GPIO_PULL_OFF);
}
static bool wait_clk_lo(ps2io_ps2_obj_t* self, uint32_t us) {
static bool wait_clk_lo(ps2io_ps2_obj_t *self, uint32_t us) {
clk_hi(self);
common_hal_mcu_delay_us(1);
while (gpio_get_pin_level(self->clk_pin) && us) {
@ -103,7 +103,7 @@ static bool wait_clk_lo(ps2io_ps2_obj_t* self, uint32_t us) {
return us;
}
static bool wait_clk_hi(ps2io_ps2_obj_t* self, uint32_t us) {
static bool wait_clk_hi(ps2io_ps2_obj_t *self, uint32_t us) {
clk_hi(self);
common_hal_mcu_delay_us(1);
while (!gpio_get_pin_level(self->clk_pin) && us) {
@ -113,19 +113,19 @@ static bool wait_clk_hi(ps2io_ps2_obj_t* self, uint32_t us) {
return us;
}
static void clk_lo(ps2io_ps2_obj_t* self) {
static void clk_lo(ps2io_ps2_obj_t *self) {
gpio_set_pin_pull_mode(self->clk_pin, GPIO_PULL_OFF);
gpio_set_pin_direction(self->clk_pin, GPIO_DIRECTION_OUT);
gpio_set_pin_level(self->clk_pin, 0);
}
static void data_hi(ps2io_ps2_obj_t* self) {
static void data_hi(ps2io_ps2_obj_t *self) {
// External pull-up
gpio_set_pin_direction(self->data_pin, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(self->data_pin, GPIO_PULL_OFF);
}
static bool wait_data_lo(ps2io_ps2_obj_t* self, uint32_t us) {
static bool wait_data_lo(ps2io_ps2_obj_t *self, uint32_t us) {
data_hi(self);
common_hal_mcu_delay_us(1);
while (gpio_get_pin_level(self->data_pin) && us) {
@ -135,7 +135,7 @@ static bool wait_data_lo(ps2io_ps2_obj_t* self, uint32_t us) {
return us;
}
static bool wait_data_hi(ps2io_ps2_obj_t* self, uint32_t us) {
static bool wait_data_hi(ps2io_ps2_obj_t *self, uint32_t us) {
data_hi(self);
common_hal_mcu_delay_us(1);
while (!gpio_get_pin_level(self->data_pin) && us) {
@ -145,18 +145,18 @@ static bool wait_data_hi(ps2io_ps2_obj_t* self, uint32_t us) {
return us;
}
static void data_lo(ps2io_ps2_obj_t* self) {
static void data_lo(ps2io_ps2_obj_t *self) {
gpio_set_pin_pull_mode(self->data_pin, GPIO_PULL_OFF);
gpio_set_pin_direction(self->data_pin, GPIO_DIRECTION_OUT);
gpio_set_pin_level(self->data_pin, 0);
}
static void idle(ps2io_ps2_obj_t* self) {
static void idle(ps2io_ps2_obj_t *self) {
clk_hi(self);
data_hi(self);
}
static void inhibit(ps2io_ps2_obj_t* self) {
static void inhibit(ps2io_ps2_obj_t *self) {
clk_lo(self);
data_hi(self);
}
@ -169,7 +169,7 @@ void ps2_interrupt_handler(uint8_t channel) {
// Grab the current time first.
uint64_t current_tick = port_get_raw_ticks(NULL);
ps2io_ps2_obj_t* self = get_eic_channel_data(channel);
ps2io_ps2_obj_t *self = get_eic_channel_data(channel);
int data_bit = gpio_get_pin_level(self->data_pin) ? 1 : 0;
// test for timeout
@ -192,7 +192,7 @@ void ps2_interrupt_handler(uint8_t channel) {
// start bit should be 0
self->last_errors |= ERROR_STARTBIT;
self->state = STATE_RECV_ERR;
} else {
} else {
self->state = STATE_RECV;
}
@ -220,7 +220,7 @@ void ps2_interrupt_handler(uint8_t channel) {
} else if (self->state == STATE_RECV_STOP) {
++self->bitcount;
if (! data_bit) {
if (!data_bit) {
self->last_errors |= ERROR_STOPBIT;
} else if (self->waiting_cmd_response) {
self->cmd_response = self->bits;
@ -242,8 +242,8 @@ void ps2_interrupt_handler(uint8_t channel) {
}
}
void common_hal_ps2io_ps2_construct(ps2io_ps2_obj_t* self,
const mcu_pin_obj_t* data_pin, const mcu_pin_obj_t* clk_pin) {
void common_hal_ps2io_ps2_construct(ps2io_ps2_obj_t *self,
const mcu_pin_obj_t *data_pin, const mcu_pin_obj_t *clk_pin) {
if (!clk_pin->has_extint) {
mp_raise_RuntimeError(translate("No hardware support on clk pin"));
}
@ -263,7 +263,7 @@ void common_hal_ps2io_ps2_construct(ps2io_ps2_obj_t* self,
self->bufposw = 0;
self->waiting_cmd_response = false;
set_eic_channel_data(clk_pin->extint_channel, (void*) self);
set_eic_channel_data(clk_pin->extint_channel, (void *)self);
// Check to see if the EIC is enabled and start it up if its not.'
if (eic_get_enable() == 0) {
@ -282,11 +282,11 @@ void common_hal_ps2io_ps2_construct(ps2io_ps2_obj_t* self,
ps2_set_config(self);
}
bool common_hal_ps2io_ps2_deinited(ps2io_ps2_obj_t* self) {
bool common_hal_ps2io_ps2_deinited(ps2io_ps2_obj_t *self) {
return self->clk_pin == NO_PIN;
}
void common_hal_ps2io_ps2_deinit(ps2io_ps2_obj_t* self) {
void common_hal_ps2io_ps2_deinit(ps2io_ps2_obj_t *self) {
if (common_hal_ps2io_ps2_deinited(self)) {
return;
}
@ -298,17 +298,16 @@ void common_hal_ps2io_ps2_deinit(ps2io_ps2_obj_t* self) {
self->data_pin = NO_PIN;
}
uint16_t common_hal_ps2io_ps2_get_len(ps2io_ps2_obj_t* self) {
uint16_t common_hal_ps2io_ps2_get_len(ps2io_ps2_obj_t *self) {
return self->bufcount;
}
bool common_hal_ps2io_ps2_get_paused(ps2io_ps2_obj_t* self) {
bool common_hal_ps2io_ps2_get_paused(ps2io_ps2_obj_t *self) {
uint32_t mask = 1 << self->channel;
return (EIC->INTENSET.reg & (mask << EIC_INTENSET_EXTINT_Pos)) == 0;
}
int16_t common_hal_ps2io_ps2_popleft(ps2io_ps2_obj_t* self)
{
int16_t common_hal_ps2io_ps2_popleft(ps2io_ps2_obj_t *self) {
common_hal_mcu_disable_interrupts();
if (self->bufcount <= 0) {
common_hal_mcu_enable_interrupts();
@ -321,8 +320,7 @@ int16_t common_hal_ps2io_ps2_popleft(ps2io_ps2_obj_t* self)
return b;
}
uint16_t common_hal_ps2io_ps2_clear_errors(ps2io_ps2_obj_t* self)
{
uint16_t common_hal_ps2io_ps2_clear_errors(ps2io_ps2_obj_t *self) {
common_hal_mcu_disable_interrupts();
uint16_t errors = self->last_errors;
self->last_errors = 0;
@ -333,8 +331,7 @@ uint16_t common_hal_ps2io_ps2_clear_errors(ps2io_ps2_obj_t* self)
// Based upon TMK implementation of PS/2 protocol
// https://github.com/tmk/tmk_keyboard/blob/master/tmk_core/protocol/ps2_interrupt.c
int16_t common_hal_ps2io_ps2_sendcmd(ps2io_ps2_obj_t* self, uint8_t b)
{
int16_t common_hal_ps2io_ps2_sendcmd(ps2io_ps2_obj_t *self, uint8_t b) {
disable_interrupt(self);
inhibit(self);
delay_us(100);

2
ports/atmel-samd/common-hal/pulseio/PulseIn.h
View File

@ -35,7 +35,7 @@ typedef struct {
mp_obj_base_t base;
uint8_t channel;
uint8_t pin;
uint16_t* buffer;
uint16_t *buffer;
uint16_t maxlen;
bool idle_state;
volatile uint16_t start;

52
ports/atmel-samd/common-hal/pulseio/PulseOut.c
View File

@ -51,11 +51,11 @@ static volatile uint16_t pulse_index = 0;
static uint16_t pulse_length;
static volatile uint32_t current_compare = 0;
static void turn_on(__IO PORT_PINCFG_Type * pincfg) {
static void turn_on(__IO PORT_PINCFG_Type *pincfg) {
pincfg->reg = PORT_PINCFG_PMUXEN;
}
static void turn_off(__IO PORT_PINCFG_Type * pincfg) {
static void turn_off(__IO PORT_PINCFG_Type *pincfg) {
pincfg->reg = PORT_PINCFG_RESETVALUE;
}
@ -71,7 +71,7 @@ void pulse_finish(void) {
return;
}
current_compare = (current_compare + pulse_buffer[pulse_index] * 3 / 4) & 0xffff;
Tc* tc = tc_insts[pulseout_tc_index];
Tc *tc = tc_insts[pulseout_tc_index];
tc->COUNT16.CC[0].reg = current_compare;
if (pulse_index % 2 == 0) {
turn_on(active_pincfg);
@ -79,9 +79,13 @@ void pulse_finish(void) {
}
void pulseout_interrupt_handler(uint8_t index) {
if (index != pulseout_tc_index) return;
Tc* tc = tc_insts[index];
if (!tc->COUNT16.INTFLAG.bit.MC0) return;
if (index != pulseout_tc_index) {
return;
}
Tc *tc = tc_insts[index];
if (!tc->COUNT16.INTFLAG.bit.MC0) {
return;
}
pulse_finish();
@ -93,16 +97,16 @@ void pulseout_reset() {
refcount = 0;
pulseout_tc_index = 0xff;
active_pincfg = NULL;
#ifdef SAMD21
#ifdef SAMD21
rtc_end_pulse();
#endif
#endif
}
void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self,
const pwmio_pwmout_obj_t* carrier,
const mcu_pin_obj_t* pin,
uint32_t frequency,
uint16_t duty_cycle) {
void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t *self,
const pwmio_pwmout_obj_t *carrier,
const mcu_pin_obj_t *pin,
uint32_t frequency,
uint16_t duty_cycle) {
if (!carrier || pin || frequency) {
mp_raise_NotImplementedError(translate("Port does not accept pins or frequency. Construct and pass a PWMOut Carrier instead"));
}
@ -136,8 +140,8 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self,
#ifdef SAMD21
tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 |
TC_CTRLA_PRESCALER_DIV64 |
TC_CTRLA_WAVEGEN_NFRQ;
TC_CTRLA_PRESCALER_DIV64 |
TC_CTRLA_WAVEGEN_NFRQ;
#endif
#ifdef SAM_D5X_E5X
tc_reset(tc);
@ -162,17 +166,17 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self,
// Turn off the pinmux which should connect the port output.
turn_off(self->pincfg);
#ifdef SAMD21
#ifdef SAMD21
rtc_start_pulse();
#endif
#endif
}
bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t* self) {
bool common_hal_pulseio_pulseout_deinited(pulseio_pulseout_obj_t *self) {
return self->pin == NO_PIN;
}
void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) {
void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t *self) {
if (common_hal_pulseio_pulseout_deinited(self)) {
return;
}
@ -187,12 +191,12 @@ void common_hal_pulseio_pulseout_deinit(pulseio_pulseout_obj_t* self) {
pulseout_tc_index = 0xff;
}
self->pin = NO_PIN;
#ifdef SAMD21
#ifdef SAMD21
rtc_end_pulse();
#endif
#endif
}
void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pulses, uint16_t length) {
void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t *self, uint16_t *pulses, uint16_t length) {
if (active_pincfg != NULL) {
mp_raise_RuntimeError(translate("Another send is already active"));
}
@ -202,7 +206,7 @@ void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pu
pulse_length = length;
current_compare = pulses[0] * 3 / 4;
Tc* tc = tc_insts[pulseout_tc_index];
Tc *tc = tc_insts[pulseout_tc_index];
tc->COUNT16.CC[0].reg = current_compare;
// Clear our interrupt in case it was set earlier
@ -212,7 +216,7 @@ void common_hal_pulseio_pulseout_send(pulseio_pulseout_obj_t* self, uint16_t* pu
turn_on(active_pincfg);
tc->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
while(pulse_index < length) {
while (pulse_index < length) {
// Do other things while we wait. The interrupts will handle sending the
// signal.
RUN_BACKGROUND_TASKS;

109
ports/atmel-samd/common-hal/pwmio/PWMOut.c
View File

@ -42,8 +42,8 @@
#undef ENABLE
# define _TCC_SIZE(unused, n) TCC ## n ## _SIZE,
# define TCC_SIZES { REPEAT_MACRO(_TCC_SIZE, 0, TCC_INST_NUM) }
#define _TCC_SIZE(unused, n) TCC##n##_SIZE,
#define TCC_SIZES { REPEAT_MACRO(_TCC_SIZE, 0, TCC_INST_NUM) }
static const uint8_t tcc_sizes[TCC_INST_NUM] = TCC_SIZES;
static uint32_t tcc_periods[TCC_INST_NUM];
@ -126,38 +126,38 @@ void pwmout_reset(void) {
}
}
static uint8_t tcc_channel(const pin_timer_t* t) {
static uint8_t tcc_channel(const pin_timer_t *t) {
// For the SAMD51 this hardcodes the use of OTMX == 0x0, the output matrix mapping, which uses
// SAMD21-style modulo mapping.
return t->wave_output % tcc_cc_num[t->index];
}
bool channel_ok(const pin_timer_t* t) {
bool channel_ok(const pin_timer_t *t) {
uint8_t channel_bit = 1 << tcc_channel(t);
return (!t->is_tc && ((tcc_channels[t->index] & channel_bit) == 0)) ||
t->is_tc;
t->is_tc;
}
pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
const mcu_pin_obj_t* pin,
uint16_t duty,
uint32_t frequency,
bool variable_frequency) {
pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self,
const mcu_pin_obj_t *pin,
uint16_t duty,
uint32_t frequency,
bool variable_frequency) {
self->pin = pin;
self->variable_frequency = variable_frequency;
self->duty_cycle = duty;
if (pin->timer[0].index >= TC_INST_NUM &&
pin->timer[1].index >= TCC_INST_NUM
#ifdef SAM_D5X_E5X
#ifdef SAM_D5X_E5X
&& pin->timer[2].index >= TCC_INST_NUM
#endif
#endif
) {
return PWMOUT_INVALID_PIN;
}
uint32_t system_clock = common_hal_mcu_processor_get_frequency();
if (frequency == 0 || frequency > system_clock/2) {
if (frequency == 0 || frequency > system_clock / 2) {
return PWMOUT_INVALID_FREQUENCY;
}
@ -165,7 +165,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
// First see if a tcc is already going with the frequency we want and our
// channel is unused. tc's don't have enough channels to share.
const pin_timer_t* timer = NULL;
const pin_timer_t *timer = NULL;
uint8_t mux_position = 0;
if (!variable_frequency) {
for (uint8_t i = 0; i < TCC_INST_NUM && timer == NULL; i++) {
@ -173,11 +173,11 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
continue;
}
for (uint8_t j = 0; j < NUM_TIMERS_PER_PIN && timer == NULL; j++) {
const pin_timer_t* t = &pin->timer[j];
const pin_timer_t *t = &pin->timer[j];
if (t->index != i || t->is_tc || t->index >= TCC_INST_NUM) {
continue;
}
Tcc* tcc = tcc_insts[t->index];
Tcc *tcc = tcc_insts[t->index];
if (tcc->CTRLA.bit.ENABLE == 1 && channel_ok(t)) {
timer = t;
mux_position = j;
@ -202,20 +202,20 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
start = 0;
}
for (int8_t i = start; i >= 0 && i < NUM_TIMERS_PER_PIN && timer == NULL; i += direction) {
const pin_timer_t* t = &pin->timer[i];
const pin_timer_t *t = &pin->timer[i];
if ((!t->is_tc && t->index >= TCC_INST_NUM) ||
(t->is_tc && t->index >= TC_INST_NUM)) {
continue;
}
if (t->is_tc) {
found = true;
Tc* tc = tc_insts[t->index];
Tc *tc = tc_insts[t->index];
if (tc->COUNT16.CTRLA.bit.ENABLE == 0 && t->wave_output == 1) {
timer = t;
mux_position = i;
}
} else {
Tcc* tcc = tcc_insts[t->index];
Tcc *tcc = tcc_insts[t->index];
if (tcc->CTRLA.bit.ENABLE == 0 && channel_ok(t)) {
timer = t;
mux_position = i;
@ -253,11 +253,11 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
if (timer->is_tc) {
tc_periods[timer->index] = top;
Tc* tc = tc_insts[timer->index];
Tc *tc = tc_insts[timer->index];
#ifdef SAMD21
tc->COUNT16.CTRLA.reg = TC_CTRLA_MODE_COUNT16 |
TC_CTRLA_PRESCALER(divisor) |
TC_CTRLA_WAVEGEN_MPWM;
TC_CTRLA_PRESCALER(divisor) |
TC_CTRLA_WAVEGEN_MPWM;
tc->COUNT16.CC[0].reg = top;
#endif
#ifdef SAM_D5X_E5X
@ -275,7 +275,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
tc_set_enable(tc, true);
} else {
tcc_periods[timer->index] = top;
Tcc* tcc = tcc_insts[timer->index];
Tcc *tcc = tcc_insts[timer->index];
tcc_set_enable(tcc, false);
tcc->CTRLA.bit.PRESCALER = divisor;
tcc->PER.bit.PER = top;
@ -300,17 +300,17 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t* self,
return PWMOUT_OK;
}
bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t* self) {
bool common_hal_pwmio_pwmout_deinited(pwmio_pwmout_obj_t *self) {
return self->pin == NULL;
}
void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) {
void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t *self) {
if (common_hal_pwmio_pwmout_deinited(self)) {
return;
}
const pin_timer_t* t = self->timer;
const pin_timer_t *t = self->timer;
if (t->is_tc) {
Tc* tc = tc_insts[t->index];
Tc *tc = tc_insts[t->index];
tc_set_enable(tc, false);
tc->COUNT16.CTRLA.bit.SWRST = true;
tc_wait_for_sync(tc);
@ -319,7 +319,7 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) {
tcc_channels[t->index] &= ~(1 << tcc_channel(t));
if (tcc_refcount[t->index] == 0) {
target_tcc_frequencies[t->index] = 0;
Tcc* tcc = tcc_insts[t->index];
Tcc *tcc = tcc_insts[t->index];
tcc_set_enable(tcc, false);
tcc->CTRLA.bit.SWRST = true;
while (tcc->SYNCBUSY.bit.SWRST != 0) {
@ -331,7 +331,7 @@ void common_hal_pwmio_pwmout_deinit(pwmio_pwmout_obj_t* self) {
self->pin = NULL;
}
extern void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t* self, uint16_t duty) {
extern void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t duty) {
// Store the unadjusted duty cycle. It turns out the the process of adjusting and calculating
// the duty cycle here and reading it back is lossy - the value will decay over time.
// Track it here so that if frequency is changed we can use this value to recalculate the
@ -339,27 +339,29 @@ extern void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t* self, uin
// See https://github.com/adafruit/circuitpython/issues/2086 for more details
self->duty_cycle = duty;
const pin_timer_t* t = self->timer;
const pin_timer_t *t = self->timer;
if (t->is_tc) {
uint16_t adjusted_duty = tc_periods[t->index] * duty / 0xffff;
#ifdef SAMD21
tc_insts[t->index]->COUNT16.CC[t->wave_output].reg = adjusted_duty;
#endif
#ifdef SAM_D5X_E5X
Tc* tc = tc_insts[t->index];
while (tc->COUNT16.SYNCBUSY.bit.CC1 != 0) {}
Tc *tc = tc_insts[t->index];
while (tc->COUNT16.SYNCBUSY.bit.CC1 != 0) {
}
tc->COUNT16.CCBUF[1].reg = adjusted_duty;
#endif
} else {
uint32_t adjusted_duty = ((uint64_t) tcc_periods[t->index]) * duty / 0xffff;
uint32_t adjusted_duty = ((uint64_t)tcc_periods[t->index]) * duty / 0xffff;
uint8_t channel = tcc_channel(t);
Tcc* tcc = tcc_insts[t->index];
Tcc *tcc = tcc_insts[t->index];
// Write into the CC buffer register, which will be transferred to the
// CC register on an UPDATE (when period is finished).
// Do clock domain syncing as necessary.
while (tcc->SYNCBUSY.reg != 0) {}
while (tcc->SYNCBUSY.reg != 0) {
}
// Lock out double-buffering while updating the CCB value.
tcc->CTRLBSET.bit.LUPD = 1;
@ -373,19 +375,20 @@ extern void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t* self, uin
}
}
uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) {
const pin_timer_t* t = self->timer;
uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) {
const pin_timer_t *t = self->timer;
if (t->is_tc) {
Tc* tc = tc_insts[t->index];
Tc *tc = tc_insts[t->index];
tc_wait_for_sync(tc);
uint16_t cv = tc->COUNT16.CC[t->wave_output].reg;
return cv * 0xffff / tc_periods[t->index];
} else {
Tcc* tcc = tcc_insts[t->index];
Tcc *tcc = tcc_insts[t->index];
uint8_t channel = tcc_channel(t);
uint32_t cv = 0;
while (tcc->SYNCBUSY.bit.CTRLB) {}
while (tcc->SYNCBUSY.bit.CTRLB) {
}
#ifdef SAMD21
// If CCBV (CCB valid) is set, the CCB value hasn't yet been copied
@ -404,20 +407,20 @@ uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t* self) {
}
#endif
uint32_t duty_cycle = ((uint64_t) cv) * 0xffff / tcc_periods[t->index];
uint32_t duty_cycle = ((uint64_t)cv) * 0xffff / tcc_periods[t->index];
return duty_cycle;
}
}
void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self,
uint32_t frequency) {
void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self,
uint32_t frequency) {
uint32_t system_clock = common_hal_mcu_processor_get_frequency();
if (frequency == 0 || frequency > system_clock/2) {
if (frequency == 0 || frequency > system_clock / 2) {
mp_raise_ValueError(translate("Invalid PWM frequency"));
}
const pin_timer_t* t = self->timer;
const pin_timer_t *t = self->timer;
uint8_t resolution;
if (t->is_tc) {
resolution = 16;
@ -434,7 +437,7 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self,
}
}
if (t->is_tc) {
Tc* tc = tc_insts[t->index];
Tc *tc = tc_insts[t->index];
uint8_t old_divisor = tc->COUNT16.CTRLA.bit.PRESCALER;
if (new_divisor != old_divisor) {
tc_set_enable(tc, false);
@ -446,18 +449,20 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self,
tc->COUNT16.CC[0].reg = new_top;
#endif
#ifdef SAM_D5X_E5X
while (tc->COUNT16.SYNCBUSY.reg != 0) {}
while (tc->COUNT16.SYNCBUSY.reg != 0) {
}
tc->COUNT16.CCBUF[0].reg = new_top;
#endif
} else {
Tcc* tcc = tcc_insts[t->index];
Tcc *tcc = tcc_insts[t->index];
uint8_t old_divisor = tcc->CTRLA.bit.PRESCALER;
if (new_divisor != old_divisor) {
tcc_set_enable(tcc, false);
tcc->CTRLA.bit.PRESCALER = new_divisor;
tcc_set_enable(tcc, true);
}
while (tcc->SYNCBUSY.reg != 0) {}
while (tcc->SYNCBUSY.reg != 0) {
}
tcc_periods[t->index] = new_top;
#ifdef SAMD21
tcc->PERB.bit.PERB = new_top;
@ -470,9 +475,9 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t* self,
common_hal_pwmio_pwmout_set_duty_cycle(self, self->duty_cycle);
}
uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) {
uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) {
uint32_t system_clock = common_hal_mcu_processor_get_frequency();
const pin_timer_t* t = self->timer;
const pin_timer_t *t = self->timer;
uint8_t divisor;
uint32_t top;
if (t->is_tc) {
@ -485,6 +490,6 @@ uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t* self) {
return (system_clock / prescaler[divisor]) / (top + 1);
}
bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t* self) {
bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) {
return self->variable_frequency;
}

2
ports/atmel-samd/common-hal/pwmio/PWMOut.h
View File

@ -34,7 +34,7 @@
typedef struct {
mp_obj_base_t base;
const mcu_pin_obj_t *pin;
const pin_timer_t* timer;
const pin_timer_t *timer;
bool variable_frequency;
uint16_t duty_cycle;
} pwmio_pwmout_obj_t;

8
ports/atmel-samd/common-hal/rgbmatrix/RGBMatrix.c
View File

@ -40,7 +40,7 @@ void *common_hal_rgbmatrix_timer_allocate(rgbmatrix_rgbmatrix_obj_t *self) {
return tc_insts[timer_index];
}
static uint8_t tc_index_from_ptr(void* ptr) {
static uint8_t tc_index_from_ptr(void *ptr) {
for (uint8_t i = TC_INST_NUM; i > 0; i--) {
if (tc_insts[i] == ptr) {
return i;
@ -49,7 +49,7 @@ static uint8_t tc_index_from_ptr(void* ptr) {
return 0xff;
}
void common_hal_rgbmatrix_timer_enable(void* ptr) {
void common_hal_rgbmatrix_timer_enable(void *ptr) {
uint8_t timer_index = tc_index_from_ptr(ptr);
if (timer_index == 0xff) {
return;
@ -58,7 +58,7 @@ void common_hal_rgbmatrix_timer_enable(void* ptr) {
turn_on_clocks(true, timer_index, 1);
}
void common_hal_rgbmatrix_timer_disable(void* ptr) {
void common_hal_rgbmatrix_timer_disable(void *ptr) {
uint8_t timer_index = tc_index_from_ptr(ptr);
if (timer_index == 0xff) {
return;
@ -67,7 +67,7 @@ void common_hal_rgbmatrix_timer_disable(void* ptr) {
tc_set_enable(ptr, false);
}
void common_hal_rgbmatrix_timer_free(void* ptr) {
void common_hal_rgbmatrix_timer_free(void *ptr) {
uint8_t timer_index = tc_index_from_ptr(ptr);
if (timer_index == 0xff) {
return;

6
ports/atmel-samd/common-hal/rgbmatrix/RGBMatrix.h
View File

@ -30,8 +30,8 @@
#include "shared-module/rgbmatrix/RGBMatrix.h"
void *common_hal_rgbmatrix_timer_allocate(rgbmatrix_rgbmatrix_obj_t *self);
void common_hal_rgbmatrix_timer_enable(void*);
void common_hal_rgbmatrix_timer_disable(void*);
void common_hal_rgbmatrix_timer_free(void*);
void common_hal_rgbmatrix_timer_enable(void *);
void common_hal_rgbmatrix_timer_disable(void *);
void common_hal_rgbmatrix_timer_free(void *);
#endif

22
ports/atmel-samd/common-hal/rotaryio/IncrementalEncoder.c
View File

@ -34,8 +34,8 @@
#include "py/runtime.h"
#include "supervisor/shared/translate.h"
void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencoder_obj_t* self,
const mcu_pin_obj_t* pin_a, const mcu_pin_obj_t* pin_b) {
void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencoder_obj_t *self,
const mcu_pin_obj_t *pin_a, const mcu_pin_obj_t *pin_b) {
if (!pin_a->has_extint || !pin_b->has_extint) {
mp_raise_RuntimeError(translate("Both pins must support hardware interrupts"));
}
@ -63,15 +63,15 @@ void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencode
gpio_set_pin_function(self->pin_b, GPIO_PIN_FUNCTION_A);
gpio_set_pin_pull_mode(self->pin_b, GPIO_PULL_UP);
set_eic_channel_data(self->eic_channel_a, (void*) self);
set_eic_channel_data(self->eic_channel_b, (void*) self);
set_eic_channel_data(self->eic_channel_a, (void *)self);
set_eic_channel_data(self->eic_channel_b, (void *)self);
self->position = 0;
self->quarter_count = 0;
shared_module_softencoder_state_init(self,
((uint8_t) gpio_get_pin_level(self->pin_a) << 1) |
(uint8_t) gpio_get_pin_level(self->pin_b));
((uint8_t)gpio_get_pin_level(self->pin_a) << 1) |
(uint8_t)gpio_get_pin_level(self->pin_b));
claim_pin(pin_a);
claim_pin(pin_b);
@ -83,11 +83,11 @@ void common_hal_rotaryio_incrementalencoder_construct(rotaryio_incrementalencode
turn_on_eic_channel(self->eic_channel_b, EIC_CONFIG_SENSE0_BOTH_Val);
}
bool common_hal_rotaryio_incrementalencoder_deinited(rotaryio_incrementalencoder_obj_t* self) {
bool common_hal_rotaryio_incrementalencoder_deinited(rotaryio_incrementalencoder_obj_t *self) {
return self->pin_a == NO_PIN;
}
void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_obj_t* self) {
void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_obj_t *self) {
if (common_hal_rotaryio_incrementalencoder_deinited(self)) {
return;
}
@ -106,11 +106,11 @@ void common_hal_rotaryio_incrementalencoder_deinit(rotaryio_incrementalencoder_o
}
void incrementalencoder_interrupt_handler(uint8_t channel) {
rotaryio_incrementalencoder_obj_t* self = get_eic_channel_data(channel);
rotaryio_incrementalencoder_obj_t *self = get_eic_channel_data(channel);
uint8_t new_state =
((uint8_t) gpio_get_pin_level(self->pin_a) << 1) |
(uint8_t) gpio_get_pin_level(self->pin_b);
((uint8_t)gpio_get_pin_level(self->pin_a) << 1) |
(uint8_t)gpio_get_pin_level(self->pin_b);
shared_module_softencoder_state_update(self, new_state);
}

8
ports/atmel-samd/common-hal/rtc/RTC.c
View File

@ -51,7 +51,7 @@ void common_hal_rtc_set_time(timeutils_struct_time_t *tm) {
uint64_t ticks_s = port_get_raw_ticks(NULL) / 1024;
uint32_t epoch_s = timeutils_seconds_since_2000(
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec
);
);
rtc_offset = epoch_s - ticks_s;
}
@ -68,11 +68,11 @@ int common_hal_rtc_get_calibration(void) {
void common_hal_rtc_set_calibration(int calibration) {
if (calibration > 127 || calibration < -127) {
#if CIRCUITPY_FULL_BUILD
#if CIRCUITPY_FULL_BUILD
mp_raise_ValueError(translate("calibration value out of range +/-127"));
#else
#else
mp_raise_ValueError(translate("calibration is out of range"));
#endif
#endif
}
hri_rtcmode0_write_FREQCORR_SIGN_bit(RTC, calibration < 0 ? 0 : 1);

24
ports/atmel-samd/common-hal/sdioio/SDCard.c
View File

@ -58,8 +58,8 @@
static Sdhc *sdhc_insts[] = SDHC_INSTS;
void common_hal_sdioio_sdcard_construct(sdioio_sdcard_obj_t *self,
const mcu_pin_obj_t * clock, const mcu_pin_obj_t * command,
uint8_t num_data, mcu_pin_obj_t ** data, uint32_t frequency) {
const mcu_pin_obj_t *clock, const mcu_pin_obj_t *command,
uint8_t num_data, mcu_pin_obj_t **data, uint32_t frequency) {
/*
SD breakout as assembled ("*" = minimum viable set)
@ -84,7 +84,7 @@ CLK PA21 PCC_D? (D32) BROWN
int instance = functions[0]->instance;
functions[1] = mcu_find_pin_function(sdio_ck, clock, instance, MP_QSTR_clock);
functions[2] = mcu_find_pin_function(sdio_dat0, data[0], instance, MP_QSTR_data0);
if(num_data == 4) {
if (num_data == 4) {
functions[3] = mcu_find_pin_function(sdio_dat1, data[1], instance, MP_QSTR_data1);
functions[4] = mcu_find_pin_function(sdio_dat2, data[2], instance, MP_QSTR_data2);
functions[5] = mcu_find_pin_function(sdio_dat3, data[3], instance, MP_QSTR_data3);
@ -94,8 +94,8 @@ CLK PA21 PCC_D? (D32) BROWN
self->command_pin = common_hal_mcu_pin_number(functions[0]->obj);
self->clock_pin = common_hal_mcu_pin_number(functions[1]->obj);
for(int i=0; i<num_data; i++) {
mcu_pin_function_t *function = functions[2+i];
for (int i = 0; i < num_data; i++) {
mcu_pin_function_t *function = functions[2 + i];
if (function) {
self->data_pins[i] = common_hal_mcu_pin_number(function->obj);
} else {
@ -103,7 +103,7 @@ CLK PA21 PCC_D? (D32) BROWN
}
}
for(size_t i=0; i<MP_ARRAY_SIZE(functions); i++) {
for (size_t i = 0; i < MP_ARRAY_SIZE(functions); i++) {
if (!functions[i]->obj) {
break;
}
@ -121,16 +121,16 @@ CLK PA21 PCC_D? (D32) BROWN
self->num_data = num_data;
self->frequency = frequency;
if(instance == 0) {
if (instance == 0) {
hri_mclk_set_AHBMASK_SDHC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID, CONF_GCLK_SDHC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SDHC0_GCLK_ID_SLOW, CONF_GCLK_SDHC0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
#ifdef SDHC1_GCLK_ID
#ifdef SDHC1_GCLK_ID
} else {
hri_mclk_set_AHBMASK_SDHC1_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID, CONF_GCLK_SDHC1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SDHC1_GCLK_ID_SLOW, CONF_GCLK_SDHC1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
#endif
#endif
}
DEBUG_PRINT("instance %d @%p\n", instance, sdhc_insts[instance]);
@ -139,7 +139,7 @@ CLK PA21 PCC_D? (D32) BROWN
sd_mmc_err_t result = SD_MMC_INIT_ONGOING;
for (int i=0; result == SD_MMC_INIT_ONGOING && i<100; i++) {
for (int i = 0; result == SD_MMC_INIT_ONGOING && i < 100; i++) {
result = sd_mmc_check(0);
DEBUG_PRINT("sd_mmc_check(0) -> %d\n", result);
}
@ -182,9 +182,9 @@ STATIC void wait_write_complete(sdioio_sdcard_obj_t *self) {
}
STATIC void debug_print_state(sdioio_sdcard_obj_t *self, const char *what, sd_mmc_err_t r) {
#if DEBUG_SDIO
#if DEBUG_SDIO
DEBUG_PRINT("%s: %d\n", what, r);
#endif
#endif
}
int common_hal_sdioio_sdcard_writeblocks(sdioio_sdcard_obj_t *self, uint32_t start_block, mp_buffer_info_t *bufinfo) {

2
ports/atmel-samd/common-hal/sdioio/SDCard.h
View File

@ -33,7 +33,7 @@ typedef struct {
struct mci_sync_desc IO_BUS;
uint32_t frequency;
uint32_t capacity;
uint8_t num_data:3, state_programming:1, has_lock:1;
uint8_t num_data : 3, state_programming : 1, has_lock : 1;
uint8_t command_pin;
uint8_t clock_pin;
uint8_t data_pins[4];

4
ports/atmel-samd/common-hal/supervisor/Runtime.c Executable file → Normal file
View File

@ -29,9 +29,9 @@
#include "supervisor/serial.h"
bool common_hal_supervisor_runtime_get_serial_connected(void) {
return (bool) serial_connected();
return (bool)serial_connected();
}
bool common_hal_supervisor_runtime_get_serial_bytes_available(void) {
return (bool) serial_bytes_available();
return (bool)serial_bytes_available();
}

18
ports/atmel-samd/common-hal/touchio/TouchIn.c
View File

@ -57,15 +57,15 @@ static uint16_t get_raw_reading(touchio_touchin_obj_t *self) {
return adafruit_ptc_get_conversion_result(PTC);
}
void common_hal_touchio_touchin_construct(touchio_touchin_obj_t* self,
const mcu_pin_obj_t *pin) {
void common_hal_touchio_touchin_construct(touchio_touchin_obj_t *self,
const mcu_pin_obj_t *pin) {
if (!pin->has_touch) {
mp_raise_ValueError(translate("Invalid pin"));
}
claim_pin(pin);
// Turn on the PTC if its not in use. We won't turn it off until reset.
if ((( Ptc *) PTC)->CTRLA.bit.ENABLE == 0) {
if (((Ptc *)PTC)->CTRLA.bit.ENABLE == 0) {
// We run the PTC at 8mhz so divide the 48mhz clock by 6.
uint8_t gclk = find_free_gclk(6);
if (gclk > GCLK_GEN_NUM) {
@ -95,11 +95,11 @@ void common_hal_touchio_touchin_construct(touchio_touchin_obj_t* self,
self->threshold = get_raw_reading(self) + 100;
}
bool common_hal_touchio_touchin_deinited(touchio_touchin_obj_t* self) {
bool common_hal_touchio_touchin_deinited(touchio_touchin_obj_t *self) {
return self->config.pin == NO_PIN;
}
void common_hal_touchio_touchin_deinit(touchio_touchin_obj_t* self) {
void common_hal_touchio_touchin_deinit(touchio_touchin_obj_t *self) {
// TODO(tannewt): Reset the PTC.
if (common_hal_touchio_touchin_deinited(self)) {
return;
@ -111,13 +111,15 @@ void common_hal_touchio_touchin_deinit(touchio_touchin_obj_t* self) {
}
void touchin_reset() {
Ptc* ptc = ((Ptc *) PTC);
Ptc *ptc = ((Ptc *)PTC);
if (ptc->CTRLA.bit.ENABLE == 1) {
ptc->CTRLA.bit.ENABLE = 0;
while (ptc->CTRLA.bit.ENABLE == 1) {}
while (ptc->CTRLA.bit.ENABLE == 1) {
}
ptc->CTRLA.bit.SWRESET = 1;
while (ptc->CTRLA.bit.SWRESET == 1) {}
while (ptc->CTRLA.bit.SWRESET == 1) {
}
}
}

2109
ports/atmel-samd/sd_mmc/sd_mmc.c
View File

File diff suppressed because it is too large Load Diff

8
ports/atmel-samd/sd_mmc/sd_mmc.h
View File

@ -104,8 +104,8 @@ typedef uint8_t card_version_t; /**< Type of card version */
/** Card detect setting */
typedef struct sd_mmc_detect {
int16_t pin; /**< Detection pin, -1 if no such pin */
uint16_t val; /**< Detection value */
int16_t pin; /**< Detection pin, -1 if no such pin */
uint16_t val; /**< Detection value */
} sd_mmc_detect_t;
/** This SD MMC stack uses the maximum block size autorized (512 bytes) */
@ -281,7 +281,7 @@ sd_mmc_err_t sdio_write_direct(uint8_t slot, uint8_t func_num, uint32_t addr, ui
* otherwise return an error code (\ref sd_mmc_err_t).
*/
sd_mmc_err_t sdio_read_extended(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t inc_addr, uint8_t *dest,
uint16_t size);
uint16_t size);
/**
* \brief Write bytes to SDIO using RW_EXTENDED command.
@ -298,7 +298,7 @@ sd_mmc_err_t sdio_read_extended(uint8_t slot, uint8_t func_num, uint32_t addr, u
* otherwise return an error code (\ref sd_mmc_err_t).
*/
sd_mmc_err_t sdio_write_extended(uint8_t slot, uint8_t func_num, uint32_t addr, uint8_t inc_addr, uint8_t *src,
uint16_t size);
uint16_t size);
#endif /* SDIO_SUPPORT_ENABLE */
/** @} */

337
ports/atmel-samd/sd_mmc/sd_mmc_protocol.h
View File

@ -97,43 +97,43 @@ extern "C" {
* @{
*/
//! Value to define a SD/MMC/SDIO command
// ! Value to define a SD/MMC/SDIO command
typedef uint32_t sdmmc_cmd_def_t;
//! \name Flags used to define a SD/MMC/SDIO command
//! @{
// ! \name Flags used to define a SD/MMC/SDIO command
// ! @{
#define SDMMC_CMD_GET_INDEX(cmd) (cmd & 0x3F)
//! Have response (MCI only)
// ! Have response (MCI only)
#define SDMMC_RESP_PRESENT (1lu << 8)
//! 8 bit response (SPI only)
// ! 8 bit response (SPI only)
#define SDMMC_RESP_8 (1lu << 9)
//! 32 bit response (SPI only)
// ! 32 bit response (SPI only)
#define SDMMC_RESP_32 (1lu << 10)
//! 136 bit response (MCI only)
// ! 136 bit response (MCI only)
#define SDMMC_RESP_136 (1lu << 11)
//! Expect valid crc (MCI only)
// ! Expect valid crc (MCI only)
#define SDMMC_RESP_CRC (1lu << 12)
//! Card may send busy
// ! Card may send busy
#define SDMMC_RESP_BUSY (1lu << 13)
// Open drain for a braodcast command (bc)
// or to enter in inactive state (MCI only)
#define SDMMC_CMD_OPENDRAIN (1lu << 14)
//! To signal a data write operation
// ! To signal a data write operation
#define SDMMC_CMD_WRITE (1lu << 15)
//! To signal a SDIO tranfer in multi byte mode
// ! To signal a SDIO tranfer in multi byte mode
#define SDMMC_CMD_SDIO_BYTE (1lu << 16)
//! To signal a SDIO tranfer in block mode
// ! To signal a SDIO tranfer in block mode
#define SDMMC_CMD_SDIO_BLOCK (1lu << 17)
//! To signal a data transfer in stream mode
// ! To signal a data transfer in stream mode
#define SDMMC_CMD_STREAM (1lu << 18)
//! To signal a data transfer in single block mode
// ! To signal a data transfer in single block mode
#define SDMMC_CMD_SINGLE_BLOCK (1lu << 19)
//! To signal a data transfer in multi block mode
// ! To signal a data transfer in multi block mode
#define SDMMC_CMD_MULTI_BLOCK (1lu << 20)
//! @}
// ! @}
//! \name Set of flags to define a reponse type
//! @{
// ! \name Set of flags to define a reponse type
// ! @{
#define SDMMC_CMD_NO_RESP (0)
#define SDMMC_CMD_R1 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
#define SDMMC_CMD_R1B (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC | SDMMC_RESP_BUSY)
@ -143,14 +143,14 @@ typedef uint32_t sdmmc_cmd_def_t;
#define SDMMC_CMD_R5 (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_CRC)
#define SDMMC_CMD_R6 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
#define SDMMC_CMD_R7 (SDMMC_RESP_PRESENT | SDMMC_RESP_32 | SDMMC_RESP_CRC)
//! @}
// ! @}
//! \name SD/MMC/SDIO command definitions
//! SDMMC_CMDx are include in SD and MMC norms
//! MMC_CMDx are include in MMC norms only
//! SD_CMDx are include in SD norms only
//! SDIO_CMDx are include in SDIO norms only
//! @{
// ! \name SD/MMC/SDIO command definitions
// ! SDMMC_CMDx are include in SD and MMC norms
// ! MMC_CMDx are include in MMC norms only
// ! SD_CMDx are include in SD norms only
// ! SDIO_CMDx are include in SDIO norms only
// ! @{
/*
* --- Basic commands and read-stream command (class 0 and class 1) ---
@ -351,21 +351,21 @@ typedef uint32_t sdmmc_cmd_def_t;
#define SDIO_CMD53_IO_W_BYTE_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE | SDMMC_CMD_WRITE)
#define SDIO_CMD53_IO_R_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK)
#define SDIO_CMD53_IO_W_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK | SDMMC_CMD_WRITE)
//! @}
//! @}
// ! @}
// ! @}
//! \name Macros for command argument definition
//! @{
// ! \name Macros for command argument definition
// ! @{
//! \name MMC CMD6 argument structure
//! @{
//! [31:26] Set to 0
//! [25:24] Access
// ! \name MMC CMD6 argument structure
// ! @{
// ! [31:26] Set to 0
// ! [25:24] Access
#define MMC_CMD6_ACCESS_COMMAND_SET (0lu << 24)
#define MMC_CMD6_ACCESS_SET_BITS (1lu << 24)
#define MMC_CMD6_ACCESS_CLEAR_BITS (2lu << 24)
#define MMC_CMD6_ACCESS_WRITE_BYTE (3lu << 24)
//! [23:16] Index for Mode Segment
// ! [23:16] Index for Mode Segment
#define MMC_CMD6_INDEX_CMD_SET (EXT_CSD_CMD_SET_INDEX << 16)
#define MMC_CMD6_INDEX_CMD_SET_REV (EXT_CSD_CMD_SET_REV_INDEX << 16)
#define MMC_CMD6_INDEX_POWER_CLASS (EXT_CSD_POWER_CLASS_INDEX << 16)
@ -375,61 +375,61 @@ typedef uint32_t sdmmc_cmd_def_t;
#define MMC_CMD6_INDEX_BOOT_CONFIG (EXT_CSD_BOOT_CONFIG_INDEX << 16)
#define MMC_CMD6_INDEX_BOOT_BUS_WIDTH (EXT_CSD_BOOT_BUS_WIDTH_INDEX << 16)
#define MMC_CMD6_INDEX_ERASE_GROUP_DEF (EXT_CSD_ERASE_GROUP_DEF_INDEX << 16)
//! [15:8] Value
// ! [15:8] Value
#define MMC_CMD6_VALUE_BUS_WIDTH_1BIT (0x0lu << 8)
#define MMC_CMD6_VALUE_BUS_WIDTH_4BIT (0x1lu << 8)
#define MMC_CMD6_VALUE_BUS_WIDTH_8BIT (0x2lu << 8)
#define MMC_CMD6_VALUE_HS_TIMING_ENABLE (0x1lu << 8)
#define MMC_CMD6_VALUE_HS_TIMING_DISABLE (0x0lu << 8)
//! [7:3] Set to 0
//! [2:0] Cmd Set
//! @}
// ! [7:3] Set to 0
// ! [2:0] Cmd Set
// ! @}
//! \name SD CMD6 argument structure
//! @{
//! CMD6 arg[ 3: 0] function group 1, access mode
// ! \name SD CMD6 argument structure
// ! @{
// ! CMD6 arg[ 3: 0] function group 1, access mode
#define SD_CMD6_GRP1_HIGH_SPEED (0x1lu << 0)
#define SD_CMD6_GRP1_DEFAULT (0x0lu << 0)
//! CMD6 arg[ 7: 4] function group 2, command system
// ! CMD6 arg[ 7: 4] function group 2, command system
#define SD_CMD6_GRP2_NO_INFLUENCE (0xFlu << 4)
#define SD_CMD6_GRP2_DEFAULT (0x0lu << 4)
//! CMD6 arg[11: 8] function group 3, 0xF or 0x0
// ! CMD6 arg[11: 8] function group 3, 0xF or 0x0
#define SD_CMD6_GRP3_NO_INFLUENCE (0xFlu << 8)
#define SD_CMD6_GRP3_DEFAULT (0x0lu << 8)
//! CMD6 arg[15:12] function group 4, 0xF or 0x0
// ! CMD6 arg[15:12] function group 4, 0xF or 0x0
#define SD_CMD6_GRP4_NO_INFLUENCE (0xFlu << 12)
#define SD_CMD6_GRP4_DEFAULT (0x0lu << 12)
//! CMD6 arg[19:16] function group 5, 0xF or 0x0
// ! CMD6 arg[19:16] function group 5, 0xF or 0x0
#define SD_CMD6_GRP5_NO_INFLUENCE (0xFlu << 16)
#define SD_CMD6_GRP5_DEFAULT (0x0lu << 16)
//! CMD6 arg[23:20] function group 6, 0xF or 0x0
// ! CMD6 arg[23:20] function group 6, 0xF or 0x0
#define SD_CMD6_GRP6_NO_INFLUENCE (0xFlu << 20)
#define SD_CMD6_GRP6_DEFAULT (0x0lu << 20)
//! CMD6 arg[30:24] reserved 0
//! CMD6 arg[31 ] Mode, 0: Check, 1: Switch
// ! CMD6 arg[30:24] reserved 0
// ! CMD6 arg[31 ] Mode, 0: Check, 1: Switch
#define SD_CMD6_MODE_CHECK (0lu << 31)
#define SD_CMD6_MODE_SWITCH (1lu << 31)
//! @}
// ! @}
//! \name SD CMD8 argument structure
//! @{
// ! \name SD CMD8 argument structure
// ! @{
#define SD_CMD8_PATTERN 0xAA
#define SD_CMD8_MASK_PATTERN 0xFF
#define SD_CMD8_HIGH_VOLTAGE 0x100
#define SD_CMD8_MASK_VOLTAGE 0xF00
//! @}
// ! @}
//! \name SD ACMD41 arguments
//! @{
#define SD_ACMD41_HCS (1lu << 30) //!< (SD) Host Capacity Support
//! @}
//! @}
// ! \name SD ACMD41 arguments
// ! @{
#define SD_ACMD41_HCS (1lu << 30) // !< (SD) Host Capacity Support
// ! @}
// ! @}
//! \name SDIO definitions
//! @{
// ! \name SDIO definitions
// ! @{
//! \name SDIO state (in R5)
//! @{
// ! \name SDIO state (in R5)
// ! @{
#define SDIO_R5_COM_CRC_ERROR (1lu << 15) /**< CRC check error */
#define SDIO_R5_ILLEGAL_COMMAND (1lu << 14) /**< Illegal command */
#define SDIO_R5_STATE (3lu << 12) /**< SDIO R5 state mask */
@ -440,11 +440,11 @@ typedef uint32_t sdmmc_cmd_def_t;
#define SDIO_R5_ERROR (1lu << 11) /**< General error */
#define SDIO_R5_FUNC_NUM (1lu << 9) /**< Invalid function number */
#define SDIO_R5_OUT_OF_RANGE (1lu << 8) /**< Argument out of range */
#define SDIO_R5_STATUS_ERR (SDIO_R5_ERROR | SDIO_R5_FUNC_NUM | SDIO_R5_OUT_OF_RANGE) //!< Errro status bits mask
//! @}
#define SDIO_R5_STATUS_ERR (SDIO_R5_ERROR | SDIO_R5_FUNC_NUM | SDIO_R5_OUT_OF_RANGE) // !< Errro status bits mask
// ! @}
//! \name SDIO state (in R6)
//! @{
// ! \name SDIO state (in R6)
// ! @{
/** The CRC check of the previous command failed. */
#define SDIO_R6_COM_CRC_ERROR (1lu << 15)
/** Command not legal for the card state. */
@ -453,30 +453,30 @@ typedef uint32_t sdmmc_cmd_def_t;
#define SDIO_R6_ERROR (1lu << 13)
/** Status bits mask for SDIO R6 */
#define SDIO_STATUS_R6 (SDIO_R6_COM_CRC_ERROR | SDIO_R6_ILLEGAL_COMMAND | SDIO_R6_ERROR)
//! @}
// ! @}
//! \name SDIO CMD52 argument bit offset
//! @{
//! CMD52 arg[ 7: 0] Write data or stuff bits
// ! \name SDIO CMD52 argument bit offset
// ! @{
// ! CMD52 arg[ 7: 0] Write data or stuff bits
#define SDIO_CMD52_WR_DATA 0
//! CMD52 arg[ 8] Reserved
// ! CMD52 arg[ 8] Reserved
#define SDIO_CMD52_STUFF0 8
//! CMD52 arg[25: 9] Register address
// ! CMD52 arg[25: 9] Register address
#define SDIO_CMD52_REG_ADRR 9
//! CMD52 arg[ 26] Reserved
// ! CMD52 arg[ 26] Reserved
#define SDIO_CMD52_STUFF1 26
//! CMD52 arg[ 27] Read after Write flag
// ! CMD52 arg[ 27] Read after Write flag
#define SDIO_CMD52_RAW_FLAG 27
//! CMD52 arg[30:28] Number of the function
// ! CMD52 arg[30:28] Number of the function
#define SDIO_CMD52_FUNCTION_NUM 28
//! CMD52 arg[ 31] Direction, 1:write, 0:read.
// ! CMD52 arg[ 31] Direction, 1:write, 0:read.
#define SDIO_CMD52_RW_FLAG 31
#define SDIO_CMD52_READ_FLAG 0
#define SDIO_CMD52_WRITE_FLAG 1
//! @}
// ! @}
//! \name SDIO CMD53 argument structure
//! @{
// ! \name SDIO CMD53 argument structure
// ! @{
/**
* [ 8: 0] Byte mode: number of bytes to transfer,
* 0 cause 512 bytes transfer.
@ -484,22 +484,22 @@ typedef uint32_t sdmmc_cmd_def_t;
* 0 set count to infinite.
*/
#define SDIO_CMD53_COUNT 0
//! CMD53 arg[25: 9] Start Address I/O register
// ! CMD53 arg[25: 9] Start Address I/O register
#define SDIO_CMD53_REG_ADDR 9
//! CMD53 arg[ 26] 1:Incrementing address, 0: fixed
// ! CMD53 arg[ 26] 1:Incrementing address, 0: fixed
#define SDIO_CMD53_OP_CODE 26
//! CMD53 arg[ 27] (Optional) 1:block mode
// ! CMD53 arg[ 27] (Optional) 1:block mode
#define SDIO_CMD53_BLOCK_MODE 27
//! CMD53 arg[30:28] Number of the function
// ! CMD53 arg[30:28] Number of the function
#define SDIO_CMD53_FUNCTION_NUM 28
//! CMD53 arg[ 31] Direction, 1:WR, 0:RD
// ! CMD53 arg[ 31] Direction, 1:WR, 0:RD
#define SDIO_CMD53_RW_FLAG 31
#define SDIO_CMD53_READ_FLAG 0
#define SDIO_CMD53_WRITE_FLAG 1
//! @}
// ! @}
//! \name SDIO Functions
//! @{
// ! \name SDIO Functions
// ! @{
#define SDIO_CIA 0 /**< SDIO Function 0 (CIA) */
#define SDIO_FN0 0 /**< SDIO Function 0 */
#define SDIO_FN1 1 /**< SDIO Function 1 */
@ -509,10 +509,10 @@ typedef uint32_t sdmmc_cmd_def_t;
#define SDIO_FN5 5 /**< SDIO Function 5 */
#define SDIO_FN6 6 /**< SDIO Function 6 */
#define SDIO_FN7 7 /**< SDIO Function 7 */
//! @}
// ! @}
//! \name SDIO Card Common Control Registers (CCCR)
//! @{
// ! \name SDIO Card Common Control Registers (CCCR)
// ! @{
#define SDIO_CCCR_SDIO_REV 0x00 /**< CCCR/SDIO revision (RO) */
#define SDIO_CCCR_REV (0xFlu << 0) /**< CCCR/FBR Version */
#define SDIO_CCCR_REV_1_00 (0x0lu << 0) /**< CCCR/FBR Version 1.00 */
@ -652,10 +652,10 @@ typedef uint32_t sdmmc_cmd_def_t;
#define SDIO_CCCR_HS 0x13 /**< High-Speed */
#define SDIO_SHS (0x1lu << 0) /**< Support High-Speed (RO) */
#define SDIO_EHS (0x1lu << 1) /**< Enable High-Speed (R/W) */
//! @}
// ! @}
//! \name SDIO Function Basic Registers (FBR)
//! @{
// ! \name SDIO Function Basic Registers (FBR)
// ! @{
#define SDIO_FBR_ADDR(fn, x) (0x100 * (fn) + (x))
#define SDIO_FBR_CSA_IF 0x0 /**< CSA and function interface code (RO) */
#define SDIO_IFC (0xFUL << 0) /**< Standard SDIO Fun Interface Code */
@ -679,10 +679,10 @@ typedef uint32_t sdmmc_cmd_def_t;
#define SDIO_FBR_CSA_PTR 0xC /**< Address pointer to CSA (3B, LSB first) (R/W) */
#define SDIO_FBR_CSA_DATA 0xF /**< Read/Write fifo to CSA (R/W) */
#define SDIO_FBR_BLK_SIZ 0x10 /**< Block size (2B, LSB first) (R/W) */
//! @}
// ! @}
//! \name SDIO Card Metaformat
//! @{
// ! \name SDIO Card Metaformat
// ! @{
/** Null tuple (PCMCIA 3.1.9) */
#define SDIO_CISTPL_NULL 0x00
/** Device tuple (PCMCIA 3.2.2) */
@ -705,38 +705,37 @@ typedef uint32_t sdmmc_cmd_def_t;
#define SDIO_CISTPL_SDIO_EXT 0x92
/** The End-of-chain Tuple (PCMCIA 3.1.2) */
#define SDIO_CISTPL_END 0xFF
//! @}
// ! @}
//! @}
// ! @}
//! \name CSD, OCR, SCR, Switch status, extend CSD definitions
//! @{
// ! \name CSD, OCR, SCR, Switch status, extend CSD definitions
// ! @{
/**
* \brief Macro function to extract a bits field from a large SD MMC register
* Used by : CSD, SCR, Switch status
*/
static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint16_t pos, uint8_t size)
{
uint32_t value;
value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
if (((pos % 8) + size) > 8) {
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
}
if (((pos % 8) + size) > 16) {
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
}
if (((pos % 8) + size) > 24) {
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (24 - (pos % 8));
}
value &= ((uint32_t)1 << size) - 1;
return value;
static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint16_t pos, uint8_t size) {
uint32_t value;
value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
if (((pos % 8) + size) > 8) {
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
}
if (((pos % 8) + size) > 16) {
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
}
if (((pos % 8) + size) > 24) {
value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (24 - (pos % 8));
}
value &= ((uint32_t)1 << size) - 1;
return value;
}
//! \name CSD Fields
//! @{
#define CSD_REG_BIT_SIZE 128 //!< 128 bits
#define CSD_REG_BSIZE (CSD_REG_BIT_SIZE / 8) //!< 16 bytes
// ! \name CSD Fields
// ! @{
#define CSD_REG_BIT_SIZE 128 // !< 128 bits
#define CSD_REG_BSIZE (CSD_REG_BIT_SIZE / 8) // !< 16 bytes
#define CSD_STRUCTURE(csd, pos, size) SDMMC_UNSTUFF_BITS(csd, CSD_REG_BIT_SIZE, pos, size)
#define CSD_STRUCTURE_VERSION(csd) CSD_STRUCTURE(csd, 126, 2)
#define SD_CSD_VER_1_0 0
@ -753,10 +752,10 @@ static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint1
#define MMC_CSD_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3)
#define MMC_CSD_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4)
#define MMC_CSD_SPEC_VERS(csd) CSD_STRUCTURE(csd, 122, 4)
//! @}
// ! @}
//! \name OCR Register Fields
//! @{
// ! \name OCR Register Fields
// ! @{
#define OCR_REG_BSIZE (32 / 8) /**< 32 bits, 4 bytes */
#define OCR_VDD_170_195 (1lu << 7)
#define OCR_VDD_20_21 (1lu << 8)
@ -783,12 +782,12 @@ static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint1
#define OCR_ACCESS_MODE_SECTOR (2lu << 29) /**< (MMC) Sector access mode */
#define OCR_CCS (1lu << 30) /**< (SD) Card Capacity Status */
#define OCR_POWER_UP_BUSY (1lu << 31) /**< Card power up status bit */
//! @}
// ! @}
//! \name SD SCR Register Fields
//! @{
#define SD_SCR_REG_BIT_SIZE 64 //!< 64 bits
#define SD_SCR_REG_BSIZE (SD_SCR_REG_BIT_SIZE / 8) //!< 8 bytes
// ! \name SD SCR Register Fields
// ! @{
#define SD_SCR_REG_BIT_SIZE 64 // !< 64 bits
#define SD_SCR_REG_BSIZE (SD_SCR_REG_BIT_SIZE / 8) // !< 8 bytes
#define SD_SCR_STRUCTURE(scr, pos, size) SDMMC_UNSTUFF_BITS(scr, SD_SCR_REG_BIT_SIZE, pos, size)
#define SD_SCR_SCR_STRUCTURE(scr) SD_SCR_STRUCTURE(scr, 60, 4)
#define SD_SCR_SCR_STRUCTURE_1_0 0
@ -810,14 +809,14 @@ static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint1
#define SD_SCR_SD_SPEC_3_00 1
#define SD_SCR_SD_EX_SECURITY(scr) SD_SCR_STRUCTURE(scr, 43, 4)
#define SD_SCR_SD_CMD_SUPPORT(scr) SD_SCR_STRUCTURE(scr, 32, 2)
//! @}
// ! @}
//! \name SD Switch Status Fields
//! @{
#define SD_SW_STATUS_BIT_SIZE 512 //!< 512 bits
#define SD_SW_STATUS_BSIZE (SD_SW_STATUS_BIT_SIZE / 8) //!< 64 bytes
// ! \name SD Switch Status Fields
// ! @{
#define SD_SW_STATUS_BIT_SIZE 512 // !< 512 bits
#define SD_SW_STATUS_BSIZE (SD_SW_STATUS_BIT_SIZE / 8) // !< 64 bytes
#define SD_SW_STATUS_STRUCTURE(sd_sw_status, pos, size) \
SDMMC_UNSTUFF_BITS(sd_sw_status, SD_SW_STATUS_BIT_SIZE, pos, size)
SDMMC_UNSTUFF_BITS(sd_sw_status, SD_SW_STATUS_BIT_SIZE, pos, size)
#define SD_SW_STATUS_MAX_CURRENT_CONSUMPTION(status) SD_SW_STATUS_STRUCTURE(status, 496, 16)
#define SD_SW_STATUS_FUN_GRP6_INFO(status) SD_SW_STATUS_STRUCTURE(status, 480, 16)
#define SD_SW_STATUS_FUN_GRP5_INFO(status) SD_SW_STATUS_STRUCTURE(status, 464, 16)
@ -839,10 +838,10 @@ static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint1
#define SD_SW_STATUS_FUN_GRP3_BUSY(status) SD_SW_STATUS_STRUCTURE(status, 304, 16)
#define SD_SW_STATUS_FUN_GRP2_BUSY(status) SD_SW_STATUS_STRUCTURE(status, 288, 16)
#define SD_SW_STATUS_FUN_GRP1_BUSY(status) SD_SW_STATUS_STRUCTURE(status, 272, 16)
//! @}
// ! @}
//! \name Card Status Fields
//! @{
// ! \name Card Status Fields
// ! @{
#define CARD_STATUS_APP_CMD (1lu << 5)
#define CARD_STATUS_SWITCH_ERROR (1lu << 7)
#define CARD_STATUS_READY_FOR_DATA (1lu << 8)
@ -876,17 +875,17 @@ static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint1
#define CARD_STATUS_ADDR_OUT_OF_RANGE (1lu << 31)
#define CARD_STATUS_ERR_RD_WR \
(CARD_STATUS_ADDR_OUT_OF_RANGE | CARD_STATUS_ADDRESS_MISALIGN | CARD_STATUS_BLOCK_LEN_ERROR \
| CARD_STATUS_WP_VIOLATION | CARD_STATUS_ILLEGAL_COMMAND | CARD_STATUS_CC_ERROR | CARD_STATUS_ERROR)
//! @}
(CARD_STATUS_ADDR_OUT_OF_RANGE | CARD_STATUS_ADDRESS_MISALIGN | CARD_STATUS_BLOCK_LEN_ERROR \
| CARD_STATUS_WP_VIOLATION | CARD_STATUS_ILLEGAL_COMMAND | CARD_STATUS_CC_ERROR | CARD_STATUS_ERROR)
// ! @}
//! \name SD Status Field
//! @{
// ! \name SD Status Field
// ! @{
#define SD_STATUS_BSIZE (512 / 8) /**< 512 bits, 64bytes */
//! @}
// ! @}
//! \name MMC Extended CSD Register Field
//! @{
// ! \name MMC Extended CSD Register Field
// ! @{
#define EXT_CSD_BSIZE 512 /**< 512 bytes. */
/* Below belongs to Properties Segment */
#define EXT_CSD_S_CMD_SET_INDEX 504lu
@ -928,18 +927,18 @@ static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint1
#define EXT_CSD_BOOT_CONFIG_INDEX 179lu
#define EXT_CSD_BOOT_BUS_WIDTH_INDEX 177lu
#define EXT_CSD_ERASE_GROUP_DEF_INDEX 175lu
//! @}
//! @}
// ! @}
// ! @}
//! \name Definition for SPI mode only
//! @{
// ! \name Definition for SPI mode only
// ! @{
//! SPI commands start with a start bit "0" and a transmit bit "1"
// ! SPI commands start with a start bit "0" and a transmit bit "1"
#define SPI_CMD_ENCODE(x) (0x40 | (x & 0x3F))
//! \name Register R1 definition for SPI mode
//! The R1 register is always send after a command.
//! @{
// ! \name Register R1 definition for SPI mode
// ! The R1 register is always send after a command.
// ! @{
#define R1_SPI_IDLE (1lu << 0)
#define R1_SPI_ERASE_RESET (1lu << 1)
#define R1_SPI_ILLEGAL_COMMAND (1lu << 2)
@ -949,11 +948,11 @@ static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint1
#define R1_SPI_PARAMETER (1lu << 6)
// R1 bit 7 is always zero, reuse this bit for error
#define R1_SPI_ERROR (1lu << 7)
//! @}
// ! @}
//! \name Register R2 definition for SPI mode
//! The R2 register can be send after R1 register.
//! @{
// ! \name Register R2 definition for SPI mode
// ! The R2 register can be send after R1 register.
// ! @{
#define R2_SPI_CARD_LOCKED (1lu << 0)
#define R2_SPI_WP_ERASE_SKIP (1lu << 1)
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
@ -964,35 +963,35 @@ static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size, uint1
#define R2_SPI_ERASE_PARAM (1lu << 6)
#define R2_SPI_OUT_OF_RANGE (1lu << 7)
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
//! @}
// ! @}
//! \name Control Tokens in SPI Mode
//! @{
//! \name Tokens used for a read operation
//! @{
// ! \name Control Tokens in SPI Mode
// ! @{
// ! \name Tokens used for a read operation
// ! @{
#define SPI_TOKEN_SINGLE_MULTI_READ 0xFE
#define SPI_TOKEN_DATA_ERROR_VALID(token) (((token)&0xF0) == 0)
#define SPI_TOKEN_DATA_ERROR_VALID(token) (((token) & 0xF0) == 0)
#define SPI_TOKEN_DATA_ERROR_ERRORS (0x0F)
#define SPI_TOKEN_DATA_ERROR_ERROR (1lu << 0)
#define SPI_TOKEN_DATA_ERROR_CC_ERROR (1lu << 1)
#define SPI_TOKEN_DATA_ERROR_ECC_ERROR (1lu << 2)
#define SPI_TOKEN_DATA_ERROR_OUT_RANGE (1lu << 3)
//! @}
//! \name Tokens used for a write operation
//! @{
// ! @}
// ! \name Tokens used for a write operation
// ! @{
#define SPI_TOKEN_SINGLE_WRITE 0xFE
#define SPI_TOKEN_MULTI_WRITE 0xFC
#define SPI_TOKEN_STOP_TRAN 0xFD
#define SPI_TOKEN_DATA_RESP_VALID(token) ((((token) & (1 << 4)) == 0) && (((token) & (1 << 0)) == 1))
#define SPI_TOKEN_DATA_RESP_CODE(token) ((token)&0x1E)
#define SPI_TOKEN_DATA_RESP_CODE(token) ((token) & 0x1E)
#define SPI_TOKEN_DATA_RESP_ACCEPTED (2lu << 1)
#define SPI_TOKEN_DATA_RESP_CRC_ERR (5lu << 1)
#define SPI_TOKEN_DATA_RESP_WRITE_ERR (6lu << 1)
//! @}
//! @}
//! @}
// ! @}
// ! @}
// ! @}
//! @} end of sd_mmc_protocol
// ! @} end of sd_mmc_protocol
#ifdef __cplusplus
}

18
ports/atmel-samd/supervisor/internal_flash.c
View File

@ -58,12 +58,12 @@ static struct flash_descriptor supervisor_flash_desc;
void supervisor_flash_init(void) {
// Activity LED for flash writes.
#ifdef MICROPY_HW_LED_MSC
struct port_config pin_conf;
port_get_config_defaults(&pin_conf);
struct port_config pin_conf;
port_get_config_defaults(&pin_conf);
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(MICROPY_HW_LED_MSC, &pin_conf);
port_pin_set_output_level(MICROPY_HW_LED_MSC, false);
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(MICROPY_HW_LED_MSC, &pin_conf);
port_pin_set_output_level(MICROPY_HW_LED_MSC, false);
#endif
#ifdef SAM_D5X_E5X
@ -115,7 +115,7 @@ bool supervisor_flash_read_block(uint8_t *dest, uint32_t block) {
bool supervisor_flash_write_block(const uint8_t *src, uint32_t block) {
#ifdef MICROPY_HW_LED_MSC
port_pin_set_output_level(MICROPY_HW_LED_MSC, true);
port_pin_set_output_level(MICROPY_HW_LED_MSC, true);
#endif
temp_status_color(ACTIVE_WRITE);
// non-MBR block, copy to cache
@ -126,8 +126,8 @@ bool supervisor_flash_write_block(const uint8_t *src, uint32_t block) {
}
int32_t error_code;
error_code = flash_erase(&supervisor_flash_desc,
dest,
FILESYSTEM_BLOCK_SIZE / flash_get_page_size(&supervisor_flash_desc));
dest,
FILESYSTEM_BLOCK_SIZE / flash_get_page_size(&supervisor_flash_desc));
if (error_code != ERR_NONE) {
return false;
}
@ -138,7 +138,7 @@ bool supervisor_flash_write_block(const uint8_t *src, uint32_t block) {
}
clear_temp_status();
#ifdef MICROPY_HW_LED_MSC
port_pin_set_output_level(MICROPY_HW_LED_MSC, false);
port_pin_set_output_level(MICROPY_HW_LED_MSC, false);
#endif
return true;
}

183
ports/atmel-samd/supervisor/port.c
View File

@ -97,9 +97,13 @@
volatile bool hold_interrupt = false;
#ifdef SAMD21
static void rtc_set_continuous(bool continuous) {
while (RTC->MODE0.STATUS.bit.SYNCBUSY);
while (RTC->MODE0.STATUS.bit.SYNCBUSY) {
;
}
RTC->MODE0.READREQ.reg = (continuous ? RTC_READREQ_RCONT : 0) | 0x0010;
while (RTC->MODE0.STATUS.bit.SYNCBUSY);
while (RTC->MODE0.STATUS.bit.SYNCBUSY) {
;
}
}
void rtc_start_pulse(void) {
@ -132,8 +136,8 @@ static void save_usb_clock_calibration(void) {
// save the new value if its different enough.
SYSCTRL->DFLLSYNC.bit.READREQ = 1;
uint16_t saved_calibration = 0x1ff;
if (strcmp((char*) CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) {
saved_calibration = ((uint16_t *) CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8];
if (strcmp((char *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) {
saved_calibration = ((uint16_t *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8];
}
while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {
// TODO(tannewt): Run the mass storage stuff if this takes a while.
@ -142,7 +146,7 @@ static void save_usb_clock_calibration(void) {
if (abs(current_calibration - saved_calibration) > 10) {
// Copy the full internal config page to memory.
uint8_t page_buffer[NVMCTRL_ROW_SIZE];
memcpy(page_buffer, (uint8_t*) CIRCUITPY_INTERNAL_CONFIG_START_ADDR, NVMCTRL_ROW_SIZE);
memcpy(page_buffer, (uint8_t *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR, NVMCTRL_ROW_SIZE);
// Modify it.
memcpy(page_buffer, "CIRCUITPYTHON1", 15);
@ -155,31 +159,33 @@ static void save_usb_clock_calibration(void) {
// whenever we need it instead of storing it long term.
struct flash_descriptor desc;
desc.dev.hw = NVMCTRL;
flash_write(&desc, (uint32_t) CIRCUITPY_INTERNAL_CONFIG_START_ADDR, page_buffer, NVMCTRL_ROW_SIZE);
flash_write(&desc, (uint32_t)CIRCUITPY_INTERNAL_CONFIG_START_ADDR, page_buffer, NVMCTRL_ROW_SIZE);
}
}
#endif
static void rtc_init(void) {
#ifdef SAMD21
#ifdef SAMD21
_gclk_enable_channel(RTC_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK2_Val);
RTC->MODE0.CTRL.bit.SWRST = true;
while (RTC->MODE0.CTRL.bit.SWRST != 0) {}
while (RTC->MODE0.CTRL.bit.SWRST != 0) {
}
RTC->MODE0.CTRL.reg = RTC_MODE0_CTRL_ENABLE |
RTC_MODE0_CTRL_MODE_COUNT32 |
RTC_MODE0_CTRL_PRESCALER_DIV2;
#endif
#ifdef SAM_D5X_E5X
RTC_MODE0_CTRL_MODE_COUNT32 |
RTC_MODE0_CTRL_PRESCALER_DIV2;
#endif
#ifdef SAM_D5X_E5X
hri_mclk_set_APBAMASK_RTC_bit(MCLK);
RTC->MODE0.CTRLA.bit.SWRST = true;
while (RTC->MODE0.SYNCBUSY.bit.SWRST != 0) {}
while (RTC->MODE0.SYNCBUSY.bit.SWRST != 0) {
}
RTC->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_ENABLE |
RTC_MODE0_CTRLA_MODE_COUNT32 |
RTC_MODE0_CTRLA_PRESCALER_DIV2 |
RTC_MODE0_CTRLA_COUNTSYNC;
#endif
RTC_MODE0_CTRLA_MODE_COUNT32 |
RTC_MODE0_CTRLA_PRESCALER_DIV2 |
RTC_MODE0_CTRLA_COUNTSYNC;
#endif
RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
@ -201,14 +207,14 @@ static void rtc_init(void) {
#endif
NVIC_ClearPendingIRQ(RTC_IRQn);
NVIC_EnableIRQ(RTC_IRQn);
#if CIRCUITPY_RTC
#if CIRCUITPY_RTC
rtc_reset();
#endif
#endif
}
safe_mode_t port_init(void) {
#if defined(SAMD21)
#if defined(SAMD21)
// Set brownout detection.
// Disable while changing level.
@ -217,17 +223,17 @@ safe_mode_t port_init(void) {
SYSCTRL->BOD33.bit.ENABLE = 1;
#ifdef ENABLE_MICRO_TRACE_BUFFER
REG_MTB_POSITION = ((uint32_t) (mtb - REG_MTB_BASE)) & 0xFFFFFFF8;
REG_MTB_FLOW = (((uint32_t) mtb - REG_MTB_BASE) + TRACE_BUFFER_SIZE_BYTES) & 0xFFFFFFF8;
REG_MTB_MASTER = 0x80000000 + (TRACE_BUFFER_MAGNITUDE_PACKETS - 1);
REG_MTB_POSITION = ((uint32_t)(mtb - REG_MTB_BASE)) & 0xFFFFFFF8;
REG_MTB_FLOW = (((uint32_t)mtb - REG_MTB_BASE) + TRACE_BUFFER_SIZE_BYTES) & 0xFFFFFFF8;
REG_MTB_MASTER = 0x80000000 + (TRACE_BUFFER_MAGNITUDE_PACKETS - 1);
#else
// Triple check that the MTB is off. Switching between debug and non-debug
// builds can leave it set over reset and wreak havok as a result.
REG_MTB_MASTER = 0x00000000 + 6;
// Triple check that the MTB is off. Switching between debug and non-debug
// builds can leave it set over reset and wreak havok as a result.
REG_MTB_MASTER = 0x00000000 + 6;
#endif
#endif
#endif
#if defined(SAM_D5X_E5X)
#if defined(SAM_D5X_E5X)
// Set brownout detection.
// Disable while changing level.
SUPC->BOD33.bit.ENABLE = 0;
@ -240,7 +246,7 @@ safe_mode_t port_init(void) {
// Leaving this code here disabled,
// because it was hard enough to figure out, and maybe there's
// a mistake that could make it work in the future.
#if 0
#if 0
// Designate QSPI memory mapped region as not cachable.
// Turn off MPU in case it is on.
@ -252,15 +258,15 @@ safe_mode_t port_init(void) {
MPU->RBAR = QSPI_AHB;
MPU->RASR =
0b011 << MPU_RASR_AP_Pos | // full read/write access for privileged and user mode
0b000 << MPU_RASR_TEX_Pos | // caching not allowed, strongly ordered
1 << MPU_RASR_S_Pos | // sharable
0 << MPU_RASR_C_Pos | // not cachable
0 << MPU_RASR_B_Pos | // not bufferable
0b10111 << MPU_RASR_SIZE_Pos | // 16MB region size
1 << MPU_RASR_ENABLE_Pos // enable this region
;
0b000 << MPU_RASR_TEX_Pos | // caching not allowed, strongly ordered
1 << MPU_RASR_S_Pos | // sharable
0 << MPU_RASR_C_Pos | // not cachable
0 << MPU_RASR_B_Pos | // not bufferable
0b10111 << MPU_RASR_SIZE_Pos | // 16MB region size
1 << MPU_RASR_ENABLE_Pos // enable this region
;
// Turn off regions 1-7.
for (uint32_t i = 1; i < 8; i ++) {
for (uint32_t i = 1; i < 8; i++) {
MPU->RNR = i;
MPU->RBAR = 0;
MPU->RASR = 0;
@ -270,28 +276,28 @@ safe_mode_t port_init(void) {
// map for all privileged access, so we don't have to set up other regions
// besides QSPI.
MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
#endif
#endif
samd_peripherals_enable_cache();
#endif
#endif
#ifdef SAMD21
#ifdef SAMD21
hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
_pm_init();
#endif
#endif
#if CALIBRATE_CRYSTALLESS
#if CALIBRATE_CRYSTALLESS
uint32_t fine = DEFAULT_DFLL48M_FINE_CALIBRATION;
// The fine calibration data is stored in an NVM page after the text and data storage but before
// the optional file system. The first 16 bytes are the identifier for the section.
if (strcmp((char*) CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) {
fine = ((uint16_t *) CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8];
if (strcmp((char *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) {
fine = ((uint16_t *)CIRCUITPY_INTERNAL_CONFIG_START_ADDR)[8];
}
clock_init(BOARD_HAS_CRYSTAL, fine);
#else
#else
// Use a default fine value
clock_init(BOARD_HAS_CRYSTAL, DEFAULT_DFLL48M_FINE_CALIBRATION);
#endif
#endif
rtc_init();
@ -319,48 +325,48 @@ safe_mode_t port_init(void) {
}
void reset_port(void) {
#if CIRCUITPY_BUSIO
#if CIRCUITPY_BUSIO
reset_sercoms();
#endif
#if CIRCUITPY_AUDIOIO
#endif
#if CIRCUITPY_AUDIOIO
audio_dma_reset();
audioout_reset();
#endif
#if CIRCUITPY_AUDIOBUSIO
//pdmin_reset();
#endif
#if CIRCUITPY_AUDIOBUSIO_I2SOUT
#endif
#if CIRCUITPY_AUDIOBUSIO
// pdmin_reset();
#endif
#if CIRCUITPY_AUDIOBUSIO_I2SOUT
i2sout_reset();
#endif
#endif
#if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE
#if CIRCUITPY_TOUCHIO && CIRCUITPY_TOUCHIO_USE_NATIVE
touchin_reset();
#endif
#endif
eic_reset();
#if CIRCUITPY_PULSEIO
#if CIRCUITPY_PULSEIO
pulsein_reset();
pulseout_reset();
#endif
#if CIRCUITPY_PWMIO
#endif
#if CIRCUITPY_PWMIO
pwmout_reset();
#endif
#endif
#if CIRCUITPY_ANALOGIO
#if CIRCUITPY_ANALOGIO
analogin_reset();
analogout_reset();
#endif
#endif
reset_gclks();
#if CIRCUITPY_GAMEPAD
#if CIRCUITPY_GAMEPAD
gamepad_reset();
#endif
#if CIRCUITPY_GAMEPADSHIFT
#endif
#if CIRCUITPY_GAMEPADSHIFT
gamepadshift_reset();
#endif
#if CIRCUITPY_PEW
#endif
#if CIRCUITPY_PEW
pew_reset();
#endif
#endif
reset_event_system();
@ -375,11 +381,11 @@ void reset_port(void) {
// gpio_set_pin_function(PIN_PB15, GPIO_PIN_FUNCTION_M); // GCLK1, D6
// #endif
#if CALIBRATE_CRYSTALLESS
#if CALIBRATE_CRYSTALLESS
if (tud_cdc_connected()) {
save_usb_clock_calibration();
}
#endif
#endif
}
void reset_to_bootloader(void) {
@ -413,10 +419,10 @@ uint32_t *port_heap_get_top(void) {
// Place the word to save 8k from the end of RAM so we and the bootloader don't clobber it.
#ifdef SAMD21
uint32_t* safe_word = (uint32_t*) (HMCRAMC0_ADDR + HMCRAMC0_SIZE - 0x2000);
uint32_t *safe_word = (uint32_t *)(HMCRAMC0_ADDR + HMCRAMC0_SIZE - 0x2000);
#endif
#ifdef SAM_D5X_E5X
uint32_t* safe_word = (uint32_t*) (HSRAM_ADDR + HSRAM_SIZE - 0x2000);
uint32_t *safe_word = (uint32_t *)(HSRAM_ADDR + HSRAM_SIZE - 0x2000);
#endif
void port_set_saved_word(uint32_t value) {
@ -434,14 +440,16 @@ static volatile uint64_t overflowed_ticks = 0;
static volatile bool _ticks_enabled = false;
#endif
static uint32_t _get_count(uint64_t* overflow_count) {
static uint32_t _get_count(uint64_t *overflow_count) {
#ifdef SAM_D5X_E5X
while ((RTC->MODE0.SYNCBUSY.reg & (RTC_MODE0_SYNCBUSY_COUNTSYNC | RTC_MODE0_SYNCBUSY_COUNT)) != 0) {}
while ((RTC->MODE0.SYNCBUSY.reg & (RTC_MODE0_SYNCBUSY_COUNTSYNC | RTC_MODE0_SYNCBUSY_COUNT)) != 0) {
}
#endif
#ifdef SAMD21
// Request a read so we don't stall the bus later. See section 14.3.1.5 Read Request
RTC->MODE0.READREQ.reg = RTC_READREQ_RREQ | 0x0010;
while (RTC->MODE0.STATUS.bit.SYNCBUSY != 0) {}
while (RTC->MODE0.STATUS.bit.SYNCBUSY != 0) {
}
#endif
// Disable interrupts so we can grab the count and the overflow.
common_hal_mcu_disable_interrupts();
@ -460,11 +468,11 @@ static void _port_interrupt_after_ticks(uint32_t ticks) {
// We'll interrupt sooner with an overflow.
return;
}
#ifdef SAMD21
#ifdef SAMD21
if (hold_interrupt) {
return;
}
#endif
#endif
RTC->MODE0.COMP[0].reg = current_ticks + (ticks << 4);
RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
RTC->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
@ -476,7 +484,7 @@ void RTC_Handler(void) {
RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
// Our RTC is 32 bits and we're clocking it at 16.384khz which is 16 (2 ** 4) subticks per
// tick.
overflowed_ticks += (1L<< (32 - 4));
overflowed_ticks += (1L << (32 - 4));
#ifdef SAM_D5X_E5X
} else if (intflag & RTC_MODE0_INTFLAG_PER2) {
RTC->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
@ -502,7 +510,7 @@ void RTC_Handler(void) {
}
}
uint64_t port_get_raw_ticks(uint8_t* subticks) {
uint64_t port_get_raw_ticks(uint8_t *subticks) {
uint64_t overflow_count;
uint32_t current_ticks = _get_count(&overflow_count);
if (subticks != NULL) {
@ -551,9 +559,9 @@ void port_interrupt_after_ticks(uint32_t ticks) {
void port_idle_until_interrupt(void) {
#ifdef SAM_D5X_E5X
// Clear the FPU interrupt because it can prevent us from sleeping.
if (__get_FPSCR() & ~(0x9f)) {
__set_FPSCR(__get_FPSCR() & ~(0x9f));
(void) __get_FPSCR();
if (__get_FPSCR() & ~(0x9f)) {
__set_FPSCR(__get_FPSCR() & ~(0x9f));
(void)__get_FPSCR();
}
#endif
common_hal_mcu_disable_interrupts();
@ -567,16 +575,15 @@ void port_idle_until_interrupt(void) {
/**
* \brief Default interrupt handler for unused IRQs.
*/
__attribute__((used)) void HardFault_Handler(void)
{
#ifdef ENABLE_MICRO_TRACE_BUFFER
__attribute__((used)) void HardFault_Handler(void) {
#ifdef ENABLE_MICRO_TRACE_BUFFER
// Turn off the micro trace buffer so we don't fill it up in the infinite
// loop below.
REG_MTB_MASTER = 0x00000000 + 6;
#endif
#endif
reset_into_safe_mode(HARD_CRASH);
while (true) {
asm("nop;");
asm ("nop;");
}
}

114
ports/atmel-samd/supervisor/qspi_flash.c
View File

@ -43,40 +43,44 @@ bool spi_flash_command(uint8_t command) {
QSPI->INSTRCTRL.bit.INSTR = command;
QSPI->INSTRFRAME.reg = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI |
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READ |
QSPI_INSTRFRAME_INSTREN;
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READ |
QSPI_INSTRFRAME_INSTREN;
QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
while( !QSPI->INTFLAG.bit.INSTREND );
while (!QSPI->INTFLAG.bit.INSTREND) {
;
}
QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
return true;
}
bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length) {
bool spi_flash_read_command(uint8_t command, uint8_t *response, uint32_t length) {
samd_peripherals_disable_and_clear_cache();
QSPI->INSTRCTRL.bit.INSTR = command;
QSPI->INSTRFRAME.reg = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI |
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READ |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_DATAEN;
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READ |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_DATAEN;
// Dummy read of INSTRFRAME needed to synchronize.
// See Instruction Transmission Flow Diagram, figure 37.9, page 995
// and Example 4, page 998, section 37.6.8.5.
(volatile uint32_t) QSPI->INSTRFRAME.reg;
(volatile uint32_t)QSPI->INSTRFRAME.reg;
memcpy(response, (uint8_t *) QSPI_AHB, length);
memcpy(response, (uint8_t *)QSPI_AHB, length);
QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
while( !QSPI->INTFLAG.bit.INSTREND );
while (!QSPI->INTFLAG.bit.INSTREND) {
;
}
QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
@ -85,29 +89,31 @@ bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length)
return true;
}
bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) {
bool spi_flash_write_command(uint8_t command, uint8_t *data, uint32_t length) {
samd_peripherals_disable_and_clear_cache();
QSPI->INSTRCTRL.bit.INSTR = command;
QSPI->INSTRFRAME.reg = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI |
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_WRITE |
QSPI_INSTRFRAME_INSTREN |
(data != NULL ? QSPI_INSTRFRAME_DATAEN : 0);
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_WRITE |
QSPI_INSTRFRAME_INSTREN |
(data != NULL ? QSPI_INSTRFRAME_DATAEN : 0);
// Dummy read of INSTRFRAME needed to synchronize.
// See Instruction Transmission Flow Diagram, figure 37.9, page 995
// and Example 4, page 998, section 37.6.8.5.
(volatile uint32_t) QSPI->INSTRFRAME.reg;
(volatile uint32_t)QSPI->INSTRFRAME.reg;
if (data != NULL) {
memcpy((uint8_t *) QSPI_AHB, data, length);
memcpy((uint8_t *)QSPI_AHB, data, length);
}
QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
while( !QSPI->INTFLAG.bit.INSTREND );
while (!QSPI->INTFLAG.bit.INSTREND) {
;
}
QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
@ -121,40 +127,44 @@ bool spi_flash_sector_command(uint8_t command, uint32_t address) {
QSPI->INSTRADDR.bit.ADDR = address;
QSPI->INSTRFRAME.reg = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI |
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_WRITE |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_ADDREN;
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_WRITE |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_ADDREN;
QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
while( !QSPI->INTFLAG.bit.INSTREND );
while (!QSPI->INTFLAG.bit.INSTREND) {
;
}
QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
return true;
}
bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) {
bool spi_flash_write_data(uint32_t address, uint8_t *data, uint32_t length) {
samd_peripherals_disable_and_clear_cache();
QSPI->INSTRCTRL.bit.INSTR = CMD_PAGE_PROGRAM;
uint32_t mode = QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI;
QSPI->INSTRFRAME.reg = mode |
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_ADDREN |
QSPI_INSTRFRAME_DATAEN;
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_ADDREN |
QSPI_INSTRFRAME_DATAEN;
memcpy(((uint8_t *) QSPI_AHB) + address, data, length);
memcpy(((uint8_t *)QSPI_AHB) + address, data, length);
// TODO(tannewt): Fix DMA and enable it.
// qspi_dma_write(address, data, length);
QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
while( !QSPI->INTFLAG.bit.INSTREND );
while (!QSPI->INTFLAG.bit.INSTREND) {
;
}
QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
@ -163,7 +173,7 @@ bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) {
return true;
}
bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
bool spi_flash_read_data(uint32_t address, uint8_t *data, uint32_t length) {
samd_peripherals_disable_and_clear_cache();
#ifdef EXTERNAL_FLASH_QSPI_SINGLE
@ -179,29 +189,31 @@ bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
#ifdef EXTERNAL_FLASH_QSPI_SINGLE
QSPI->INSTRFRAME.reg = mode |
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READMEMORY |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_ADDREN |
QSPI_INSTRFRAME_DATAEN |
QSPI_INSTRFRAME_DUMMYLEN(0);
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READMEMORY |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_ADDREN |
QSPI_INSTRFRAME_DATAEN |
QSPI_INSTRFRAME_DUMMYLEN(0);
#else
QSPI->INSTRFRAME.reg = mode |
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READMEMORY |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_ADDREN |
QSPI_INSTRFRAME_DATAEN |
QSPI_INSTRFRAME_DUMMYLEN(8);
QSPI_INSTRFRAME_ADDRLEN_24BITS |
QSPI_INSTRFRAME_TFRTYPE_READMEMORY |
QSPI_INSTRFRAME_INSTREN |
QSPI_INSTRFRAME_ADDREN |
QSPI_INSTRFRAME_DATAEN |
QSPI_INSTRFRAME_DUMMYLEN(8);
#endif
memcpy(data, ((uint8_t *) QSPI_AHB) + address, length);
memcpy(data, ((uint8_t *)QSPI_AHB) + address, length);
// TODO(tannewt): Fix DMA and enable it.
// qspi_dma_read(address, data, length);
QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE | QSPI_CTRLA_LASTXFER;
while( !QSPI->INTFLAG.bit.INSTREND );
while (!QSPI->INTFLAG.bit.INSTREND) {
;
}
QSPI->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
@ -224,8 +236,8 @@ void spi_flash_init(void) {
// Super fast, may be unreliable when Saleae is connected to high speed lines.
QSPI->BAUD.bit.BAUD = 2;
QSPI->CTRLB.reg = QSPI_CTRLB_MODE_MEMORY | // Serial memory mode (map to QSPI_AHB)
QSPI_CTRLB_DATALEN_8BITS |
QSPI_CTRLB_CSMODE_LASTXFER;
QSPI_CTRLB_DATALEN_8BITS |
QSPI_CTRLB_CSMODE_LASTXFER;
QSPI->CTRLA.reg = QSPI_CTRLA_ENABLE;
@ -238,7 +250,7 @@ void spi_flash_init(void) {
}
}
void spi_flash_init_device(const external_flash_device* device) {
void spi_flash_init_device(const external_flash_device *device) {
check_quad_enable(device);
// TODO(tannewt): Adjust the speed for the found device.

8
ports/atmel-samd/supervisor/usb.c
View File

@ -68,19 +68,19 @@ void USB_Handler(void) {
#endif
#ifdef SAM_D5X_E5X
void USB_0_Handler (void) {
void USB_0_Handler(void) {
usb_irq_handler();
}
void USB_1_Handler (void) {
void USB_1_Handler(void) {
usb_irq_handler();
}
void USB_2_Handler (void) {
void USB_2_Handler(void) {
usb_irq_handler();
}
void USB_3_Handler (void) {
void USB_3_Handler(void) {
usb_irq_handler();
}
#endif

10
ports/esp32s2/boards/adafruit_funhouse/board.c
View File

@ -55,16 +55,16 @@ void board_init(void) {
common_hal_never_reset_pin(&pin_GPIO20);
// Debug UART
#ifdef DEBUG
#ifdef DEBUG
common_hal_never_reset_pin(&pin_GPIO37);
common_hal_never_reset_pin(&pin_GPIO38);
#endif /* DEBUG */
#endif /* DEBUG */
busio_spi_obj_t* spi = &displays[0].fourwire_bus.inline_bus;
busio_spi_obj_t *spi = &displays[0].fourwire_bus.inline_bus;
common_hal_busio_spi_construct(spi, &pin_GPIO36, &pin_GPIO35, NULL);
common_hal_busio_spi_never_reset(spi);
displayio_fourwire_obj_t* bus = &displays[0].fourwire_bus;
displayio_fourwire_obj_t *bus = &displays[0].fourwire_bus;
bus->base.type = &displayio_fourwire_type;
common_hal_displayio_fourwire_construct(bus,
spi,
@ -78,7 +78,7 @@ void board_init(void) {
// workaround as board_init() is called before reset_port() in main.c
pwmout_reset();
displayio_display_obj_t* display = &displays[0].display;
displayio_display_obj_t *display = &displays[0].display;
display->base.type = &displayio_display_type;
common_hal_displayio_display_construct(
display,

2
ports/esp32s2/boards/adafruit_funhouse/mpconfigboard.h
View File

@ -24,7 +24,7 @@
* THE SOFTWARE.
*/
//Micropython setup
// Micropython setup
#define MICROPY_HW_BOARD_NAME "Adafruit FunHome"
#define MICROPY_HW_MCU_NAME "ESP32S2"

4
ports/esp32s2/boards/artisense_rd00/board.c
View File

@ -34,10 +34,10 @@ void board_init(void) {
common_hal_never_reset_pin(&pin_GPIO20);
// Debug UART
#ifdef DEBUG
#ifdef DEBUG
common_hal_never_reset_pin(&pin_GPIO43);
common_hal_never_reset_pin(&pin_GPIO44);
#endif /* DEBUG */
#endif /* DEBUG */
// Crystal
common_hal_never_reset_pin(&pin_GPIO15);

4
ports/esp32s2/boards/artisense_rd00/mpconfigboard.h
View File

@ -24,9 +24,9 @@
* THE SOFTWARE.
*/
//Micropython setup
// Micropython setup
//Same setup as the Saola board but with no Neopixel on board
// Same setup as the Saola board but with no Neopixel on board
#define MICROPY_HW_BOARD_NAME "Artisense Reference Design RD00"
#define MICROPY_HW_MCU_NAME "ESP32S2"

4
ports/esp32s2/boards/atmegazero_esp32s2/board.c
View File

@ -34,10 +34,10 @@ void board_init(void) {
common_hal_never_reset_pin(&pin_GPIO20);
// Debug UART
#ifdef DEBUG
#ifdef DEBUG
common_hal_never_reset_pin(&pin_GPIO43);
common_hal_never_reset_pin(&pin_GPIO44);
#endif /* DEBUG */
#endif /* DEBUG */
// SPI Flash and RAM
common_hal_never_reset_pin(&pin_GPIO26);

2
ports/esp32s2/boards/atmegazero_esp32s2/mpconfigboard.h
View File

@ -24,7 +24,7 @@
* THE SOFTWARE.
*/
//Micropython setup
// Micropython setup
#define MICROPY_HW_BOARD_NAME "ATMegaZero ESP32-S2"
#define MICROPY_HW_MCU_NAME "ESP32S2"

12
ports/mimxrt10xx/common-hal/pwmio/PWMOut.c
View File

@ -150,11 +150,11 @@ void pwmout_reset(void) {
#define PWM_SRC_CLK_FREQ CLOCK_GetFreq(kCLOCK_IpgClk)
static int calculate_pulse_count(uint32_t frequency, uint8_t *prescaler) {
if (frequency > PWM_SRC_CLK_FREQ/2) {
if (frequency > PWM_SRC_CLK_FREQ / 2) {
return 0;
}
for(int shift = 0; shift<8; shift++) {
int pulse_count = PWM_SRC_CLK_FREQ/(1<<shift)/frequency;
for (int shift = 0; shift < 8; shift++) {
int pulse_count = PWM_SRC_CLK_FREQ / (1 << shift) / frequency;
if (pulse_count >= 65535) {
continue;
}
@ -270,7 +270,7 @@ void common_hal_pwmio_pwmout_set_duty_cycle(pwmio_pwmout_obj_t *self, uint16_t d
if (duty == 65535) {
self->duty_scaled = self->pulse_count + 1;
} else {
self->duty_scaled = ((uint32_t)duty * self->pulse_count + self->pulse_count/2) / 65535;
self->duty_scaled = ((uint32_t)duty * self->pulse_count + self->pulse_count / 2) / 65535;
}
switch (self->pwm->channel) {
case kPWM_PwmX:
@ -292,7 +292,7 @@ uint16_t common_hal_pwmio_pwmout_get_duty_cycle(pwmio_pwmout_obj_t *self) {
if (self->duty_cycle == 65535) {
return 65535;
}
return ((uint32_t)self->duty_scaled * 65535 + 65535/2) / self->pulse_count;
return ((uint32_t)self->duty_scaled * 65535 + 65535 / 2) / self->pulse_count;
}
void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self,
@ -319,7 +319,7 @@ void common_hal_pwmio_pwmout_set_frequency(pwmio_pwmout_obj_t *self,
}
uint32_t common_hal_pwmio_pwmout_get_frequency(pwmio_pwmout_obj_t *self) {
return PWM_SRC_CLK_FREQ/self->pulse_count/(1 << self->prescaler);
return PWM_SRC_CLK_FREQ / self->pulse_count / (1 << self->prescaler);
}
bool common_hal_pwmio_pwmout_get_variable_frequency(pwmio_pwmout_obj_t *self) {

10
ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h
View File

@ -49,8 +49,8 @@ typedef struct {
typedef struct {
PWM_Type *pwm;
pwm_submodule_t submodule:4;
pwm_channels_t channel:4;
pwm_submodule_t submodule : 4;
pwm_channels_t channel : 4;
uint8_t mux_mode;
uint8_t input_idx;
uint32_t input_reg;
@ -59,9 +59,9 @@ typedef struct {
#define PWM_PIN(p_pwm, p_submodule, p_channel, p_iomuxc, p_pin) \
PWM_PIN_(p_pwm, p_submodule, p_channel, p_iomuxc, p_pin)
//----------------------------------------------------------//
// supplied by the expansion of p_iomuxc into multiple args //
#define PWM_PIN_(p_pwm, p_submodule, p_channel, p_mux_reg, p_mux_mode, p_input_reg, p_input_idx, p_config_reg, p_pin)\
// ----------------------------------------------------------//
// supplied by the expansion of p_iomuxc into multiple args //
#define PWM_PIN_(p_pwm, p_submodule, p_channel, p_mux_reg, p_mux_mode, p_input_reg, p_input_idx, p_config_reg, p_pin) \
{ \
.pwm = p_pwm, \
.submodule = p_submodule, \

148
ports/nrf/common-hal/alarm/__init__.c
View File

@ -80,42 +80,40 @@ STATIC nrf_sleep_source_t _get_wakeup_cause(void) {
}
if (reset_reason_saved & NRF_POWER_RESETREAS_RESETPIN_MASK) {
return NRF_SLEEP_WAKEUP_RESETPIN;
}
else if (reset_reason_saved & NRF_POWER_RESETREAS_OFF_MASK) {
} else if (reset_reason_saved & NRF_POWER_RESETREAS_OFF_MASK) {
return NRF_SLEEP_WAKEUP_GPIO;
}
else if (reset_reason_saved & NRF_POWER_RESETREAS_VBUS_MASK) {
} else if (reset_reason_saved & NRF_POWER_RESETREAS_VBUS_MASK) {
return NRF_SLEEP_WAKEUP_VBUS;
}
return NRF_SLEEP_WAKEUP_UNDEFINED;
}
#ifdef NRF_DEBUG_PRINT
static const char* cause_str[] = {
"UNDEFINED",
"GPIO",
"TIMER",
"TOUCHPAD",
"VBUS",
"RESETPIN",
static const char *cause_str[] = {
"UNDEFINED",
"GPIO",
"TIMER",
"TOUCHPAD",
"VBUS",
"RESETPIN",
};
void print_wakeup_cause(nrf_sleep_source_t cause) {
if (cause >= 0 && cause < NRF_SLEEP_WAKEUP_ZZZ) {
dbg_printf("wakeup cause = NRF_SLEEP_WAKEUP_%s\r\n",
cause_str[(int)cause]);
cause_str[(int)cause]);
}
}
#endif
bool common_hal_alarm_woken_from_sleep(void) {
nrf_sleep_source_t cause = _get_wakeup_cause();
#ifdef NRF_DEBUG_PRINT
if (cause != NRF_SLEEP_WAKEUP_UNDEFINED) {
//print_wakeup_cause(cause);
}
#endif
return (cause == NRF_SLEEP_WAKEUP_GPIO || cause == NRF_SLEEP_WAKEUP_TIMER
|| cause == NRF_SLEEP_WAKEUP_TOUCHPAD);
nrf_sleep_source_t cause = _get_wakeup_cause();
#ifdef NRF_DEBUG_PRINT
if (cause != NRF_SLEEP_WAKEUP_UNDEFINED) {
// print_wakeup_cause(cause);
}
#endif
return cause == NRF_SLEEP_WAKEUP_GPIO || cause == NRF_SLEEP_WAKEUP_TIMER
|| cause == NRF_SLEEP_WAKEUP_TOUCHPAD;
}
STATIC mp_obj_t _get_wake_alarm(size_t n_alarms, const mp_obj_t *alarms) {
@ -131,7 +129,7 @@ STATIC mp_obj_t _get_wake_alarm(size_t n_alarms, const mp_obj_t *alarms) {
return alarm_pin_pinalarm_get_wakeup_alarm(n_alarms, alarms);
}
default:
break;
break;
}
return mp_const_none;
}
@ -156,47 +154,48 @@ void system_on_idle_until_alarm(int64_t timediff_ms, uint32_t prescaler) {
uint64_t start_tick = 0, end_tick = 0;
int64_t tickdiff;
#if defined(MICROPY_QSPI_CS)
#if defined(MICROPY_QSPI_CS)
qspi_flash_enter_sleep();
#endif
#endif
if (timediff_ms != -1) {
have_timeout = true;
#if 0
int64_t now = common_hal_time_monotonic_ms();
dbg_printf("now_ms=%ld timediff_ms=%ld\r\n", (long)now, (long)timediff_ms);
#endif
if (timediff_ms < 0) timediff_ms = 0;
if (prescaler == 0) {
// 1 tick = 1/1024 sec = 1000/1024 ms
// -> 1 ms = 1024/1000 ticks
tickdiff = (mp_uint_t)(timediff_ms * 1024 / 1000); // ms -> ticks
#if 0
int64_t now = common_hal_time_monotonic_ms();
dbg_printf("now_ms=%ld timediff_ms=%ld\r\n", (long)now, (long)timediff_ms);
#endif
if (timediff_ms < 0) {
timediff_ms = 0;
}
if (prescaler == 0) {
// 1 tick = 1/1024 sec = 1000/1024 ms
// -> 1 ms = 1024/1000 ticks
tickdiff = (mp_uint_t)(timediff_ms * 1024 / 1000); // ms -> ticks
} else {
// 1 tick = prescaler/1024 sec = prescaler*1000/1024 ms
// -> 1ms = 1024/(1000*prescaler) ticks
tickdiff = (mp_uint_t)(timediff_ms * 1024 / (1000 * prescaler));
}
start_tick = port_get_raw_ticks(NULL);
end_tick = start_tick + tickdiff;
}
else {
// 1 tick = prescaler/1024 sec = prescaler*1000/1024 ms
// -> 1ms = 1024/(1000*prescaler) ticks
tickdiff = (mp_uint_t)(timediff_ms * 1024 / (1000 * prescaler));
}
start_tick = port_get_raw_ticks(NULL);
end_tick = start_tick + tickdiff;
}
#if 0
#if 0
dbg_printf("start_tick=%ld end_tick=%ld have_timeout=%c\r\n", (long)start_tick, (long)end_tick, have_timeout ? 'T' : 'F');
#endif
#endif
int64_t remaining;
sleepmem_wakeup_event = SLEEPMEM_WAKEUP_BY_NONE;
sleepmem_wakeup_pin = WAKEUP_PIN_UNDEF;
sleepmem_wakeup_pin = WAKEUP_PIN_UNDEF;
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
int ct = 40;
char reason = '?';
#define WAKEUP_REASON(x) reason = (x)
#else
#else
#define WAKEUP_REASON(x)
#endif
#endif
while(1) {
while (1) {
if (mp_hal_is_interrupted()) {
WAKEUP_REASON('I');
break;
@ -222,12 +221,12 @@ void system_on_idle_until_alarm(int64_t timediff_ms, uint32_t prescaler) {
}
// Idle until an interrupt happens.
port_idle_until_interrupt();
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
if (ct > 0) {
dbg_printf("_");
--ct;
}
#endif
#endif
if (have_timeout) {
remaining = end_tick - port_get_raw_ticks(NULL);
if (remaining <= 0) {
@ -237,25 +236,24 @@ void system_on_idle_until_alarm(int64_t timediff_ms, uint32_t prescaler) {
}
}
}
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
dbg_printf("%c\r\n", reason);
#endif
#endif
#if defined(MICROPY_QSPI_CS)
#if defined(MICROPY_QSPI_CS)
qspi_flash_exit_sleep();
#endif
#endif
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
tickdiff = port_get_raw_ticks(NULL) - start_tick;
double sec;
if (prescaler == 0) {
sec = (double)tickdiff / 1024;
}
else {
} else {
sec = (double)(tickdiff * prescaler) / 1024;
}
dbg_printf("lapse %6.1f sec\r\n", sec);
#endif
#endif
}
mp_obj_t common_hal_alarm_light_sleep_until_alarms(size_t n_alarms, const mp_obj_t *alarms) {
@ -263,17 +261,16 @@ mp_obj_t common_hal_alarm_light_sleep_until_alarms(size_t n_alarms, const mp_obj
alarm_time_timealarm_clear_wakeup_time();
_setup_sleep_alarms(false, n_alarms, alarms);
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
dbg_printf("\r\nlight sleep...");
#endif
#endif
int64_t timediff_ms = alarm_time_timealarm_get_wakeup_timediff_ms();
system_on_idle_until_alarm(timediff_ms, 0);
if (mp_hal_is_interrupted()) {
wake_alarm = mp_const_none;
}
else {
} else {
wake_alarm = _get_wake_alarm(n_alarms, alarms);
}
alarm_reset();
@ -291,24 +288,26 @@ void NORETURN common_hal_alarm_enter_deep_sleep(void) {
alarm_pin_pinalarm_prepare_for_deep_sleep();
alarm_time_timealarm_prepare_for_deep_sleep();
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
dbg_printf("\r\ndeep sleep...");
#endif
#endif
int64_t timediff_ms = alarm_time_timealarm_get_wakeup_timediff_ms();
tick_set_prescaler(PRESCALER_VALUE_IN_DEEP_SLEEP -1);
#ifdef NRF_DEBUG_PRINT
dbg_check_RTCprescaler(); //XXX
#endif
tick_set_prescaler(PRESCALER_VALUE_IN_DEEP_SLEEP - 1);
#ifdef NRF_DEBUG_PRINT
dbg_check_RTCprescaler(); // XXX
#endif
system_on_idle_until_alarm(timediff_ms, PRESCALER_VALUE_IN_DEEP_SLEEP);
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
dbg_printf("RESET...\r\n\r\n");
#endif
#endif
reset_cpu();
// should not reach here..
while(1) ;
while (1) {
;
}
}
// old version deep sleep code that was used in common_hal_alarm_enter_deep_sleep()
@ -316,15 +315,14 @@ void NORETURN common_hal_alarm_enter_deep_sleep(void) {
#if 0
void OLD_go_system_off(void) {
sleepmem_wakeup_event = SLEEPMEM_WAKEUP_BY_NONE;
sleepmem_wakeup_pin = WAKEUP_PIN_UNDEF;
sleepmem_wakeup_pin = WAKEUP_PIN_UNDEF;
uint8_t sd_enabled;
sd_softdevice_is_enabled(&sd_enabled);
set_memory_retention();
dbg_printf("OLD go system off.. %d\r\n", sd_enabled);
if (sd_enabled) {
sd_power_system_off();
}
else {
} else {
NRF_POWER->SYSTEMOFF = 1;
}
}
@ -334,9 +332,9 @@ void common_hal_alarm_pretending_deep_sleep(void) {
alarm_pin_pinalarm_prepare_for_deep_sleep();
alarm_time_timealarm_prepare_for_deep_sleep();
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
dbg_printf("\r\npretending to deep sleep...");
#endif
#endif
int64_t timediff_ms = alarm_time_timealarm_get_wakeup_timediff_ms();
system_on_idle_until_alarm(timediff_ms, 0);

64
ports/nrf/common-hal/alarm/pin/PinAlarm.c
View File

@ -82,12 +82,12 @@ bool common_hal_alarm_pin_pinalarm_get_pull(alarm_pin_pinalarm_obj_t *self) {
static void pinalarm_gpiote_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
++_pinhandler_gpiote_count;
sleepmem_wakeup_event = SLEEPMEM_WAKEUP_BY_PIN;
sleepmem_wakeup_pin = pin & 0xFF;
sleepmem_wakeup_pin = pin & 0xFF;
}
bool alarm_pin_pinalarm_woke_us_up(void) {
return (sleepmem_wakeup_event == SLEEPMEM_WAKEUP_BY_PIN &&
sleepmem_wakeup_pin != WAKEUP_PIN_UNDEF);
return sleepmem_wakeup_event == SLEEPMEM_WAKEUP_BY_PIN &&
sleepmem_wakeup_pin != WAKEUP_PIN_UNDEF;
}
mp_obj_t alarm_pin_pinalarm_get_wakeup_alarm(size_t n_alarms, const mp_obj_t *alarms) {
@ -96,8 +96,8 @@ mp_obj_t alarm_pin_pinalarm_get_wakeup_alarm(size_t n_alarms, const mp_obj_t *al
if (!mp_obj_is_type(alarms[i], &alarm_pin_pinalarm_type)) {
continue;
}
alarm_pin_pinalarm_obj_t *alarm = MP_OBJ_TO_PTR(alarms[i]);
if (alarm->pin->number == sleepmem_wakeup_pin) {
alarm_pin_pinalarm_obj_t *alarm = MP_OBJ_TO_PTR(alarms[i]);
if (alarm->pin->number == sleepmem_wakeup_pin) {
return alarms[i];
}
}
@ -106,8 +106,8 @@ mp_obj_t alarm_pin_pinalarm_get_wakeup_alarm(size_t n_alarms, const mp_obj_t *al
alarm->pin = NULL;
// Map the pin number back to a pin object.
for (size_t i = 0; i < mcu_pin_globals.map.used; i++) {
const mcu_pin_obj_t* pin_obj = MP_OBJ_TO_PTR(mcu_pin_globals.map.table[i].value);
if ((size_t) pin_obj->number == sleepmem_wakeup_pin) {
const mcu_pin_obj_t *pin_obj = MP_OBJ_TO_PTR(mcu_pin_globals.map.table[i].value);
if ((size_t)pin_obj->number == sleepmem_wakeup_pin) {
alarm->pin = mcu_pin_globals.map.table[i].value;
break;
}
@ -130,8 +130,8 @@ void alarm_pin_pinalarm_reset(void) {
continue;
}
reset_pin_number(i);
nrfx_gpiote_in_event_disable((nrfx_gpiote_pin_t)i);
nrfx_gpiote_in_uninit((nrfx_gpiote_pin_t)i);
nrfx_gpiote_in_event_disable((nrfx_gpiote_pin_t)i);
nrfx_gpiote_in_uninit((nrfx_gpiote_pin_t)i);
}
high_alarms = 0;
@ -141,7 +141,7 @@ void alarm_pin_pinalarm_reset(void) {
static void configure_pins_for_sleep(void) {
nrfx_err_t err;
if ( nrfx_gpiote_is_init() ) {
if (nrfx_gpiote_is_init()) {
nrfx_gpiote_uninit();
}
err = nrfx_gpiote_init(NRFX_GPIOTE_CONFIG_IRQ_PRIORITY);
@ -157,7 +157,7 @@ static void configure_pins_for_sleep(void) {
.hi_accuracy = true,
.skip_gpio_setup = false
};
for(size_t i = 0; i < 64; ++i) {
for (size_t i = 0; i < 64; ++i) {
uint64_t mask = 1ull << i;
if (((high_alarms & mask) == 0) && ((low_alarms & mask) == 0)) {
continue;
@ -165,28 +165,26 @@ static void configure_pins_for_sleep(void) {
if (((high_alarms & mask) != 0) && ((low_alarms & mask) == 0)) {
cfg.sense = NRF_GPIOTE_POLARITY_LOTOHI;
cfg.pull = ((pull_pins & mask) != 0) ?
NRF_GPIO_PIN_PULLDOWN : NRF_GPIO_PIN_NOPULL;
}
else
NRF_GPIO_PIN_PULLDOWN : NRF_GPIO_PIN_NOPULL;
} else
if (((high_alarms & mask) == 0) && ((low_alarms & mask) != 0)) {
cfg.sense = NRF_GPIOTE_POLARITY_HITOLO;
cfg.pull = ((pull_pins & mask) != 0) ?
NRF_GPIO_PIN_PULLUP : NRF_GPIO_PIN_NOPULL;
}
else {
NRF_GPIO_PIN_PULLUP : NRF_GPIO_PIN_NOPULL;
} else {
cfg.sense = NRF_GPIOTE_POLARITY_TOGGLE;
cfg.pull = NRF_GPIO_PIN_NOPULL;
}
err = nrfx_gpiote_in_init((nrfx_gpiote_pin_t)i, &cfg,
pinalarm_gpiote_handler);
assert(err == NRFX_SUCCESS);
pinalarm_gpiote_handler);
assert(err == NRFX_SUCCESS);
nrfx_gpiote_in_event_enable((nrfx_gpiote_pin_t)i, true);
if (((high_alarms & mask) != 0) && ((low_alarms & mask) == 0)) {
nrf_gpio_cfg_sense_set((uint32_t)i, NRF_GPIO_PIN_SENSE_HIGH);
}
}
if (((high_alarms & mask) == 0) && ((low_alarms & mask) != 0)) {
nrf_gpio_cfg_sense_set((uint32_t)i, NRF_GPIO_PIN_SENSE_LOW);
}
}
}
}
@ -200,10 +198,10 @@ void alarm_pin_pinalarm_set_alarms(bool deep_sleep, size_t n_alarms, const mp_ob
if (!mp_obj_is_type(alarms[i], &alarm_pin_pinalarm_type)) {
continue;
}
alarm_pin_pinalarm_obj_t *alarm = MP_OBJ_TO_PTR(alarms[i]);
alarm_pin_pinalarm_obj_t *alarm = MP_OBJ_TO_PTR(alarms[i]);
pin_number = alarm->pin->number;
//dbg_printf("alarm_pin_pinalarm_set_alarms(pin#=%d, val=%d, pull=%d)\r\n", pin_number, alarm->value, alarm->pull);
// dbg_printf("alarm_pin_pinalarm_set_alarms(pin#=%d, val=%d, pull=%d)\r\n", pin_number, alarm->value, alarm->pull);
if (alarm->value) {
high_alarms |= 1ull << pin_number;
high_count++;
@ -218,25 +216,23 @@ void alarm_pin_pinalarm_set_alarms(bool deep_sleep, size_t n_alarms, const mp_ob
if (pin_number != -1) {
if (!deep_sleep) {
configure_pins_for_sleep();
}
else {
} else {
// we don't setup gpio HW here but do them in
// alarm_pin_pinalarm_prepare_for_deep_sleep() below
reset_reason_saved = 0;
pins_configured = false;
reset_reason_saved = 0;
pins_configured = false;
}
}
else {
//dbg_printf("alarm_pin_pinalarm_set_alarms() no valid pins\r\n");
} else {
// dbg_printf("alarm_pin_pinalarm_set_alarms() no valid pins\r\n");
}
}
void alarm_pin_pinalarm_prepare_for_deep_sleep(void) {
if (!pins_configured) {
configure_pins_for_sleep();
pins_configured = true;
#ifdef NRF_DEBUG_PRINT
//dbg_dump_GPIOregs();
#endif
pins_configured = true;
#ifdef NRF_DEBUG_PRINT
// dbg_dump_GPIOregs();
#endif
}
}

6
ports/nrf/common-hal/alarm/time/TimeAlarm.c
View File

@ -55,10 +55,10 @@ mp_obj_t alarm_time_timealarm_get_wakeup_alarm(size_t n_alarms, const mp_obj_t *
}
bool alarm_time_timealarm_woke_us_up(void) {
return sleepmem_wakeup_event == SLEEPMEM_WAKEUP_BY_TIMER;
return sleepmem_wakeup_event == SLEEPMEM_WAKEUP_BY_TIMER;
}
int64_t wakeup_time_saved =0;
int64_t wakeup_time_saved = 0;
int64_t alarm_time_timealarm_get_wakeup_timediff_ms(void) {
if (wakeup_time_saved == 0) {
@ -88,7 +88,7 @@ void alarm_time_timealarm_set_alarms(bool deep_sleep, size_t n_alarms, const mp_
if (timealarm_set) {
mp_raise_ValueError(translate("Only one alarm.time alarm can be set."));
}
timealarm = MP_OBJ_TO_PTR(alarms[i]);
timealarm = MP_OBJ_TO_PTR(alarms[i]);
timealarm_set = true;
}
if (!timealarm_set) {

2
ports/nrf/common-hal/alarm/touch/TouchAlarm.c
View File

@ -28,7 +28,7 @@
#include "shared-bindings/alarm/touch/TouchAlarm.h"
#include "shared-bindings/microcontroller/__init__.h"
//static volatile bool woke_up = false;
// static volatile bool woke_up = false;
void common_hal_alarm_touch_touchalarm_construct(alarm_touch_touchalarm_obj_t *self, const mcu_pin_obj_t *pin) {
mp_raise_NotImplementedError(NULL);

18
ports/nrf/common-hal/countio/Counter.c
View File

@ -13,8 +13,8 @@ static void _intr_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
self->count += 1;
}
void common_hal_countio_counter_construct(countio_counter_obj_t* self,
const mcu_pin_obj_t* pin_a) {
void common_hal_countio_counter_construct(countio_counter_obj_t *self,
const mcu_pin_obj_t *pin_a) {
self->pin_a = pin_a->number;
_countio_objs[self->pin_a] = self;
@ -36,11 +36,11 @@ void common_hal_countio_counter_construct(countio_counter_obj_t* self,
}
bool common_hal_countio_counter_deinited(countio_counter_obj_t* self) {
bool common_hal_countio_counter_deinited(countio_counter_obj_t *self) {
return self->pin_a == NO_PIN;
}
void common_hal_countio_counter_deinit(countio_counter_obj_t* self) {
void common_hal_countio_counter_deinit(countio_counter_obj_t *self) {
if (common_hal_countio_counter_deinited(self)) {
return;
}
@ -52,15 +52,15 @@ void common_hal_countio_counter_deinit(countio_counter_obj_t* self) {
self->pin_a = NO_PIN;
}
mp_int_t common_hal_countio_counter_get_count(countio_counter_obj_t* self) {
mp_int_t common_hal_countio_counter_get_count(countio_counter_obj_t *self) {
return self->count;
}
void common_hal_countio_counter_set_count(countio_counter_obj_t* self,
mp_int_t new_count) {
void common_hal_countio_counter_set_count(countio_counter_obj_t *self,
mp_int_t new_count) {
self->count = new_count;
}
void common_hal_countio_counter_reset(countio_counter_obj_t* self){
self->count = 0;
void common_hal_countio_counter_reset(countio_counter_obj_t *self) {
self->count = 0;
}

2
ports/nrf/common-hal/countio/__init__.c
View File

@ -1 +1 @@
//No countio module functions
// No countio module functions

28
ports/nrf/common-hal/microcontroller/Processor.c
View File

@ -129,22 +129,18 @@ void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) {
mcu_reset_reason_t common_hal_mcu_processor_get_reset_reason(void) {
mcu_reset_reason_t r = RESET_REASON_UNKNOWN;
if (reset_reason_saved == 0) {
r = RESET_REASON_POWER_ON;
}
else if (reset_reason_saved & POWER_RESETREAS_RESETPIN_Msk) {
r = RESET_REASON_RESET_PIN;
}
else if (reset_reason_saved & POWER_RESETREAS_DOG_Msk) {
r = RESET_REASON_WATCHDOG;
}
else if (reset_reason_saved & POWER_RESETREAS_SREQ_Msk) {
r = RESET_REASON_SOFTWARE;
}
else if ((reset_reason_saved & POWER_RESETREAS_OFF_Msk) ||
(reset_reason_saved & POWER_RESETREAS_LPCOMP_Msk) ||
(reset_reason_saved & POWER_RESETREAS_NFC_Msk) ||
(reset_reason_saved & POWER_RESETREAS_VBUS_Msk)) {
r = RESET_REASON_DEEP_SLEEP_ALARM;
r = RESET_REASON_POWER_ON;
} else if (reset_reason_saved & POWER_RESETREAS_RESETPIN_Msk) {
r = RESET_REASON_RESET_PIN;
} else if (reset_reason_saved & POWER_RESETREAS_DOG_Msk) {
r = RESET_REASON_WATCHDOG;
} else if (reset_reason_saved & POWER_RESETREAS_SREQ_Msk) {
r = RESET_REASON_SOFTWARE;
} else if ((reset_reason_saved & POWER_RESETREAS_OFF_Msk) ||
(reset_reason_saved & POWER_RESETREAS_LPCOMP_Msk) ||
(reset_reason_saved & POWER_RESETREAS_NFC_Msk) ||
(reset_reason_saved & POWER_RESETREAS_VBUS_Msk)) {
r = RESET_REASON_DEEP_SLEEP_ALARM;
}
return r;
}

4
ports/nrf/common-hal/rotaryio/IncrementalEncoder.c
View File

@ -42,8 +42,8 @@ static void _intr_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
}
uint8_t new_state =
((uint8_t) nrf_gpio_pin_read(self->pin_a) << 1) |
(uint8_t) nrf_gpio_pin_read(self->pin_b);
((uint8_t)nrf_gpio_pin_read(self->pin_a) << 1) |
(uint8_t)nrf_gpio_pin_read(self->pin_b);
shared_module_softencoder_state_update(self, new_state);
}

141
ports/nrf/supervisor/debug_uart.c
View File

@ -50,20 +50,20 @@ extern uint32_t reset_reason_saved;
const nrfx_uarte_t _dbg_uart_inst = NRFX_UARTE_INSTANCE(1);
static int _dbg_uart_initialized = 0;
#define DBG_PBUF_LEN 80
static char _dbg_pbuf[DBG_PBUF_LEN+1];
static char _dbg_pbuf[DBG_PBUF_LEN + 1];
void _debug_uart_uninit(void) {
nrf_gpio_cfg(DEBUG_UART_TXPIN,
NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_NOSENSE);
NRF_GPIO_PIN_DIR_INPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_NOSENSE);
nrfx_uarte_uninit(&_dbg_uart_inst);
}
void _debug_uart_init(void) {
//if (_dbg_uart_initialized) return;
// if (_dbg_uart_initialized) return;
nrfx_uarte_config_t config = {
.pseltxd = DEBUG_UART_TXPIN,
.pselrxd = DEBUG_UART_RXPIN,
@ -80,30 +80,29 @@ void _debug_uart_init(void) {
nrfx_uarte_init(&_dbg_uart_inst, &config, NULL);
// drive config
nrf_gpio_cfg(config.pseltxd,
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_PULLUP, // orig=NOPULL
NRF_GPIO_PIN_H0H1, // orig=S0S1
NRF_GPIO_PIN_NOSENSE);
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_DISCONNECT,
NRF_GPIO_PIN_PULLUP, // orig=NOPULL
NRF_GPIO_PIN_H0H1, // orig=S0S1
NRF_GPIO_PIN_NOSENSE);
_dbg_uart_initialized = 1;
return;
}
void _debug_print_substr(const char* text, uint32_t length) {
char* data = (char*)text;
int siz;
while(length != 0) {
void _debug_print_substr(const char *text, uint32_t length) {
char *data = (char *)text;
int siz;
while (length != 0) {
if (length <= DBG_PBUF_LEN) {
siz = length;
}
else {
siz = DBG_PBUF_LEN;
}
memcpy(_dbg_pbuf, data, siz);
_dbg_pbuf[siz] = 0;
nrfx_uarte_tx(&_dbg_uart_inst, (uint8_t const*)_dbg_pbuf, siz);
data += siz;
length -= siz;
siz = length;
} else {
siz = DBG_PBUF_LEN;
}
memcpy(_dbg_pbuf, data, siz);
_dbg_pbuf[siz] = 0;
nrfx_uarte_tx(&_dbg_uart_inst, (uint8_t const *)_dbg_pbuf, siz);
data += siz;
length -= siz;
}
}
@ -121,7 +120,7 @@ int dbg_printf(const char *fmt, ...) {
void dbg_dump_RTCreg(void) {
dbg_printf("\r\nRTC2\r\n");
NRF_RTC_Type *r = rtc_instance.p_reg;
NRF_RTC_Type *r = rtc_instance.p_reg;
dbg_printf("PRESCALER=%08X, ", (int)r->PRESCALER);
dbg_printf("COUNTER=%08X ", (int)r->COUNTER);
dbg_printf("INTENSET=%08X ", (int)r->INTENSET);
@ -131,19 +130,21 @@ void dbg_dump_RTCreg(void) {
}
int dbg_check_RTCprescaler(void) {
NRF_RTC_Type *r = rtc_instance.p_reg;
NRF_RTC_Type *r = rtc_instance.p_reg;
if ((int)r->PRESCALER == 0) {
dbg_printf("****** PRESCALER == 0\r\n");
return -1;
return -1;
}
return 0;
}
void dbg_dump_RAMreg(void) {
int i;
for(i = 0; i <= 8; ++i) {
for (i = 0; i <= 8; ++i) {
dbg_printf(" RAM%d:%08X", i, (int)(NRF_POWER->RAM[i].POWER));
if (i==4) dbg_printf("\r\n");
if (i == 4) {
dbg_printf("\r\n");
}
}
dbg_printf("\r\n");
}
@ -154,52 +155,58 @@ void dbg_dump_GPIOregs(void) {
NRF_GPIO_Type *gpio[] = { NRF_P0, NRF_P1 };
const char cnf_pull_chr[] = "-D*U"; // pull down, pull up
const char cnf_sense_chr[] = "-?HL"; // sense high, sense low
for(port=0, col=0; port<=1; ++port) {
for(i=0; i<32; ++i) {
uint32_t cnf = gpio[port]->PIN_CNF[i];
if (cnf != 0x0002) { // changed from default value
dbg_printf("[%d_%02d]:%c%c%c%d%c ", port, i,
(cnf & 1) ? 'O' : 'I', // output, input
(cnf & 2) ? 'd' : 'c', // disconnected, connected
cnf_pull_chr[(cnf >> 2) & 3],
(int)((cnf >> 8) & 7), // drive config 0-7
cnf_sense_chr[(cnf >> 16) & 3]);
if (++col >= 6) {
dbg_printf("\r\n");
col = 0;
}
for (port = 0, col = 0; port <= 1; ++port) {
for (i = 0; i < 32; ++i) {
uint32_t cnf = gpio[port]->PIN_CNF[i];
if (cnf != 0x0002) { // changed from default value
dbg_printf("[%d_%02d]:%c%c%c%d%c ", port, i,
(cnf & 1) ? 'O' : 'I', // output, input
(cnf & 2) ? 'd' : 'c', // disconnected, connected
cnf_pull_chr[(cnf >> 2) & 3],
(int)((cnf >> 8) & 7), // drive config 0-7
cnf_sense_chr[(cnf >> 16) & 3]);
if (++col >= 6) {
dbg_printf("\r\n");
col = 0;
}
}
}
}
if (col > 0) {
dbg_printf("\r\n");
}
if (col > 0) dbg_printf("\r\n");
dbg_printf("GPIOTE\r\n");
NRF_GPIOTE_Type const *reg = NRF_GPIOTE;
const char config_mode_chr[] = "-E-T"; // event, task
const char config_pol_chr[] = "-HLT"; // low-to-Hi, hi-to-Low, Toggle
const char config_outinit_chr[] = "01"; // initial value is 0 or 1
for(i=0, col=0; i<8; ++i) {
for (i = 0, col = 0; i < 8; ++i) {
uint32_t conf = reg->CONFIG[i];
if (conf != 0) { // changed from default value
dbg_printf("CONFIG[%d]:%d_%02d,%c%c%c ", i,
(int)((conf >> 13) & 1), (int)((conf >> 8) & 0x1F),
config_mode_chr[conf & 3],
config_pol_chr[(conf >> 16) & 3],
(conf & 3) == 3 ?
config_outinit_chr[(conf >> 20) & 1] : '-');
if (++col >= 4) {
dbg_printf("\r\n");
col = 0;
if (conf != 0) { // changed from default value
dbg_printf("CONFIG[%d]:%d_%02d,%c%c%c ", i,
(int)((conf >> 13) & 1), (int)((conf >> 8) & 0x1F),
config_mode_chr[conf & 3],
config_pol_chr[(conf >> 16) & 3],
(conf & 3) == 3 ?
config_outinit_chr[(conf >> 20) & 1] : '-');
if (++col >= 4) {
dbg_printf("\r\n");
col = 0;
}
}
}
if (col > 0) {
dbg_printf("\r\n");
}
if (col > 0) dbg_printf("\r\n");
for(i=0; i<8; ++i) {
for (i = 0; i < 8; ++i) {
dbg_printf("EVENTS_IN[%d]:%X ", i, (int)(reg->EVENTS_IN[i]));
if ((i & 3) == 3) dbg_printf("\r\n");
if ((i & 3) == 3) {
dbg_printf("\r\n");
}
}
dbg_printf("EVENTS_PORT:%X INTENSET:%08X\r\n",
(int)(reg->EVENTS_PORT), (int)(reg->INTENSET));
(int)(reg->EVENTS_PORT), (int)(reg->INTENSET));
}
void dbg_dumpQSPIreg(void) {
@ -207,22 +214,22 @@ void dbg_dumpQSPIreg(void) {
dbg_printf("QSPI\r\n");
r = NRF_QSPI->IFCONFIG0;
dbg_printf("IFCONFIG0 READ=%ld write=%ld ADDR=%ld DPM=%ld PPSIZE=%ld\r\n",
r & 7, (r >> 3) & 7, (r >> 6) & 1, (r >> 7) & 1, (r >> 12) & 1);
r & 7, (r >> 3) & 7, (r >> 6) & 1, (r >> 7) & 1, (r >> 12) & 1);
r = NRF_QSPI->IFCONFIG1;
dbg_printf("IFCONFIG1 SCKDELAY=%ld SPIMODE=%ld SCKFREQ=%ld\r\n",
r & 0xFF, (r >> 25) & 1, (r >> 28) & 0xF);
r & 0xFF, (r >> 25) & 1, (r >> 28) & 0xF);
r = NRF_QSPI->STATUS;
dbg_printf("STATUS DPM=%ld READY=%ld SREG=0x%02lX\r\n",
(r >> 2) & 1, (r >> 3) & 1, (r >> 24) & 0xFF);
(r >> 2) & 1, (r >> 3) & 1, (r >> 24) & 0xFF);
r = NRF_QSPI->DPMDUR;
dbg_printf("DPMDUR ENTER=%ld EXIT=%ld\r\n", r & 0xFFFF, (r >> 16) & 0xFFFF);
}
void dbg_dump_reset_reason(void) {
int reset_reason = (int)common_hal_mcu_processor_get_reset_reason();
const char* rr_str[] = {
"POWER_ON", "BROWNOUT", "SOFTWARE", "DEEPSLEEPALARM",
"RESET_PIN", "WATCHDOG", "UNKNOWN"
const char *rr_str[] = {
"POWER_ON", "BROWNOUT", "SOFTWARE", "DEEPSLEEPALARM",
"RESET_PIN", "WATCHDOG", "UNKNOWN"
};
dbg_printf("reset_reason=%s\r\n", rr_str[reset_reason]);
}

4
ports/nrf/supervisor/port.c
View File

@ -259,9 +259,9 @@ void reset_port(void) {
reset_all_pins();
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
_debug_uart_init();
#endif
#endif
}
void reset_to_bootloader(void) {

60
ports/nrf/supervisor/qspi_flash.c
View File

@ -213,11 +213,11 @@ void spi_flash_init(void) {
.readoc = NRF_QSPI_READOC_FASTREAD,
.writeoc = NRF_QSPI_WRITEOC_PP,
.addrmode = NRF_QSPI_ADDRMODE_24BIT,
#ifdef QSPI_FLASH_POWERDOWN
#ifdef QSPI_FLASH_POWERDOWN
.dpmconfig = true
#else
#else
.dpmconfig = false
#endif
#endif
},
.phy_if = {
.sck_freq = NRF_QSPI_FREQ_32MDIV16, // Start at a slow 2MHz and speed up once we know what we're talking to.
@ -243,12 +243,12 @@ void spi_flash_init(void) {
// No callback for blocking API
nrfx_qspi_init(&qspi_cfg, NULL, NULL);
#ifdef QSPI_FLASH_POWERDOWN
#ifdef QSPI_FLASH_POWERDOWN
// If pin-reset while flash is in power-down mode,
// the flash cannot accept any commands. Send CMD_WAKE to release it.
spi_flash_write_command(CMD_WAKE, NULL, 0);
NRFX_DELAY_US(WAIT_AFTER_DPM_EXIT);
#endif
#endif
}
void spi_flash_init_device(const external_flash_device *device) {
@ -274,59 +274,59 @@ void spi_flash_init_device(const external_flash_device *device) {
}
void qspi_flash_enter_sleep(void) {
#ifdef QSPI_FLASH_POWERDOWN
#ifdef QSPI_FLASH_POWERDOWN
uint32_t r;
NRF_QSPI->DPMDUR =
((DUR_DPM_ENTER & 0xFFFF) << 16) | (DUR_DPM_EXIT & 0xFFFF);
// set sck_delay tempolarily
r = NRF_QSPI->IFCONFIG1;
sck_delay_saved = (r & QSPI_IFCONFIG1_SCKDELAY_Msk)
>> QSPI_IFCONFIG1_SCKDELAY_Pos;
>> QSPI_IFCONFIG1_SCKDELAY_Pos;
NRF_QSPI->IFCONFIG1
= (NRF_QSPI->IFCONFIG1 & ~QSPI_IFCONFIG1_SCKDELAY_Msk)
| (SCK_DELAY << QSPI_IFCONFIG1_SCKDELAY_Pos);
| (SCK_DELAY << QSPI_IFCONFIG1_SCKDELAY_Pos);
// enabling IFCONFIG0.DPMENABLE here won't work.
// -> do it in spi_flash_init()
//NRF_QSPI->IFCONFIG0 |= QSPI_IFCONFIG0_DPMENABLE_Msk;
//dbg_dumpQSPIreg();
// NRF_QSPI->IFCONFIG0 |= QSPI_IFCONFIG0_DPMENABLE_Msk;
// dbg_dumpQSPIreg();
// enter deep power-down mode (DPM)
NRF_QSPI->IFCONFIG1 |= QSPI_IFCONFIG1_DPMEN_Msk;
NRFX_DELAY_US(WAIT_AFTER_DPM_ENTER);
if (!(NRF_QSPI->STATUS & QSPI_STATUS_DPM_Msk)) {
#ifdef NRF_DEBUG_PRINT
#ifdef NRF_DEBUG_PRINT
dbg_printf("qspi flash: DPM failed\r\n");
#endif
#endif
}
#endif
#endif
qspi_disable();
//dbg_dumpQSPIreg();
// dbg_dumpQSPIreg();
}
void qspi_flash_exit_sleep(void) {
qspi_enable();
#ifdef QSPI_FLASH_POWERDOWN
#ifdef QSPI_FLASH_POWERDOWN
if (NRF_QSPI->STATUS & QSPI_STATUS_DPM_Msk) {
// exit deep power-down mode
NRF_QSPI->IFCONFIG1 &= ~QSPI_IFCONFIG1_DPMEN_Msk;
NRFX_DELAY_US(WAIT_AFTER_DPM_EXIT);
NRFX_DELAY_US(WAIT_AFTER_DPM_EXIT);
if (NRF_QSPI->STATUS & QSPI_STATUS_DPM_Msk) {
#ifdef NRF_DEBUG_PRINT
dbg_printf("qspi flash: exiting DPM failed\r\n");
#endif
if (NRF_QSPI->STATUS & QSPI_STATUS_DPM_Msk) {
#ifdef NRF_DEBUG_PRINT
dbg_printf("qspi flash: exiting DPM failed\r\n");
#endif
}
// restore sck_delay
if (sck_delay_saved == 0) {
sck_delay_saved = 10; // default
}
NRF_QSPI->IFCONFIG1
= (NRF_QSPI->IFCONFIG1 & ~QSPI_IFCONFIG1_SCKDELAY_Msk)
| (sck_delay_saved << QSPI_IFCONFIG1_SCKDELAY_Pos);
}
// restore sck_delay
if (sck_delay_saved == 0) {
sck_delay_saved = 10; // default
}
NRF_QSPI->IFCONFIG1
= (NRF_QSPI->IFCONFIG1 & ~QSPI_IFCONFIG1_SCKDELAY_Msk)
| (sck_delay_saved << QSPI_IFCONFIG1_SCKDELAY_Pos);
}
//dbg_dumpQSPIreg();
#endif
// dbg_dumpQSPIreg();
#endif
}

2
ports/raspberrypi/boards/sparkfun_micromod_rp2040/pins.c
View File

@ -37,7 +37,7 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_BUS10), MP_ROM_PTR(&pin_GPIO25) }, // BUS10 alias
{ MP_ROM_QSTR(MP_QSTR_ADC_DP), MP_ROM_PTR(&pin_GPIO25) }, // ADC_DP alias
{ MP_ROM_QSTR(MP_QSTR_CAM_VSYNC), MP_ROM_PTR(&pin_GPIO25) }, // CAM_VSYNC alias
// NC - G11
// NC - G11
// PWM pins (PWM0,PWM1)
{ MP_ROM_QSTR(MP_QSTR_PWM0), MP_ROM_PTR(&pin_GPIO13) }, // GPIO13 - PWM0

2
ports/raspberrypi/common-hal/busio/I2C.c
View File

@ -162,7 +162,7 @@ void common_hal_busio_i2c_unlock(busio_i2c_obj_t *self) {
}
uint8_t common_hal_busio_i2c_write(busio_i2c_obj_t *self, uint16_t addr,
const uint8_t *data, size_t len, bool transmit_stop_bit) {
const uint8_t *data, size_t len, bool transmit_stop_bit) {
if (len == 0) {
// The RP2040 I2C peripheral will not perform 0 byte writes.
// So use bitbangio.I2C to do the write.

28
ports/raspberrypi/common-hal/imagecapture/ParallelImageCapture.c
View File

@ -44,7 +44,7 @@
// Define this to (1), and you can scope the instruction-pointer of the state machine on D26..28 (note the weird encoding though!)
#define DEBUG_STATE_MACHINE (0)
#if DEBUG_STATE_MACHINE
#define SIDE(x) ((x)<<8)
#define SIDE(x) ((x) << 8)
#else
#define SIDE(x) (0)
#endif
@ -61,10 +61,10 @@
/* 0 */ pio_encode_wait_gpio(0, vsync) | _0, \
/* 1 */ pio_encode_wait_gpio(1, vsync) | _1, \
/* .wrap_target */ \
/* 2 */ pio_encode_wait_gpio(1, href) | _2, \
/* 3 */ pio_encode_wait_gpio(1, pclk) | _3, \
/* 2 */ pio_encode_wait_gpio(1, href) | _2, \
/* 3 */ pio_encode_wait_gpio(1, pclk) | _3, \
/* 4 */ pio_encode_in(pio_pins, width) | _4, \
/* 5 */ pio_encode_wait_gpio(0, pclk) | _5, \
/* 5 */ pio_encode_wait_gpio(0, pclk) | _5, \
/* .wrap */ \
}
@ -73,8 +73,7 @@ void common_hal_imagecapture_parallelimagecapture_construct(imagecapture_paralle
const mcu_pin_obj_t *data_clock,
const mcu_pin_obj_t *vertical_sync,
const mcu_pin_obj_t *horizontal_reference,
int data_count)
{
int data_count) {
uint16_t imagecapture_code[] = IMAGECAPTURE_CODE(data_count, data_clock->number, vertical_sync->number, horizontal_reference->number);
@ -86,12 +85,12 @@ void common_hal_imagecapture_parallelimagecapture_construct(imagecapture_paralle
data0, data_count, // in pins
0, 0, // in pulls
NULL, 0, 0, 0, // set pins
#if DEBUG_STATE_MACHINE
#if DEBUG_STATE_MACHINE
&pin_GPIO26, 3, 7, 7, // sideset pins
#else
#else
NULL, 0, 0, 0, // sideset pins
#endif
(1<<vertical_sync->number) | (1<<horizontal_reference->number) | (1<<data_clock->number), // wait gpio pins
#endif
(1 << vertical_sync->number) | (1 << horizontal_reference->number) | (1 << data_clock->number), // wait gpio pins
true, // exclusive pin use
false, 32, false, // out settings
false, // wait for txstall
@ -103,21 +102,18 @@ void common_hal_imagecapture_parallelimagecapture_construct(imagecapture_paralle
rp2pio_statemachine_set_wrap(&self->state_machine, 2, 5);
}
void common_hal_imagecapture_parallelimagecapture_deinit(imagecapture_parallelimagecapture_obj_t *self)
{
void common_hal_imagecapture_parallelimagecapture_deinit(imagecapture_parallelimagecapture_obj_t *self) {
if (common_hal_imagecapture_parallelimagecapture_deinited(self)) {
return;
}
return common_hal_rp2pio_statemachine_deinit(&self->state_machine);
}
bool common_hal_imagecapture_parallelimagecapture_deinited(imagecapture_parallelimagecapture_obj_t *self)
{
bool common_hal_imagecapture_parallelimagecapture_deinited(imagecapture_parallelimagecapture_obj_t *self) {
return common_hal_rp2pio_statemachine_deinited(&self->state_machine);
}
void common_hal_imagecapture_parallelimagecapture_capture(imagecapture_parallelimagecapture_obj_t *self, void *buffer, size_t bufsize)
{
void common_hal_imagecapture_parallelimagecapture_capture(imagecapture_parallelimagecapture_obj_t *self, void *buffer, size_t bufsize) {
PIO pio = self->state_machine.pio;
uint sm = self->state_machine.state_machine;
uint8_t offset = rp2pio_statemachine_program_offset(&self->state_machine);

10
ports/raspberrypi/common-hal/pulseio/PulseIn.c
View File

@ -135,13 +135,13 @@ void common_hal_pulseio_pulsein_interrupt() {
result = level_count;
last_level = level;
level_count = 1;
// Pulses that are londger than MAX_PULSE will return MAX_PULSE
if (result > MAX_PULSE ) {
result = MAX_PULSE;
}
// Pulses that are londger than MAX_PULSE will return MAX_PULSE
if (result > MAX_PULSE) {
result = MAX_PULSE;
}
// ignore pulses that are too short
if (result <= MAX_PULSE && result > MIN_PULSE) {
self->buffer[buf_index] = (uint16_t) result;
self->buffer[buf_index] = (uint16_t)result;
buf_index++;
self->len++;
}

2
ports/raspberrypi/common-hal/rp2pio/StateMachine.c
View File

@ -813,5 +813,5 @@ void rp2pio_statemachine_set_wrap(rp2pio_statemachine_obj_t *self, uint wrap_tar
uint8_t sm = self->state_machine;
uint8_t offset = rp2pio_statemachine_program_offset(self);
pio_sm_set_wrap(self->pio, sm, offset+wrap_target, offset+wrap);
pio_sm_set_wrap(self->pio, sm, offset + wrap_target, offset + wrap);
}

28
ports/stm/common-hal/audiopwmio/PWMAudioOut.c
View File

@ -37,12 +37,12 @@ STATIC audiopwmio_pwmaudioout_obj_t *active_audio = NULL;
STATIC void set_pin(uint8_t channel, GPIO_PinState state) {
HAL_GPIO_WritePin(pin_port(active_audio->pin[channel]->port),
pin_mask(active_audio->pin[channel]->number), state);
pin_mask(active_audio->pin[channel]->number), state);
}
STATIC void toggle_pin(uint8_t channel) {
HAL_GPIO_TogglePin(pin_port(active_audio->pin[channel]->port),
pin_mask(active_audio->pin[channel]->number));
pin_mask(active_audio->pin[channel]->number));
}
STATIC void set_drive_mode(const mcu_pin_obj_t *pin, uint32_t mode) {
@ -93,10 +93,10 @@ STATIC bool fill_buffers(audiopwmio_pwmaudioout_obj_t *self) {
}
uint32_t num_samples = buffer_length / self->bytes_per_sample / self->sample_channel_count;
int16_t *buffer16 = (int16_t*)buffer;
int16_t *buffer16 = (int16_t *)buffer;
while (num_samples--) {
for (int8_t channel=0; channel < effective_channels; channel++) {
for (int8_t channel = 0; channel < effective_channels; channel++) {
int16_t val;
if (self->bytes_per_sample == 1) {
val = *buffer++ << 8;
@ -121,7 +121,7 @@ STATIC bool fill_buffers(audiopwmio_pwmaudioout_obj_t *self) {
if (self->len[channel] > 1) {
self->buffer[channel][self->buffer_length[channel]++] = self->len[channel];
if (replicate) {
self->buffer[1-channel][self->buffer_length[1-channel]++] = self->len[channel];
self->buffer[1 - channel][self->buffer_length[1 - channel]++] = self->len[channel];
}
self->len[channel] = 0;
}
@ -131,14 +131,14 @@ STATIC bool fill_buffers(audiopwmio_pwmaudioout_obj_t *self) {
}
}
} while (get_buffer_result == GET_BUFFER_MORE_DATA &&
(!self->buffer_length[0] || (self->pin[1] && !self->buffer_length[1])));
(!self->buffer_length[0] || (self->pin[1] && !self->buffer_length[1])));
if (get_buffer_result == GET_BUFFER_DONE) {
// It's the final countdown
for (int8_t channel=0; channel < effective_channels; channel++) {
for (int8_t channel = 0; channel < effective_channels; channel++) {
self->buffer[channel][self->buffer_length[channel]++] = self->len[channel];
if (replicate) {
self->buffer[1-channel][self->buffer_length[1-channel]++] = self->len[channel];
self->buffer[1 - channel][self->buffer_length[1 - channel]++] = self->len[channel];
}
}
@ -163,10 +163,8 @@ STATIC void move_to_beginning(uint16_t *buffer, uint16_t *buffer_length, uint16_
STATIC void pwmaudioout_event_handler(void) {
// Detect TIM Update event
if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET)
{
if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET)
{
if (__HAL_TIM_GET_FLAG(&tim_handle, TIM_FLAG_UPDATE) != RESET) {
if (__HAL_TIM_GET_IT_SOURCE(&tim_handle, TIM_IT_UPDATE) != RESET) {
__HAL_TIM_CLEAR_IT(&tim_handle, TIM_IT_UPDATE);
if (!active_audio || active_audio->paused) {
__HAL_TIM_DISABLE_IT(&tim_handle, TIM_IT_UPDATE);
@ -221,7 +219,7 @@ void audiopwmout_reset() {
// Caller validates that pins are free.
void common_hal_audiopwmio_pwmaudioout_construct(audiopwmio_pwmaudioout_obj_t *self,
const mcu_pin_obj_t *left_channel, const mcu_pin_obj_t *right_channel, uint16_t quiescent_value) {
const mcu_pin_obj_t *left_channel, const mcu_pin_obj_t *right_channel, uint16_t quiescent_value) {
// Set up the pin(s) for output
self->pin[0] = left_channel;
@ -306,7 +304,7 @@ void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t *self,
// Calculate period (TODO: supersample to 1 MHz?)
TIM_TypeDef *tim_instance = stm_peripherals_find_timer();
uint32_t source = stm_peripherals_timer_get_source_freq(tim_instance);
uint32_t prescaler = source/sample_rate;
uint32_t prescaler = source / sample_rate;
// Activate timer
active_audio = self;
@ -314,7 +312,7 @@ void common_hal_audiopwmio_pwmaudioout_play(audiopwmio_pwmaudioout_obj_t *self,
stm_peripherals_timer_preinit(tim_instance, 4, pwmaudioout_event_handler);
tim_handle.Instance = tim_instance;
tim_handle.Init.Period = 100; //immediately replaced.
tim_handle.Init.Period = 100; // immediately replaced.
tim_handle.Init.Prescaler = prescaler - 1;
tim_handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
tim_handle.Init.CounterMode = TIM_COUNTERMODE_UP;

2
ports/stm/common-hal/pwmio/PWMOut.c
View File

@ -183,7 +183,7 @@ pwmout_result_t common_hal_pwmio_pwmout_construct(pwmio_pwmout_obj_t *self,
}
}
//Channel/PWM init
// Channel/PWM init
self->chan_handle.OCMode = TIM_OCMODE_PWM1;
self->chan_handle.Pulse = timer_get_internal_duty(duty, period);
self->chan_handle.OCPolarity = TIM_OCPOLARITY_HIGH;

2
ports/unix/coverage-frzmpy/frzmpy1.py
View File

@ -1 +1 @@
print('frzmpy1')
print("frzmpy1")

2
ports/unix/coverage-frzmpy/frzmpy_pkg1/__init__.py
View File

@ -1,3 +1,3 @@
# test frozen package with __init__.py
print('frzmpy_pkg1.__init__')
print("frzmpy_pkg1.__init__")
x = 1

4
ports/unix/coverage-frzmpy/frzmpy_pkg2/mod.py
View File

@ -1,4 +1,6 @@
# test frozen package without __init__.py
print('frzmpy_pkg2.mod')
print("frzmpy_pkg2.mod")
class Foo:
x = 1

2
ports/unix/coverage-frzstr/frzstr1.py
View File

@ -1 +1 @@
print('frzstr1')
print("frzstr1")

2
ports/unix/coverage-frzstr/frzstr_pkg1/__init__.py
View File

@ -1,3 +1,3 @@
# test frozen package with __init__.py
print('frzstr_pkg1.__init__')
print("frzstr_pkg1.__init__")
x = 1

4
ports/unix/coverage-frzstr/frzstr_pkg2/mod.py
View File

@ -1,4 +1,6 @@
# test frozen package without __init__.py
print('frzstr_pkg2.mod')
print("frzstr_pkg2.mod")
class Foo:
x = 1

2
supervisor/shared/external_flash/spi_flash.c
View File

@ -56,7 +56,7 @@ static void flash_disable(void) {
common_hal_busio_spi_unlock(&supervisor_flash_spi_bus);
}
static bool transfer(uint8_t* command, uint32_t command_length, uint8_t* data_in, uint8_t* data_out, uint32_t data_length) {
static bool transfer(uint8_t *command, uint32_t command_length, uint8_t *data_in, uint8_t *data_out, uint32_t data_length) {
if (!flash_enable()) {
return false;
}

75
tools/codeformat.py
View File

@ -32,6 +32,7 @@ import itertools
import os
import pathlib
import re
import sys
import subprocess
# Relative to top-level repo dir.
@ -68,6 +69,45 @@ EXCLUSIONS = [
"tests/basics/*.py",
]
# None of the standard Python path matching routines implement the matching
# we want, which is most like git's "pathspec" version of globs.
# In particular, we want "**/" to match all directories.
# This routine is sufficient to work with the patterns we have, but
# subtle cases like character classes that contain meta-characters
# are not covered
def git_glob_to_regex(pat):
def transform(m):
m = m.group(0)
if m == "*":
return "[^/]*"
if m == "**":
return ".*"
if m == "?":
return "[^/]"
if m == ".":
return r"\."
return m
result = [transform(part) for part in re.finditer(r"(\*\*|[*?.]|[^*?.]+)", pat)]
return "(^" + "".join(result) + "$)"
# Create a single, complicated regular expression that matches exactly the
# files we want, accounting for the PATHS as well as the EXCLUSIONS.
path_re = (
""
# First a negative lookahead assertion that it doesn't match
# any of the EXCLUSIONS
+ "(?!"
+ "|".join(git_glob_to_regex(pat) for pat in EXCLUSIONS)
+ ")"
# Then a positive match for any of the PATHS
+ "(?:"
+ "|".join(git_glob_to_regex(pat) for pat in PATHS)
+ ")"
)
path_rx = re.compile(path_re)
# Path to repo top-level dir.
TOP = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
@ -76,15 +116,15 @@ UNCRUSTIFY_CFG = os.path.join(TOP, "tools/uncrustify.cfg")
C_EXTS = (".c", ".h")
PY_EXTS = (".py",)
# Transform a filename argument relative to the current directory into one
# relative to the TOP directory, which is what we need when checking against
# path_rx.
def relative_filename(arg):
return str(pathlib.Path(arg).resolve().relative_to(TOP))
def list_files(args, paths, exclusions=None, prefix=""):
files = set()
args = [os.path.join(prefix, arg) for arg in args]
for pattern in paths:
files.update(arg for arg in args if pathlib.Path(arg).match(pattern))
for pattern in exclusions or []:
files.difference_update(fnmatch.filter(files, os.path.join(prefix, pattern)))
return sorted(files)
def list_files(args):
return sorted(arg for arg in args if path_rx.match(relative_filename(arg)))
def fixup_c(filename):
@ -111,7 +151,9 @@ def fixup_c(filename):
if directive in ("if ", "ifdef ", "ifndef "):
l_next = lines[0]
indent_next = len(re.match(r"( *)", l_next).group(1))
if indent - 4 == indent_next and re.match(r" +(} else |case )", l_next):
if indent - 4 == indent_next and re.match(
r" +(} else |case )", l_next
):
# This #-line (and all associated ones) needs dedenting by 4 spaces.
l = l[4:]
dedent_stack.append(indent - 4)
@ -135,19 +177,25 @@ def fixup_c(filename):
def main():
cmd_parser = argparse.ArgumentParser(description="Auto-format C and Python files -- to be used via pre-commit only.")
cmd_parser = argparse.ArgumentParser(
description="Auto-format C and Python files -- to be used via pre-commit only."
)
cmd_parser.add_argument("-c", action="store_true", help="Format C code only")
cmd_parser.add_argument("-p", action="store_true", help="Format Python code only")
cmd_parser.add_argument("-v", action="store_true", help="Enable verbose output")
cmd_parser.add_argument("--dry-run", action="store_true", help="Print, don't act")
cmd_parser.add_argument("files", nargs="+", help="Run on specific globs")
args = cmd_parser.parse_args()
if args.dry_run:
print(" ".join(sys.argv))
# Setting only one of -c or -p disables the other. If both or neither are set, then do both.
format_c = args.c or not args.p
format_py = args.p or not args.c
# Expand the arguments passed on the command line, subject to the PATHS and EXCLUSIONS
files = list_files(args.files, PATHS, EXCLUSIONS, TOP)
files = list_files(args.files)
# Extract files matching a specific language.
def lang_files(exts):
@ -161,7 +209,10 @@ def main():
file_args = list(itertools.islice(files, N))
if not file_args:
break
subprocess.call(cmd + file_args)
if args.dry_run:
print(" ".join(cmd + file_args))
else:
subprocess.call(cmd + file_args)
# Format C files with uncrustify.
if format_c: