circuitpython/ports/stm32/boards/stm32l452_af.csv

1	Port		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
2			SYS_AF	TIM1/TIM2/LPTIM1	I2C4/TIM1/TIM2/TIM3	I2C4/USART2/CAN1/TIM1	I2C1/I2C2/I2C3/I2C4	SPI1/SPI2/I2C4	SPI3/DFSDM/COMP1	USART1/USART2/USART3	UART4/LPUART1/CAN1	CAN1/TSC	CAN1/USB/QUADSPI		SDMMC1/COMP1/COMP2	SAI1	TIM2/TIM15/TIM16/LPTIM2	EVENTOUT	ADC	COMP	DAC
3	PortA	PA0		TIM2_CH1						USART2_CTS	UART4_TX				COMP1_OUT	SAI1_EXTCLK	TIM2_ETR	EVENTOUT	ADC12_IN5	COMP1_INM
4	PortA	PA1		TIM2_CH2			I2C1_SMBA	SPI1_SCK		USART2_RTS/USART2_DE	UART4_RX						TIM15_CH1N	EVENTOUT	ADC12_IN6	COMP1_INP
5	PortA	PA2		TIM2_CH3						USART2_TX	LPUART1_TX		QUADSPI_BK1_NCS		COMP2_OUT		TIM15_CH1	EVENTOUT	ADC12_IN7	COMP2_INM
6	PortA	PA3		TIM2_CH4						USART2_RX	LPUART1_RX		QUADSPI_CLK			SAI1_MCLK_A	TIM15_CH2	EVENTOUT	ADC12_IN8	COMP2_INP
7	PortA	PA4						SPI1_NSS	SPI3_NSS	USART2_CK						SAI1_FS_B	LPTIM2_OUT	EVENTOUT	ADC12_IN9	COMP1_INM/COMP2_INM	DAC1_OUT1
8	PortA	PA5		TIM2_CH1	TIM2_ETR			SPI1_SCK	DFSDM1_CKOUT								LPTIM2_ETR	EVENTOUT	ADC12_IN10	COMP1_INM/COMP2_INM
9	PortA	PA6		TIM1_BKIN	TIM3_CH1			SPI1_MISO	COMP1_OUT	USART3_CTS	LPUART1_CTS		QUADSPI_BK1_IO3		TIM1_BKIN_COMP2		TIM16_CH1	EVENTOUT	ADC12_IN11
10	PortA	PA7		TIM1_CH1N	TIM3_CH2		I2C3_SCL	SPI1_MOSI	DFSDM1_DATIN0				QUADSPI_BK1_IO2		COMP2_OUT			EVENTOUT	ADC12_IN12
11	PortA	PA8	MCO	TIM1_CH1					DFSDM1_CKIN1	USART1_CK						SAI1_SCK_A	LPTIM2_OUT	EVENTOUT
12	PortA	PA9		TIM1_CH2			I2C1_SCL		DFSDM1_DATIN1	USART1_TX						SAI1_FS_A	TIM15_BKIN	EVENTOUT
13	PortA	PA10		TIM1_CH3			I2C1_SDA			USART1_RX			USBCRS_SYNC			SAI1_SD_A		EVENTOUT
14	PortA	PA11		TIM1_CH4	TIM1_BKIN2			SPI1_MISO	COMP1_OUT	USART1_CTS		CAN1_RX	USBDM		TIM1_BKIN2_COMP1			EVENTOUT
15	PortA	PA12		TIM1_ETR				SPI1_MOSI		USART1_RTS/USART1_DE		CAN1_TX	USBDP					EVENTOUT
16	PortA	PA13	JTMS/SWDIO	IR_OUT									USBNOE			SAI1_SD_B		EVENTOUT
17	PortA	PA14	JTCK/SWCLK	LPTIM1_OUT			I2C1_SMBA	I2C4_SMBA								SAI1_FS_B		EVENTOUT
18	PortA	PA15	JTDI	TIM2_CH1	TIM2_ETR	USART2_RX		SPI1_NSS	SPI3_NSS	USART3_RTS/USART3_DE	UART4_RTS/UART4_DE	TSC_G3_IO1						EVENTOUT
19	PortB	PB0		TIM1_CH2N	TIM3_CH3			SPI1_NSS	DFSDM1_CKIN0	USART3_CK			QUADSPI_BK1_IO1		COMP1_OUT	SAI1_EXTCLK		EVENTOUT	ADC12_IN15
20	PortB	PB1		TIM1_CH3N	TIM3_CH4				DFSDM_DATIN0	USART3_RTS/USART3_DE	LPUART1_RTS/LPUART1_DE		QUADSPI_BK1_IO0				LPTIM2_IN1	EVENTOUT	ADC12_IN16	COMP1_INN
21	PortB	PB2	RTC_OUT	LPTIM1_OUT			I2C3_SMBA		DFSDM_CKIN0									EVENTOUT		COMP1_INP
22	PortB	PB3	JTDO/TRACESWO	TIM2_CH2				SPI1_SCK	SPI3_SCK	USART1_RTS/USART1_DE						SAI1_SCK_B		EVENTOUT		COMP2_INM
23	PortB	PB4	NJTRST		TIM3_CH1		I2C3_SDA	SPI1_MISO	SPI3_MISO	USART1_CTS		TSC_G2_IO1				SAI1_MCLK_B		EVENTOUT		COMP2_INP
24	PortB	PB5		LPTIM1_IN1	TIM3_CH2	CAN1_RX	I2C1_SMBA	SPI1_MOSI	SPI3_MOSI	USART1_CK		TSC_G2_IO2			COMP2_OUT	SAI1_SD_B	TIM16_BKIN	EVENTOUT
25	PortB	PB6		LPTIM1_ETR			I2C1_SCL	I2C4_SCL		USART1_TX	CAN1_TX	TSC_G2_IO3				SAI1_FS_B	TIM16_CH1N	EVENTOUT		COMP2_INP
26	PortB	PB7		LPTIM1_IN2			I2C1_SDA	I2C4_SDA		USART1_RX	UART4_CTS	TSC_G2_IO4						EVENTOUT		COMP2_INM
27	PortB	PB8					I2C1_SCL					CAN1_RX			SDMMC1_D4	SAI1_MCLK_A	TIM16_CH1	EVENTOUT
28	PortB	PB9		IR_OUT			I2C1_SDA	SPI2_NSS				CAN1_TX			SDMMC1_D5	SAI1_FS_A		EVENTOUT
29	PortB	PB10		TIM2_CH3		I2C4_SCL	I2C2_SCL	SPI2_SCK		USART3_TX	LPUART1_RX	TSC_SYNC	QUADSPI_CLK		COMP1_OUT	SAI1_SCK_A		EVENTOUT
30	PortB	PB11		TIM2_CH4		I2C4_SDA	I2C2_SDA			USART3_RX	LPUART1_TX		QUADSPI_NCS		COMP2_OUT			EVENTOUT
31	PortB	PB12		TIM1_BKIN		TIM1_BKIN_COMP2	I2C2_SMBA	SPI2_NSS	DFSDM_DATIN1	USART3_CK	LPUART1_RTS/LPUART1_DE	TSC_G1_IO1	CAN1_RX			SAI1_FS_A	TIM15_BKIN	EVENTOUT
32	PortB	PB13		TIM1_CH1N			I2C2_SCL	SPI2_SCK	DFSDM_CKIN1	USART3_CTS	LPUART1_CTS	TSC_G1_IO2	CAN1_TX			SAI1_SCK_A	TIM15_CH1N	EVENTOUT
33	PortB	PB14		TIM1_CH2N			I2C2_SDA	SPI2_MISO	DFSDM_DATIN2	USART3_RTS/USART3_DE		TSC_G1_IO3				SAI1_MCLK_A	TIM15_CH1	EVENTOUT
34	PortB	PB15	RTC_REFIN	TIM1_CH3N				SPI2_MOSI	DFSDM_CKIN2			TSC_G1_IO4				SAI1_SD_A	TIM15_CH2	EVENTOUT
35	PortC	PC0		LPTIM1_IN1	I2C4_SCL		I2C3_SCL				LPUART1_RX						LPTIM2_IN1	EVENTOUT	ADC123_IN1
36	PortC	PC1	TRACED0	LPTIM1_OUT	I2C4_SDA		I2C3_SDA				LPUART1_TX							EVENTOUT	ADC123_IN2
37	PortC	PC2		LPTIM1_IN2				SPI2_MISO	DFSDM_CKOUT									EVENTOUT	ADC123_IN3
38	PortC	PC3		LPTIM1_ETR				SPI2_MOSI								SAI1_SD_A	LPTIM2_ETR	EVENTOUT	ADC123_IN4
39	PortC	PC4								USART3_TX								EVENTOUT	ADC12_IN13	COMP1_INM
40	PortC	PC5								USART3_RX								EVENTOUT	ADC12_IN14	COMP1_INP
41	PortC	PC6			TIM3_CH1				DFSDM_CKIN3			TSC_G4_IO1			SDMMC1_D6			EVENTOUT
42	PortC	PC7			TIM3_CH2				DFSDM_DATIN3			TSC_G4_IO2			SDMMC1_D7			EVENTOUT
43	PortC	PC8			TIM3_CH3							TSC_G4_IO3			SDMMC1_D0			EVENTOUT
44	PortC	PC9			TIM3_CH4							TSC_G4_IO4	USBNOE		SDMMC1_D1			EVENTOUT
45	PortC	PC10	TRACED1						SPI3_SCK	USART3_TX	UART4_TX	TSC_G3_IO2			SDMMC1_D2			EVENTOUT
46	PortC	PC11							SPI3_MISO	USART3_RX	UART4_RX	TSC_G3_IO3			SDMMC1_D3			EVENTOUT
47	PortC	PC12	TRACED3						SPI3_MOSI	USART3_CK		TSC_G3_IO4			SDMMC1_CK			EVENTOUT
48	PortC	PC13																EVENTOUT
49	PortC	PC14																EVENTOUT
50	PortC	PC15																EVENTOUT
51	PortD	PD0						SPI2_NSS				CAN1_RX						EVENTOUT
52	PortD	PD1						SPI2_SCK				CAN1_TX						EVENTOUT
53	PortD	PD2	TRACED2		TIM3_ETR					USART3_RTS/USART3_DE		TSC_SYNC			SDMMC1_CMD			EVENTOUT
54	PortD	PD3						SPI2_MISO	DFSDM_DATIN0	USART2_CTS			QUADSPI_BK2_NCS					EVENTOUT
55	PortD	PD4						SPI2_MOSI	DFSDM_CKIN0	USART2_RTS/USART2_DE			QUADSPI_BK2_IO0					EVENTOUT
56	PortD	PD5								USART2_TX			QUADSPI_BK2_IO1					EVENTOUT
57	PortD	PD6							DFSDM_DATIN1	USART2_RX			QUADSPI_BK2_IO2			SAI1_SD_A		EVENTOUT
58	PortD	PD7							DFSDM_CKIN1	USART2_CK			QUADSPI_BK2_IO3					EVENTOUT
59	PortD	PD8								USART3_TX								EVENTOUT
60	PortD	PD9								USART3_RX								EVENTOUT
61	PortD	PD10								USART3_CK		TSC_G6_IO1						EVENTOUT
62	PortD	PD11					I2C4_SMBA			USART3_CTS		TSC_G6_IO2					LPTIM2_ETR	EVENTOUT
63	PortD	PD12					I2C4_SCL			USART3_RTS/USART3_DE		TSC_G6_IO3					LPTIM2_IN1	EVENTOUT
64	PortD	PD13					I2C4_SDA					TSC_G6_IO4					LPTIM2_OUT	EVENTOUT
65	PortD	PD14																EVENTOUT
66	PortD	PD15																EVENTOUT
67	PortE	PE0															TIM16_CH1	EVENTOUT
68	PortE	PE1																EVENTOUT
69	PortE	PE2	TRACECLK		TIM3_ETR							TSC_G7_IO1				SAI1_MCLK_A		EVENTOUT
70	PortE	PE3	TRACED0		TIM3_CH1							TSC_G7_IO2				SAI1_SD_B		EVENTOUT
71	PortE	PE4	TRACED1		TIM3_CH2				DFSDM_DATIN3			TSC_G7_IO3				SAI1_FS_A		EVENTOUT
72	PortE	PE5	TRACED2		TIM3_CH3				DFSDM_CKIN3			TSC_G7_IO4				SAI1_SCK_A		EVENTOUT
73	PortE	PE6	TRACED3		TIM3_CH4											SAI1_SD_A		EVENTOUT
74	PortE	PE7		TIM1_ETR					DFSDM_DATIN2							SAI1_SD_B		EVENTOUT
75	PortE	PE8		TIM1_CH1N					DFSDM_CKIN2							SAI1_SCK_B		EVENTOUT
76	PortE	PE9		TIM1_CH1					DFSDM_CKOUT							SAI1_FS_B		EVENTOUT
77	PortE	PE10		TIM1_CH2N								TSC_G5_IO1	QUADSPI_CLK			SAI1_MCLK_B		EVENTOUT
78	PortE	PE11		TIM1_CH2								TSC_G5_IO2	QUADSPI_BK1_NCS					EVENTOUT
79	PortE	PE12		TIM1_CH3N				SPI1_NSS				TSC_G5_IO3	QUADSPI_BK1_IO0					EVENTOUT
80	PortE	PE13		TIM1_CH3				SPI1_SCK				TSC_G5_IO4	QUADSPI_BK1_IO1					EVENTOUT
81	PortE	PE14		TIM1_CH4	TIM1_BKIN2	TIM1_BKIN2_COMP2		SPI1_MISO					QUADSPI_BK1_IO2					EVENTOUT
82	PortE	PE15		TIM1_BKIN		TIM1_BKIN_COMP1		SPI1_MOSI					QUADSPI_BK1_IO3					EVENTOUT
83	PortH	PH0																EVENTOUT
84	PortH	PH1																EVENTOUT
85	PortH	PH3