circuitpython/stm32f767_af.csv at d613776f0d4215e064964c6838de27e81d4fbcca

Damien George 01dd7804b8 ports: Make new ports/ sub-directory and move all ports there.

This is to keep the top-level directory clean, to make it clear what is
core and what is a port, and to allow the repository to grow with new ports
in a sustainable way.

2017-09-06 13:40:51 +10:00

12 KiB

Raw Blame History

1	Port		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
2			SYS	TIM1/2	TIM3/4/5	TIM8/9/10/11/LPTIM1/CEC	I2C1/2/3/4/CEC	SPI1/2/3/4/5/6	SPI3/SAI1	SPI2/3/USART1/2/3/UART5/SPDIFRX	SAI2/USART6/UART4/5/7/8/SPDIFRX	CAN1/2/TIM12/13/14/QUADSPI/LCD	SAI2/QUADSPI/SDMMC2/OTG2_HS/OTG1_FS	SDMMC2/ETH	FMC/SDMMC1/OTG2_FS	DCMI	LCD	SYS
3	PortA	PA0		TIM2_CH1/TIM2_ETR	TIM5_CH1	TIM8_ETR				USART2_CTS	UART4_TX		SAI2_SD_B	ETH_MII_CRS				EVENTOUT
4	PortA	PA1		TIM2_CH2	TIM5_CH2					USART2_RTS	UART4_RX	QUADSPI_BK1_IO3	SAI2_MCK_B	ETH_MII_RX_CLK/ETH_RMII_REF_CLK			LCD_R2	EVENTOUT
5	PortA	PA2		TIM2_CH3	TIM5_CH3	TIM9_CH1				USART2_TX	SAI2_SCK_B			ETH_MDIO			LCD_R1	EVENTOUT
6	PortA	PA3		TIM2_CH4	TIM5_CH4	TIM9_CH2				USART2_RX			OTG_HS_ULPI_D0	ETH_MII_COL			LCD_B5	EVENTOUT
7	PortA	PA4						SPI1_NSS/I2S1_WS	SPI3_NSS/I2S3_WS	USART2_CK					OTG_HS_SOF	DCMI_HSYNC	LCD_VSYNC	EVENTOUT
8	PortA	PA5		TIM2_CH1/TIM2_ETR		TIM8_CH1N		SPI1_SCK/I2S1_CK					OTG_HS_ULPI_CK				LCD_R4	EVENTOUT
9	PortA	PA6		TIM1_BKIN	TIM3_CH1	TIM8_BKIN		SPI1_MISO				TIM13_CH1				DCMI_PIXCLK	LCD_G2	EVENTOUT
10	PortA	PA7		TIM1_CH1N	TIM3_CH2	TIM8_CH1N		SPI1_MOSI/I2S1_SD				TIM14_CH1		ETH_MII_RX_DV/ETH_RMII_CRS_DV	FMC_SDNWE			EVENTOUT
11	PortA	PA8	MCO1	TIM1_CH1		TIM8_BKIN2	I2C3_SCL			USART1_CK			OTG_FS_SOF				LCD_R6	EVENTOUT
12	PortA	PA9		TIM1_CH2			I2C3_SMBA	SPI2_SCK/I2S2_CK		USART1_TX						DCMI_D0		EVENTOUT
13	PortA	PA10		TIM1_CH3						USART1_RX			OTG_FS_ID			DCMI_D1		EVENTOUT
14	PortA	PA11		TIM1_CH4						USART1_CTS		CAN1_RX	OTG_FS_DM				LCD_R4	EVENTOUT
15	PortA	PA12		TIM1_ETR						USART1_RTS	SAI2_FS_B	CAN1_TX	OTG_FS_DP				LCD_R5	EVENTOUT
16	PortA	PA13	JTMS	SWDIO														EVENTOUT
17	PortA	PA14	JTCK	SWCLK														EVENTOUT
18	PortA	PA15	JTDI	TIM2_CH1/TIM2_ETR			HDMICE	CSPI1_NSS/I2S1_WS	SPI3_NSS/I2S3_WS		UART4_RTS							EVENTOUT
19	PortB	PB0		TIM1_CH2N	TIM3_CH3T	IM8_CH2N					UART4_CTS	LCD_R3	OTG_HS_ULPI_D1	ETH_MII_RXD2				EVENTOUT
20	PortB	PB1		TIM1_CH3N	TIM3_CH4T	IM8_CH3N						LCD_R6	OTG_HS_ULPI_D2	ETH_MII_RXD3				EVENTOUT
21	PortB	PB2							SAI1_SD_A	SPI3_MOSI/I2S3_SD		QUADSPI_CLK						EVENTOUT
22	PortB	PB3	JTDO/TRACESWO	TIM2_CH2				SPI1_SCK/I2S1_CK	SPI3_SCK/I2S3_CK				SDMMC2_D2					EVENTOUT
23	PortB	PB4	NJTRST		TIM3_CH1			SPI1_MISO	SPI3_MISO	SPI2_NSS/I2S2_WS			SDMMC2_D3					EVENTOUT
24	PortB	PB5			TIM3_CH2		I2C1_SMBA	SPI1_MOSI/I2S1_SD	SPI3_MOSI/I2S3_SD			CAN2_RX	OTG_HS_ULPI_D7	ETH_PPS_OUT	FMC_SDCKE1	DCMI_D10		EVENTOUT
25	PortB	PB6			TIM4_CH1	HDMICEC	I2C1_SCL			USART1_TX		CAN2_TX	QUADSPI_BK1_NCS		FMC_SDNE1	DCMI_D5		EVENTOUT
26	PortB	PB7			TIM4_CH2		I2C1_SDA			USART1_RX					FMC_NL	DCMI_VSYNC		EVENTOUT
27	PortB	PB8			TIM4_CH3	TIM10_CH1	I2C1_SCL					CAN1_RX	SDMMC2_D4	ETH_MII_TXD3	SDMMC1_D4	DCMI_D6	LCD_B6	EVENTOUT
28	PortB	PB9			TIM4_CH4	TIM11_CH1	I2C1_SDA	SPI2_NSS/I2S2_WS				CAN1_TX	SDMMC2_D5		SDMMC1_D5	DCMI_D7	LCD_B7	EVENTOUT
29	PortB	PB10		TIM2_CH3			I2C2_SCL	SPI2_SCK/I2S2_CK		USART3_TX			OTG_HS_ULPI_D3	ETH_MII_RX_ER			LCD_G4	EVENTOUT
30	PortB	PB11		TIM2_CH4			I2C2_SDA			USART3_RX			OTG_HS_ULPI_D4	ETH_MII_TX_EN/ETH_RMII_TX_EN			LCD_G5	EVENTOUT
31	PortB	PB12		TIM1_BKIN			I2C2_SMBA	SPI2_NSS/I2S2_WS		USART3_CK		CAN2_RX	OTG_HS_ULPI_D5	ETH_MII_TXD0/ETH_RMII_TXD0	OTG_HS_ID			EVENTOUT
32	PortB	PB13		TIM1_CH1N				SPI2_SCK/I2S2_CK		USART3_CTS		CAN2_TX	OTG_HS_ULPI_D6	ETH_MII_TXD1/ETH_RMII_TXD1				EVENTOUT
33	PortB	PB14		TIM1_CH2N		TIM8_CH2N		SPI2_MISO		USART3_RTS		TIM12_CH1	SDMMC2_D0		OTG_HS_DM			EVENTOUT
34	PortB	PB15	RTC_REFIN	TIM1_CH3N		TIM8_CH3N		SPI2_MOSI/I2S2_SD				TIM12_CH2	SDMMC2_D1		OTG_HS_DP			EVENTOUT
35	PortC	PC0									SAI2_FS_B		OTG_HS_ULPI_STP		FMC_SDNWE		LCD_R5	EVENTOUT
36	PortC	PC1	TRACED0					SPI2_MOSI/I2S2_SD	SAI1_SD_A					ETH_MDC				EVENTOUT
37	PortC	PC2						SPI2_MISO					OTG_HS_ULPI_DIR	ETH_MII_TXD2	FMC_SDNE0			EVENTOUT
38	PortC	PC3						SPI2_MOSI/I2S2_SD					OTG_HS_ULPI_NXT	ETH_MII_TX_CLK	FMC_SDCKE0			EVENTOUT
39	PortC	PC4						I2S1_MCK			SPDIFRX_IN2			ETH_MII_RXD0/ETH_RMII_RXD0	FMC_SDNE0			EVENTOUT
40	PortC	PC5									SPDIFRX_IN3			ETH_MII_RXD1/ETH_RMII_RXD1	FMC_SDCKE0			EVENTOUT
41	PortC	PC6			TIM3_CH1	TIM8_CH1		I2S2_MCK			USART6_TX		SDMMC2_D6		SDMMC1_D6	DCMI_D0	LCD_HSYNC	EVENTOUT
42	PortC	PC7			TIM3_CH2	TIM8_CH2			I2S3_MCK		USART6_RX		SDMMC2_D7		SDMMC1_D7	DCMI_D1	LCD_G6	EVENTOUT
43	PortC	PC8	TRACED1		TIM3_CH3	TIM8_CH3				UART5_RTS	USART6_CK				SDMMC1_D0	DCMI_D2		EVENTOUT
44	PortC	PC9	MCO2		TIM3_CH4	TIM8_CH4	I2C3_SDA	I2S_CKIN		UART5_CTS		QUADSPI_BK1_IO0			SDMMC1_D1	DCMI_D3		EVENTOUT
45	PortC	PC10							SPI3_SCK/I2S3_CK	USART3_TX	UART4_TX	QUADSPI_BK1_IO1			SDMMC1_D2	DCMI_D8	LCD_R2	EVENTOUT
46	PortC	PC11							SPI3_MISO	USART3_RX	UART4_RX	QUADSPI_BK2_NCS			SDMMC1_D3	DCMI_D4		EVENTOUT
47	PortC	PC12	TRACED3						SPI3_MOSI/I2S3_SD	USART3_CK	UART5_TX				SDMMC1_CK	DCMI_D9		EVENTOUT
48	PortC	PC13																EVENTOUT
49	PortC	PC14																EVENTOUT
50	PortC	PC15																EVENTOUT
51	PortD	PD0										CAN1_RX			FMC_D2			EVENTOUT
52	PortD	PD1										CAN1_TX			FMC_D3			EVENTOUT
53	PortD	PD2	TRACED2		TIM3_ETR						UART5_RX				SDMMC1_CMD	DCMI_D11		EVENTOUT
54	PortD	PD3						SPI2_SCK/I2S2_CK		USART2_CTS					FMC_CLK	DCMI_D5	LCD_G7	EVENTOUT
55	PortD	PD4								USART2_RTS					FMC_NOE			EVENTOUT
56	PortD	PD5								USART2_TX					FMC_NWE			EVENTOUT
57	PortD	PD6						SPI3_MOSI/I2S3_SD	SAI1_SD_A	USART2_RX				SDMMC2_CK	FMC_NWAIT	DCMI_D10	LCD_B2	EVENTOUT
58	PortD	PD7								USART2_CK	SPDIFRX_IN0			SDMMC2_CMD	FMC_NE1			EVENTOUT
59	PortD	PD8								USART3_TX	SPDIFRX_IN1				FMC_D13			EVENTOUT
60	PortD	PD9								USART3_RX					FMC_D14			EVENTOUT
61	PortD	PD10								USART3_CK					FMC_D15		LCD_B3	EVENTOUT
62	PortD	PD11					I2C4_SMBA			USART3_CTS		QUADSPI_BK1_IO0	SAI2_SD_A		FMC_A16/FMC_CLE			EVENTOUT
63	PortD	PD12			TIM4_CH1	LPTIM1_IN1	I2C4_SCL			USART3_RTS		QUADSPI_BK1_IO1	SAI2_FS_A		FMC_A17/FMC_ALE			EVENTOUT
64	PortD	PD13			TIM4_CH2	LPTIM1_OUT	I2C4_SDA					QUADSPI_BK1_IO3	SAI2_SCK_A		FMC_A18			EVENTOUT
65	PortD	PD14			TIM4_CH3						UART8_CTS				FMC_D0			EVENTOUT
66	PortD	PD15			TIM4_CH4						UART8_RTS				FMC_D1			EVENTOUT
67	PortE	PE0			TIM4_ETR	LPTIM1_ETR					UART8_RX		SAI2_MCK_A		FMC_NBL0	DCMI_D2		EVENTOUT
68	PortE	PE1				LPTIM1_IN2					UART8_TX				FMC_NBL1	DCMI_D3		EVENTOUT
69	PortE	PE2	TRACECLK					SPI4_SCK	SAI1_MCLK_A			QUADSPI_BK1_IO2		ETH_MII_TXD3	FMC_A23			EVENTOUT
70	PortE	PE3	TRACED0						SAI1_SD_B						FMC_A19			EVENTOUT
71	PortE	PE4	TRACED1					SPI4_NSS	SAI1_FS_A						FMC_A20	DCMI_D4	LCD_B0	EVENTOUT
72	PortE	PE5	TRACED2			TIM9_CH1		SPI4_MISO	SAI1_SCK_A						FMC_A21	DCMI_D6	LCD_G0	EVENTOUT
73	PortE	PE6	TRACED3	TIM1_BKIN2		TIM9_CH2		SPI4_MOSI	SAI1_SD_A				SAI2_MCK_B		FMC_A22	DCMI_D7	LCD_G1	EVENTOUT
74	PortE	PE7		TIM1_ETR							UART7_RX		QUADSPI_BK2_IO0		FMC_D4			EVENTOUT
75	PortE	PE8		TIM1_CH1N							UART7_TX		QUADSPI_BK2_IO1		FMC_D5			EVENTOUT
76	PortE	PE9		TIM1_CH1							UART7_RTS		QUADSPI_BK2_IO2		FMC_D6			EVENTOUT
77	PortE	PE10		TIM1_CH2N							UART7_CTS		QUADSPI_BK2_IO3		FMC_D7			EVENTOUT
78	PortE	PE11		TIM1_CH2				SPI4_NSS					SAI2_SD_B		FMC_D8		LCD_G3	EVENTOUT
79	PortE	PE12		TIM1_CH3N				SPI4_SCK					SAI2_SCK_B		FMC_D9		LCD_B4	EVENTOUT
80	PortE	PE13		TIM1_CH3				SPI4_MISO					SAI2_FS_B		FMC_D10		LCD_DE	EVENTOUT
81	PortE	PE14		TIM1_CH4				SPI4_MOSI					SAI2_MCK_B		FMC_D11		LCD_CLK	EVENTOUT
82	PortE	PE15		TIM1_BKIN											FMC_D12		LCD_R7	EVENTOUT
83	PortF	PF0					I2C2_SDA								FMC_A0			EVENTOUT
84	PortF	PF1					I2C2_SCL								FMC_A1			EVENTOUT
85	PortF	PF2					I2C2_SMBA								FMC_A2			EVENTOUT
86	PortF	PF3													FMC_A3			EVENTOUT
87	PortF	PF4													FMC_A4			EVENTOUT
88	PortF	PF5													FMC_A5			EVENTOUT
89	PortF	PF6				TIM10_CH1		SPI5_NSS	SAI1_SD_B		UART7_RX	QUADSPI_BK1_IO3						EVENTOUT
90	PortF	PF7				TIM11_CH1		SPI5_SCK	SAI1_MCLK_B		UART7_TX	QUADSPI_BK1_IO2						EVENTOUT
91	PortF	PF8						SPI5_MISO	SAI1_SCK_B		UART7_RTS	TIM13_CH1	QUADSPI_BK1_IO0					EVENTOUT
92	PortF	PF9						SPI5_MOSI	SAI1_FS_B		UART7_CTS	TIM14_CH1	QUADSPI_BK1_IO1					EVENTOUT
93	PortF	PF10														DCMI_D11	LCD_DE	EVENTOUT
94	PortF	PF11						SPI5_MOSI					SAI2_SD_B		FMC_SDNRAS	DCMI_D12		EVENTOUT
95	PortF	PF12													FMC_A6			EVENTOUT
96	PortF	PF13					I2C4_SMBA								FMC_A7			EVENTOUT
97	PortF	PF14					I2C4_SCL								FMC_A8			EVENTOUT
98	PortF	PF15					I2C4_SDA								FMC_A9			EVENTOUT
99	PortG	PG0													FMC_A10			EVENTOUT
100	PortG	PG1													FMC_A11			EVENTOUT
101	PortG	PG2													FMC_A12			EVENTOUT
102	PortG	PG3													FMC_A13			EVENTOUT
103	PortG	PG4													FMC_A14/FMC_BA0			EVENTOUT
104	PortG	PG5													FMC_A15/FMC_BA1			EVENTOUT
105	PortG	PG6														DCMI_D12	LCD_R7	EVENTOUT
106	PortG	PG7									USART6_CK				FMC_INT	DCMI_D13	LCD_CLK	EVENTOUT
107	PortG	PG8						SPI6_NSS		SPDIFRX_IN2	USART6_RTS			ETH_PPS_OUT	FMC_SDCLK			EVENTOUT
108	PortG	PG9								SPDIFRX_IN3	USART6_RX	QUADSPI_BK2_IO2	SAI2_FS_B	SDMMC2_D0	FMC_NE2/FMC_NCE	DCMI_VSYNC		EVENTOUT
109	PortG	PG10										LCD_G3	SAI2_SD_B	SDMMC2_D1	FMC_NE3	DCMI_D2	LCD_B2	EVENTOUT
110	PortG	PG11								SPDIFRX_IN0			SDMMC2_D2	ETH_MII_TX_EN/ETH_RMII_TX_EN		DCMI_D3	LCD_B3	EVENTOUT
111	PortG	PG12				LPTIM1_IN1		SPI6_MISO		SPDIFRX_IN1	USART6_RTS	LCD_B4		SDMMC2_D3	FMC_NE4		LCD_B1	EVENTOUT
112	PortG	PG13	TRACED0			LPTIM1_OUT		SPI6_SCK			USART6_CTS			ETH_MII_TXD0/ETH_RMII_TXD0	FMC_A24		LCD_R0	EVENTOUT
113	PortG	PG14	TRACED1			LPTIM1_ETR		SPI6_MOSI			USART6_TX	QUADSPI_BK2_IO3		ETH_MII_TXD1/ETH_RMII_TXD1	FMC_A25		LCD_B0	EVENTOUT
114	PortG	PG15									USART6_CTS				FMC_SDNCAS	DCMI_D13		EVENTOUT
115	PortH	PH0																EVENTOUT
116	PortH	PH1																EVENTOUT
117	PortH	PH2				LPTIM1_IN2						QUADSPI_BK2_IO0	SAI2_SCK_B	ETH_MII_CRS	FMC_SDCKE0		LCD_R0	EVENTOUT
118	PortH	PH3										QUADSPI_BK2_IO1	SAI2_MCK_B	ETH_MII_COL	FMC_SDNE0		LCD_R1	EVENTOUT
119	PortH	PH4					I2C2_SCL						OTG_HS_ULPI_NXT					EVENTOUT
120	PortH	PH5					I2C2_SDA	SPI5_NSS							FMC_SDNWE			EVENTOUT
121	PortH	PH6					I2C2_SMBA	SPI5_SCK				TIM12_CH1		ETH_MII_RXD2	FMC_SDNE1	DCMI_D8		EVENTOUT
122	PortH	PH7					I2C3_SCL	SPI5_MISO						ETH_MII_RXD3	FMC_SDCKE1	DCMI_D9		EVENTOUT
123	PortH	PH8					I2C3_SDA								FMC_D16	DCMI_HSYNC	LCD_R2	EVENTOUT
124	PortH	PH9					I2C3_SMBA					TIM12_CH2			FMC_D17	DCMI_D0	LCD_R3	EVENTOUT
125	PortH	PH10			TIM5_CH1		I2C4_SMBA								FMC_D18	DCMI_D1	LCD_R4	EVENTOUT
126	PortH	PH11			TIM5_CH2		I2C4_SCL								FMC_D19	DCMI_D2	LCD_R5	EVENTOUT
127	PortH	PH12			TIM5_CH3		I2C4_SDA								FMC_D20	DCMI_D3	LCD_R6	EVENTOUT
128	PortH	PH13				TIM8_CH1N						CAN1_TX			FMC_D21		LCD_G2	EVENTOUT
129	PortH	PH14				TIM8_CH2N									FMC_D22	DCMI_D4	LCD_G3	EVENTOUT
130	PortH	PH15				TIM8_CH3N									FMC_D23	DCMI_D11	LCD_G4	EVENTOUT
131	PortI	PI0			TIM5_CH4			SPI2_NSS/I2S2_WS							FMC_D24	DCMI_D13	LCD_G5	EVENTOUT
132	PortI	PI1				TIM8_BKIN2		SPI2_SCK/I2S2_CK							FMC_D25	DCMI_D8	LCD_G6	EVENTOUT
133	PortI	PI2				TIM8_CH4		SPI2_MISO							FMC_D26	DCMI_D9	LCD_G7	EVENTOUT
134	PortI	PI3				TIM8_ETR		SPI2_MOSI/I2S2_SD							FMC_D27	DCMI_D10		EVENTOUT
135	PortI	PI4				TIM8_BKIN							SAI2_MCK_A		FMC_NBL2	DCMI_D5	LCD_B4	EVENTOUT
136	PortI	PI5				TIM8_CH1							SAI2_SCK_A		FMC_NBL3	DCMI_VSYNC	LCD_B5	EVENTOUT
137	PortI	PI6				TIM8_CH2							SAI2_SD_A		FMC_D28	DCMI_D6	LCD_B6	EVENTOUT
138	PortI	PI7				TIM8_CH3							SAI2_FS_A		FMC_D29	DCMI_D7	LCD_B7	EVENTOUT
139	PortI	PI8																EVENTOUT
140	PortI	PI9										CAN1_RX			FMC_D30		LCD_VSYNC	EVENTOUT
141	PortI	PI10												ETH_MII_RX_ER	FMC_D31		LCD_HSYNC	EVENTOUT
142	PortI	PI11											OTG_HS_ULPI_DIR					EVENTOUT
143	PortI	PI12															LCD_HSYNC	EVENTOUT
144	PortI	PI13															LCD_VSYNC	EVENTOUT
145	PortI	PI14															LCD_CLK	EVENTOUT
146	PortI	PI15															LCD_R0	EVENTOUT
147	PortJ	PJ0															LCD_R1	EVENTOUT
148	PortJ	PJ1															LCD_R2	EVENTOUT
149	PortJ	PJ2															LCD_R3	EVENTOUT
150	PortJ	PJ3															LCD_R4	EVENTOUT
151	PortJ	PJ4															LCD_R5	EVENTOUT
152	PortJ	PJ5															LCD_R6	EVENTOUT
153	PortJ	PJ6															LCD_R7	EVENTOUT
154	PortJ	PJ7															LCD_G0	EVENTOUT
155	PortJ	PJ8															LCD_G1	EVENTOUT
156	PortJ	PJ9															LCD_G2	EVENTOUT
157	PortJ	PJ10															LCD_G3	EVENTOUT
158	PortJ	PJ11															LCD_G4	EVENTOUT
159	PortJ	PJ12															LCD_B0	EVENTOUT
160	PortJ	PJ13															LCD_B1	EVENTOUT
161	PortJ	PJ14															LCD_B2	EVENTOUT
162	PortJ	PJ15															LCD_B3	EVENTOUT
163	PortK	PK0															LCD_G5	EVENTOUT
164	PortK	PK1															LCD_G6	EVENTOUT
165	PortK	PK2															LCD_G7	EVENTOUT
166	PortK	PK3															LCD_B4	EVENTOUT
167	PortK	PK4															LCD_B5	EVENTOUT
168	PortK	PK5															LCD_B6	EVENTOUT
169	PortK	PK6															LCD_B7	EVENTOUT
170	PortK	PK7															LCD_DE	EVENTOUT

12 KiB Raw Blame History

12 KiB

Raw Blame History