circuitpython/ports/cxd56/common-hal
Diego Elio Pettenò dd5d7c86d2 Fix up end of file and trailing whitespace.
This can be enforced by pre-commit, but correct it separately to make it easier to review.
2020-06-03 10:56:35 +01:00
..
analogio new pin validation routines; don't use mp_const_none if NULL will do 2020-02-28 23:43:04 -05:00
board Add Spresense board folder 2019-10-11 12:09:51 +02:00
busio Fix up end of file and trailing whitespace. 2020-06-03 10:56:35 +01:00
digitalio Update digitalio api for other ports 2020-05-20 09:23:42 -07:00
microcontroller Fix up Spresense build. It doesn't sleep. 2020-03-17 14:21:45 -07:00
os Change port name to cxd56 2019-10-11 08:23:51 +02:00
pulseio Fix up end of file and trailing whitespace. 2020-06-03 10:56:35 +01:00
rtc Change port name to cxd56 2019-10-11 08:23:51 +02:00
supervisor Change port name to cxd56 2019-10-11 08:23:51 +02:00