ab7ddfddd5
Refactor the convoluted asf4 clock setup into something more readable. enable_clock_generator() has 2 changes: - Set 'Output enabled' to match the current clock setup - Handle divisors above 511 Add an enable_clock_generator_sync() version which makes it possible to setup clocks without waiting for syncing. The bootup would hang without this. I have checked these registers: NVMCTRL->CTRLA = 0x00000004 Peripheral clocks (only non-zero shown): PCHCTRL[1]=0x00000045 PCHCTRL[10]=0x00000041 Generator clocks (only non-zero shown): GENCTRL[0] = 0x00010907 GENCTRL[1] = 0x00010906 -GENCTRL[2] = 0x00041104 +GENCTRL[2] = 0x00200904 GENCTRL[4] = 0x00010907 GENCTRL[5] = 0x00180906 DFLL clock: OSCCTRL->DFLLCTRLA = 0x00000082 OSCCTRL->DFLLCTRLB = 0x00000000 OSCCTRL->DFLLVAL = 0x00008082 OSCCTRL->DFLLMUL = 0x00000000 DPLL clocks: OSCCTRL->Dpll[0].DPLLCTRLA=0x00000002 OSCCTRL->Dpll[0].DPLLCTRLB=0x00000000 OSCCTRL->Dpll[0].DPLLRATIO=0x0000003b OSCCTRL->Dpll[1].DPLLCTRLA=0x00000080 OSCCTRL->Dpll[1].DPLLCTRLB=0x00000020 OSCCTRL->Dpll[1].DPLLRATIO=0x00000000 OSC32KCTRL clock: OSC32KCTRL->RTCCTRL = 0x00000000 OSC32KCTRL->XOSC32K = 0x00002082 OSC32KCTRL->CFDCTRL = 0x00000000 OSC32KCTRL->EVCTRL = 0x00000000 OSC32KCTRL->OSCULP32K = 0x00002300 Only gen2 changed which is due to samd51 having more bits in the simple division register so DIVSEL wasn't necessary, and it didn't have OE set.
345 lines
12 KiB
C
345 lines
12 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "boards/board.h"
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#include "supervisor/port.h"
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// ASF 4
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#include "atmel_start_pins.h"
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#include "hal/include/hal_delay.h"
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#include "hal/include/hal_gpio.h"
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#include "hal/include/hal_init.h"
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#include "hal/include/hal_usb_device.h"
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#include "hpl/gclk/hpl_gclk_base.h"
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#include "hpl/pm/hpl_pm_base.h"
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#ifdef SAMD21
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#include "hri/hri_pm_d21.h"
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#endif
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#ifdef SAMD51
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#include "hri/hri_rstc_d51.h"
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#endif
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#include "common-hal/analogio/AnalogIn.h"
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#include "common-hal/analogio/AnalogOut.h"
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#include "common-hal/audiobusio/PDMIn.h"
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#include "common-hal/audiobusio/I2SOut.h"
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#include "common-hal/audioio/AudioOut.h"
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#include "common-hal/microcontroller/Pin.h"
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#include "common-hal/pulseio/PulseIn.h"
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#include "common-hal/pulseio/PulseOut.h"
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#include "common-hal/pulseio/PWMOut.h"
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#include "common-hal/rtc/RTC.h"
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#include "common-hal/touchio/TouchIn.h"
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#include "common-hal/usb_hid/Device.h"
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#include "shared-bindings/rtc/__init__.h"
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#include "clocks.h"
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#include "events.h"
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#include "peripherals.h"
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#include "shared_dma.h"
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#include "tick.h"
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#ifdef CIRCUITPY_GAMEPAD_TICKS
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#include "shared-module/gamepad/__init__.h"
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#endif
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extern volatile bool mp_msc_enabled;
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#if defined(SAMD21) && defined(ENABLE_MICRO_TRACE_BUFFER)
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// Stores 2 ^ TRACE_BUFFER_MAGNITUDE_PACKETS packets.
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// 7 -> 128 packets
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#define TRACE_BUFFER_MAGNITUDE_PACKETS 7
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// Size in uint32_t. Two per packet.
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#define TRACE_BUFFER_SIZE (1 << (TRACE_BUFFER_MAGNITUDE_PACKETS + 1))
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// Size in bytes. 4 bytes per uint32_t.
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#define TRACE_BUFFER_SIZE_BYTES (TRACE_BUFFER_SIZE << 2)
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__attribute__((__aligned__(TRACE_BUFFER_SIZE_BYTES))) uint32_t mtb[TRACE_BUFFER_SIZE];
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#endif
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safe_mode_t port_init(void) {
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#if defined(SAMD21)
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// Set brownout detection to ~2.7V. Default from factory is 1.7V,
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// which is too low for proper operation of external SPI flash chips (they are 2.7-3.6V).
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// Disable while changing level.
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SYSCTRL->BOD33.bit.ENABLE = 0;
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SYSCTRL->BOD33.bit.LEVEL = 39; // 2.77V with hysteresis off. Table 37.20 in datasheet.
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SYSCTRL->BOD33.bit.ENABLE = 1;
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#ifdef ENABLE_MICRO_TRACE_BUFFER
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REG_MTB_POSITION = ((uint32_t) (mtb - REG_MTB_BASE)) & 0xFFFFFFF8;
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REG_MTB_FLOW = (((uint32_t) mtb - REG_MTB_BASE) + TRACE_BUFFER_SIZE_BYTES) & 0xFFFFFFF8;
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REG_MTB_MASTER = 0x80000000 + (TRACE_BUFFER_MAGNITUDE_PACKETS - 1);
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#else
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// Triple check that the MTB is off. Switching between debug and non-debug
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// builds can leave it set over reset and wreak havok as a result.
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REG_MTB_MASTER = 0x00000000 + 6;
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#endif
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#endif
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#if defined(SAMD51)
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// Set brownout detection to ~2.7V. Default from factory is 1.7V,
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// which is too low for proper operation of external SPI flash chips (they are 2.7-3.6V).
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// Disable while changing level.
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SUPC->BOD33.bit.ENABLE = 0;
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SUPC->BOD33.bit.LEVEL = 200; // 2.7V: 1.5V + LEVEL * 6mV.
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SUPC->BOD33.bit.ENABLE = 1;
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// MPU (Memory Protection Unit) setup.
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// We hoped we could make the QSPI region be non-cachable with the MPU,
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// but the CMCC doesn't seem to pay attention to the MPU settings.
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// Leaving this code here disabled,
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// because it was hard enough to figure out, and maybe there's
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// a mistake that could make it work in the future.
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#if 0
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// Designate QSPI memory mapped region as not cachable.
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// Turn off MPU in case it is on.
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MPU->CTRL = 0;
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// Configure region 0.
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MPU->RNR = 0;
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// Region base: start of QSPI mapping area.
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// QSPI region runs from 0x04000000 up to and not including 0x05000000: 16 megabytes
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MPU->RBAR = QSPI_AHB;
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MPU->RASR =
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0b011 << MPU_RASR_AP_Pos | // full read/write access for privileged and user mode
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0b000 << MPU_RASR_TEX_Pos | // caching not allowed, strongly ordered
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1 << MPU_RASR_S_Pos | // sharable
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0 << MPU_RASR_C_Pos | // not cachable
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0 << MPU_RASR_B_Pos | // not bufferable
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0b10111 << MPU_RASR_SIZE_Pos | // 16MB region size
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1 << MPU_RASR_ENABLE_Pos // enable this region
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;
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// Turn off regions 1-7.
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for (uint32_t i = 1; i < 8; i ++) {
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MPU->RNR = i;
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MPU->RBAR = 0;
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MPU->RASR = 0;
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}
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// Turn on MPU. Turn on PRIVDEFENA, which defines a default memory
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// map for all privileged access, so we don't have to set up other regions
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// besides QSPI.
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MPU->CTRL = MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
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#endif
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samd_peripherals_enable_cache();
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#endif
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// On power on start or external reset, set _ezero to the canary word. If it
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// gets killed, we boot in safe mode. _ezero is the boundary between statically
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// allocated memory including the fixed MicroPython heap and the stack. If either
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// misbehaves, the canary will not be intact after soft reset.
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#ifdef CIRCUITPY_CANARY_WORD
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#ifdef SAMD21
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bool power_on_or_external_reset = hri_pm_get_RCAUSE_POR_bit(PM) || hri_pm_get_RCAUSE_EXT_bit(PM);
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bool system_reset = hri_pm_get_RCAUSE_SYST_bit(PM);
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#endif
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#ifdef SAMD51
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bool power_on_or_external_reset = hri_rstc_get_RCAUSE_POR_bit(RSTC) || hri_rstc_get_RCAUSE_EXT_bit(RSTC);
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bool system_reset = hri_rstc_get_RCAUSE_SYST_bit(RSTC);
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#endif
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if (power_on_or_external_reset) {
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_ezero = CIRCUITPY_CANARY_WORD;
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} else if (system_reset) {
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// If we're starting from a system reset we're likely coming from the
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// bootloader or hard fault handler. If we're coming from the handler
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// the canary will be CIRCUITPY_SAFE_RESTART_WORD and we don't want to
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// revive the canary so that a second hard fault won't restart. Resets
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// from anywhere else are ok.
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if (_ezero == CIRCUITPY_SAFE_RESTART_WORD) {
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_ezero = ~CIRCUITPY_CANARY_WORD;
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} else {
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_ezero = CIRCUITPY_CANARY_WORD;
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}
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}
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#endif
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#ifdef SAMD21
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hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
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_pm_init();
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#endif
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clock_init();
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board_init();
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// Configure millisecond timer initialization.
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tick_init();
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#ifndef PIRKEY_M0
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rtc_init();
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#endif
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init_shared_dma();
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#ifdef CIRCUITPY_CANARY_WORD
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// Run in safe mode if the canary is corrupt.
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if (_ezero != CIRCUITPY_CANARY_WORD) {
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return HARD_CRASH;
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}
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#endif
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// if (PM->RCAUSE.bit.BOD33 == 1 || PM->RCAUSE.bit.BOD12 == 1) {
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// return BROWNOUT;
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// }
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if (board_requests_safe_mode()) {
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return USER_SAFE_MODE;
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}
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return NO_SAFE_MODE;
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}
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void reset_port(void) {
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// Reset all SERCOMs except the ones being used by on-board devices.
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Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
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for (int i = 0; i < SERCOM_INST_NUM; i++) {
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#ifdef SPI_FLASH_SERCOM
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if (sercom_instances[i] == SPI_FLASH_SERCOM) {
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continue;
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}
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#endif
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#ifdef MICROPY_HW_APA102_SERCOM
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if (sercom_instances[i] == MICROPY_HW_APA102_SERCOM) {
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continue;
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}
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#endif
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// SWRST is same for all modes of SERCOMs.
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sercom_instances[i]->SPI.CTRLA.bit.SWRST = 1;
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}
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#ifdef EXPRESS_BOARD
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audioout_reset();
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#if !defined(__SAMD51G19A__) && !defined(__SAMD51G18A__)
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i2sout_reset();
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#endif
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audio_dma_reset();
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//pdmin_reset();
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#endif
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#ifdef SAMD21
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touchin_reset();
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#endif
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pulsein_reset();
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pulseout_reset();
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pwmout_reset();
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#ifndef PIRKEY_M0
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analogin_reset();
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analogout_reset();
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rtc_reset();
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#endif
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reset_gclks();
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#ifdef CIRCUITPY_GAMEPAD_TICKS
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gamepad_reset();
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#endif
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reset_event_system();
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reset_all_pins();
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// Set up debugging pins after reset_all_pins().
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// Uncomment to init PIN_PA17 for debugging.
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// struct port_config pin_conf;
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// port_get_config_defaults(&pin_conf);
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//
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// pin_conf.direction = PORT_PIN_DIR_OUTPUT;
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// port_pin_set_config(MICROPY_HW_LED1, &pin_conf);
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// port_pin_set_output_level(MICROPY_HW_LED1, false);
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// Output clocks for debugging.
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// not supported by SAMD51G; uncomment for SAMD51J or update for 51G
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// #ifdef SAMD51
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// gpio_set_pin_function(PIN_PA10, GPIO_PIN_FUNCTION_M); // GCLK4, D3
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// gpio_set_pin_function(PIN_PA11, GPIO_PIN_FUNCTION_M); // GCLK5, A4
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// gpio_set_pin_function(PIN_PB14, GPIO_PIN_FUNCTION_M); // GCLK0, D5
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// gpio_set_pin_function(PIN_PB15, GPIO_PIN_FUNCTION_M); // GCLK1, D6
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// #endif
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usb_hid_reset();
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// #ifdef CALIBRATE_CRYSTALLESS
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// // If we are on USB lets double check our fine calibration for the clock and
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// // save the new value if its different enough.
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// if (mp_msc_enabled) {
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// SYSCTRL->DFLLSYNC.bit.READREQ = 1;
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// uint16_t saved_calibration = 0x1ff;
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// if (strcmp((char*) INTERNAL_CIRCUITPY_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) {
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// saved_calibration = ((uint16_t *) INTERNAL_CIRCUITPY_CONFIG_START_ADDR)[8];
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// }
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// while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) {
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// // TODO(tannewt): Run the mass storage stuff if this takes a while.
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// }
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// int16_t current_calibration = SYSCTRL->DFLLVAL.bit.FINE;
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// if (abs(current_calibration - saved_calibration) > 10) {
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// enum status_code error_code;
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// uint8_t page_buffer[NVMCTRL_ROW_SIZE];
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// for (int i = 0; i < NVMCTRL_ROW_PAGES; i++) {
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// do
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// {
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// error_code = nvm_read_buffer(INTERNAL_CIRCUITPY_CONFIG_START_ADDR + i * NVMCTRL_PAGE_SIZE,
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// page_buffer + i * NVMCTRL_PAGE_SIZE,
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// NVMCTRL_PAGE_SIZE);
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// } while (error_code == STATUS_BUSY);
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// }
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// // If this is the first write, include the header.
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// if (strcmp((char*) page_buffer, "CIRCUITPYTHON1") != 0) {
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// memcpy(page_buffer, "CIRCUITPYTHON1", 15);
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// }
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// // First 16 bytes (0-15) are ID. Little endian!
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// page_buffer[16] = current_calibration & 0xff;
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// page_buffer[17] = current_calibration >> 8;
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// do
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// {
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// error_code = nvm_erase_row(INTERNAL_CIRCUITPY_CONFIG_START_ADDR);
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// } while (error_code == STATUS_BUSY);
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// for (int i = 0; i < NVMCTRL_ROW_PAGES; i++) {
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// do
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// {
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// error_code = nvm_write_buffer(INTERNAL_CIRCUITPY_CONFIG_START_ADDR + i * NVMCTRL_PAGE_SIZE,
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// page_buffer + i * NVMCTRL_PAGE_SIZE,
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// NVMCTRL_PAGE_SIZE);
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// } while (error_code == STATUS_BUSY);
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// }
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// }
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// }
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// #endif
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}
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/**
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* \brief Default interrupt handler for unused IRQs.
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*/
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__attribute__((used)) void HardFault_Handler(void)
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{
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while (true) {
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asm("");
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}
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for (uint32_t i = 0; i < 100000; i++) {
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asm("noop;");
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}
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}
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