Refactor the convoluted asf4 clock setup into something more readable.
enable_clock_generator() has 2 changes:
- Set 'Output enabled' to match the current clock setup
- Handle divisors above 511
Add an enable_clock_generator_sync() version which makes it possible to setup
clocks without waiting for syncing. The bootup would hang without this.
I have checked these registers:
NVMCTRL->CTRLA = 0x00000004
Peripheral clocks (only non-zero shown):
PCHCTRL[1]=0x00000045
PCHCTRL[10]=0x00000041
Generator clocks (only non-zero shown):
GENCTRL[0] = 0x00010907
GENCTRL[1] = 0x00010906
-GENCTRL[2] = 0x00041104
+GENCTRL[2] = 0x00200904
GENCTRL[4] = 0x00010907
GENCTRL[5] = 0x00180906
DFLL clock:
OSCCTRL->DFLLCTRLA = 0x00000082
OSCCTRL->DFLLCTRLB = 0x00000000
OSCCTRL->DFLLVAL = 0x00008082
OSCCTRL->DFLLMUL = 0x00000000
DPLL clocks:
OSCCTRL->Dpll[0].DPLLCTRLA=0x00000002
OSCCTRL->Dpll[0].DPLLCTRLB=0x00000000
OSCCTRL->Dpll[0].DPLLRATIO=0x0000003b
OSCCTRL->Dpll[1].DPLLCTRLA=0x00000080
OSCCTRL->Dpll[1].DPLLCTRLB=0x00000020
OSCCTRL->Dpll[1].DPLLRATIO=0x00000000
OSC32KCTRL clock:
OSC32KCTRL->RTCCTRL = 0x00000000
OSC32KCTRL->XOSC32K = 0x00002082
OSC32KCTRL->CFDCTRL = 0x00000000
OSC32KCTRL->EVCTRL = 0x00000000
OSC32KCTRL->OSCULP32K = 0x00002300
Only gen2 changed which is due to samd51 having more bits in the simple
division register so DIVSEL wasn't necessary, and it didn't have OE set.
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