1f6cb8f047
This commit adds support for machine.I2S on the mimxrt port. The I2S API is consistent with the existing stm32, esp32, and rp2 implementations. I2S features: - controller transmit and controller receive - 16-bit and 32-bit sample sizes - mono and stereo formats - sampling frequencies from 8kHz to 48kHz - 3 modes of operation: - blocking - non-blocking with callback - uasyncio - configurable internal buffer - optional MCK Tested with the following development boards: - MIMXRT1010_EVK, MIMXRT1015_EVK, MIMXRT1020_EVK, MIMXRT1050_EVK - Teensy 4.0, Teensy 4.1 - Olimex RT1010 - Seeed ARCH MIX Tested with the following I2S hardware peripherals: - UDA1334 - GY-SPH0645LM4H - WM8960 codec on board the MIMXRT boards and separate breakout board - INMP441 - PCM5102 - SGTL5000 on the Teensy audio shield Signed-off-by: Mike Teachman <mike.teachman@gmail.com>
80 lines
2.8 KiB
C
80 lines
2.8 KiB
C
#define MICROPY_HW_BOARD_NAME "i.MX RT1010 EVK"
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#define MICROPY_HW_MCU_NAME "MIMXRT1011DAE5A"
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// i.MX RT1010 EVK has 1 board LED
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#define MICROPY_HW_LED1_PIN (pin_GPIO_11)
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#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin))
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#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))
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#define MICROPY_HW_NUM_PIN_IRQS (2 * 32)
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// Define mapping logical UART # to hardware UART #
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// LPUART1 on USB_DBG -> 0
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// LPUART1 on D0/D1 -> 1
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// LPUART3 on A0/D4 -> 3
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// LPUART4 on D6/D7 -> 2
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#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
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#define MICROPY_HW_UART_INDEX { 1, 1, 4, 3 }
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#define IOMUX_TABLE_UART \
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{ IOMUXC_GPIO_10_LPUART1_TXD }, { IOMUXC_GPIO_09_LPUART1_RXD }, \
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{ 0 }, { 0 }, \
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{ 0 }, { 0 }, \
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{ IOMUXC_GPIO_AD_02_LPUART4_TXD }, { IOMUXC_GPIO_AD_01_LPUART4_RXD },
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#define MICROPY_HW_SPI_INDEX { 1 }
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#define IOMUX_TABLE_SPI \
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{ IOMUXC_GPIO_AD_06_LPSPI1_SCK }, { IOMUXC_GPIO_AD_05_LPSPI1_PCS0 }, \
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{ IOMUXC_GPIO_AD_04_LPSPI1_SDO }, { IOMUXC_GPIO_AD_03_LPSPI1_SDI }, \
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{ IOMUXC_GPIO_AD_02_LPSPI1_PCS1 }
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#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx }
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#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx }
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// Define mapping hardware I2C # to logical I2C #
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// SDA/SCL HW-I2C Logical I2C
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// D14/D15 LPI2C1 -> 0
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// D0/D1 LPI2C2 -> 1
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// D6/D7 LPI2C2 -> 1 Alternatively possible GPIO_AD_01, GPIO_AD_02
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#define MICROPY_HW_I2C_INDEX { 1, 2 }
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#define IOMUX_TABLE_I2C \
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{ IOMUXC_GPIO_02_LPI2C1_SCL }, { IOMUXC_GPIO_01_LPI2C1_SDA }, \
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{ IOMUXC_GPIO_10_LPI2C2_SCL }, { IOMUXC_GPIO_09_LPI2C2_SDA },
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#define MICROPY_PY_MACHINE_I2S (1)
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#define MICROPY_HW_I2S_NUM (1)
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#define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux }
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#define I2S_CLOCK_PRE_DIV { 0, kCLOCK_Sai1PreDiv }
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#define I2S_CLOCK_DIV { 0, kCLOCK_Sai1Div }
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#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir }
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#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx }
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#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx }
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#define I2S_WM8960_RX_MODE (1)
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#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
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{ \
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.hw_id = _hwid, \
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.fn = _fn, \
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.mode = _mode, \
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.name = MP_QSTR_##_pin, \
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.iomux = {_iomux}, \
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}
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#define I2S_GPIO_MAP \
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{ \
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I2S_GPIO(1, MCK, TX, GPIO_08, IOMUXC_GPIO_08_SAI1_MCLK), \
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I2S_GPIO(1, SCK, RX, GPIO_01, IOMUXC_GPIO_01_SAI1_RX_BCLK), \
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I2S_GPIO(1, WS, RX, GPIO_02, IOMUXC_GPIO_02_SAI1_RX_SYNC), \
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I2S_GPIO(1, SD, RX, GPIO_03, IOMUXC_GPIO_03_SAI1_RX_DATA00), \
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I2S_GPIO(1, SCK, TX, GPIO_06, IOMUXC_GPIO_06_SAI1_TX_BCLK), \
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I2S_GPIO(1, WS, TX, GPIO_07, IOMUXC_GPIO_07_SAI1_TX_SYNC), \
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I2S_GPIO(1, SD, TX, GPIO_04, IOMUXC_GPIO_04_SAI1_TX_DATA00), \
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}
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#define MICROPY_BOARD_ROOT_POINTERS \
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struct _machine_i2s_obj_t *machine_i2s_obj[MICROPY_HW_I2S_NUM];
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