circuitpython/stmhal/boards/stm32f4xx-af.csv

1	Port		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
2			SYS	TIM1/2	TIM3/4/5	TIM8/9/10/11	I2C1/2/3	SPI1/SPI2/I2S2/I2S2ext	SPI3/I2Sext/I2S3	USART1/2/3/I2S3ext	UART4/5/USART6	CAN1/CAN2/TIM12/13/14	OTG_FS/OTG_HS	ETH	FSMC/SDIO/OTG_FS	DCMI
3	PortA	PA0		TIM2_CH1_ETR	TIM5_CH1	TIM8_ETR				USART2_CTS	UART4_TX			ETH_MII_CRS				EVENTOUT
4	PortA	PA1		TIM2_CH2	TIM5_CH2					USART2_RTS	UART4_RX			ETH_MII_RX_CLK/ETH_RMII__REF_CLK				EVENTOUT
5	PortA	PA2		TIM2_CH3	TIM5_CH3	TIM9_CH1				USART2_TX				ETH_MDIO				EVENTOUT
6	PortA	PA3		TIM2_CH4	TIM5_CH4	TIM9_CH2				USART2_RX			OTG_HS_ULPI_D0	ETH_MII_COL				EVENTOUT
7	PortA	PA4						SPI1_NSS	SPI3_NSS/I2S3_WS	USART2_CK					OTG_HS_SOF	DCMI_HSYNC		EVENTOUT
8	PortA	PA5		TIM2_CH1_ETR		TIM8_CH1N		SPI1_SCK					OTG_HS_ULPI_CK					EVENTOUT
9	PortA	PA6		TIM1_BKIN	TIM3_CH1	TIM8_BKIN		SPI1_MISO				TIM13_CH1				DCMI_PIXCK		EVENTOUT
10	PortA	PA7		TIM1_CH1N	TIM3_CH2	TIM8_CH1N		SPI1_MOSI				TIM14_CH1		ETH_MII_RX_DV/ETH_RMII_CRS_DV				EVENTOUT
11	PortA	PA8	MCO1	TIM1_CH1			I2C3_SCL			USART1_CK			OTG_FS_SOF					EVENTOUT
12	PortA	PA9		TIM1_CH2			I2C3_SMBA			USART1_TX						DCMI_D0		EVENTOUT
13	PortA	PA10		TIM1_CH3						USART1_RX			OTG_FS_ID			DCMI_D1		EVENTOUT
14	PortA	PA11		TIM1_CH4						USART1_CTS		CAN1_RX	OTG_FS_DM					EVENTOUT
15	PortA	PA12		TIM1_ETR						USART1_RTS		CAN1_TX	OTG_FS_DP					EVENTOUT
16	PortA	PA13	JTMS-SWDIO															EVENTOUT
17	PortA	PA14	JTCK-SWCLK															EVENTOUT
18	PortA	PA15	JTDI	TIM2_CH1/TIM2_ETR				SPI1_NSS	SPI3_NSS/I2S3_WS									EVENTOUT
19	PortB	PB0		TIM1_CH2N	TIM3_CH3	TIM8_CH2N							OTG_HS_ULPI_D1	ETH_MII_RXD2				EVENTOUT
20	PortB	PB1		TIM1_CH3N	TIM3_CH4	TIM8_CH3N							OTG_HS_ULPI_D2	ETH_MII_RXD3				EVENTOUT
21	PortB	PB2																EVENTOUT
22	PortB	PB3	JTDO/TRACESWO	TIM2_CH2				SPI1_SCK	SPI3_SCKI2S3_CK									EVENTOUT
23	PortB	PB4	NJTRST		TIM3_CH1			SPI1_MISO	SPI3_MISO	I2S3ext_SD								EVENTOUT
24	PortB	PB5			TIM3_CH2		I2C1_SMBA	SPI1_MOSI	SPI3_MOSI/I2S3_SD			CAN2_RX	OTG_HS_ULPI_D7	ETH_PPS_OUT		DCMI_D10		EVENTOUT
25	PortB	PB6			TIM4_CH1		I2C1_SCL			USART1_TX		CAN2_TX				DCMI_D5		EVENTOUT
26	PortB	PB7			TIM4_CH2		I2C1_SDA			USART1_RX					FSMC_NL	DCMI_VSYNC		EVENTOUT
27	PortB	PB8			TIM4_CH3	TIM10_CH1	I2C1_SCL					CAN1_RX		ETH_MII_TXD3	SDIO_D4	DCMI_D6		EVENTOUT
28	PortB	PB9			TIM4_CH4	TIM11_CH1	I2C1_SDA	SPI2_NSS/I2S2_WS				CAN1_TX			SDIO_D5	DCMI_D7		EVENTOUT
29	PortB	PB10		TIM2_CH3			I2C2_SCL	SPI2_SCKI2S2_CK		USART3_TX			OTG_HS_ULPI_D3	ETH_MII_RX_ER				EVENTOUT
30	PortB	PB11		TIM2_CH4			I2C2_SDA			USART3_RX			OTG_HS_ULPI_D4	ETH_MII_TX_EN/ETH_RMII_TX_EN				EVENTOUT
31	PortB	PB12		TIM1_BKIN			I2C2_SMBA	SPI2_NSS/I2S2_WS		USART3_CK		CAN2_RX	OTG_HS_ULPI_D5	ETH_MII_TXD0/ETH_RMII_TXD0	OTG_HS_ID			EVENTOUT
32	PortB	PB13		TIM1_CH1N				SPI2_SCKI2S2_CK		USART3_CTS		CAN2_TX	OTG_HS_ULPI_D6	ETH_MII_TXD1/ETH_RMII_TXD1				EVENTOUT
33	PortB	PB14		TIM1_CH2N		TIM8_CH2N		SPI2_MISO	I2S2ext_SD	USART3_RTS		TIM12_CH1			OTG_HS_DM			EVENTOUT
34	PortB	PB15	RTC_REFIN	TIM1_CH3N		TIM8_CH3N		SPI2_MOSI/I2S2_SD				TIM12_CH2			OTG_HS_DP			EVENTOUT
35	PortC	PC0											OTG_HS_ULPI_STP					EVENTOUT
36	PortC	PC1												ETH_MDC				EVENTOUT
37	PortC	PC2						SPI2_MISO	I2S2ext_SD				OTG_HS_ULPI_DIR	ETH_MII_TXD2				EVENTOUT
38	PortC	PC3						SPI2_MOSI/I2S2_SD					OTG_HS_ULPI_NXT	ETH_MII_TX_CLK				EVENTOUT
39	PortC	PC4												ETH_MII_RXD0/ETH_RMII_RXD0				EVENTOUT
40	PortC	PC5												ETH_MII_RXD1/ETH_RMII_RXD1				EVENTOUT
41	PortC	PC6			TIM3_CH1	TIM8_CH1		I2S2_MCK			USART6_TX				SDIO_D6	DCMI_D0		EVENTOUT
42	PortC	PC7			TIM3_CH2	TIM8_CH2			I2S3_MCK		USART6_RX				SDIO_D7	DCMI_D1		EVENTOUT
43	PortC	PC8			TIM3_CH3	TIM8_CH3					USART6_CK				SDIO_D0	DCMI_D2		EVENTOUT
44	PortC	PC9	MCO2		TIM3_CH4	TIM8_CH4	I2C3_SDA	I2S_CKIN							SDIO_D1	DCMI_D3		EVENTOUT
45	PortC	PC10							SPI3_SCK/I2S3_CK	USART3_TX	UART4_TX				SDIO_D2	DCMI_D8		EVENTOUT
46	PortC	PC11						I2S3ext_SD	SPI3_MISO	USART3_RX	UART4_RX				SDIO_D3	DCMI_D4		EVENTOUT
47	PortC	PC12							SPI3_MOSI/I2S3_SD	USART3_CK	UART5_TX				SDIO_CK	DCMI_D9		EVENTOUT
48	PortC	PC13																EVENTOUT
49	PortC	PC14																EVENTOUT
50	PortC	PC15																EVENTOUT
51	PortD	PD0										CAN1_RX			FSMC_D2			EVENTOUT
52	PortD	PD1										CAN1_TX			FSMC_D3			EVENTOUT
53	PortD	PD2			TIM3_ETR						UART5_RX				SDIO_CMD	DCMI_D11		EVENTOUT
54	PortD	PD3								USART2_CTS					FSMC_CLK			EVENTOUT
55	PortD	PD4								USART2_RTS					FSMC_NOE			EVENTOUT
56	PortD	PD5								USART2_TX					FSMC_NWE			EVENTOUT
57	PortD	PD6								USART2_RX					FSMC_NWAIT			EVENTOUT
58	PortD	PD7								USART2_CK					FSMC_NE1/FSMC_NCE2			EVENTOUT
59	PortD	PD8								USART3_TX					FSMC_D13			EVENTOUT
60	PortD	PD9								USART3_RX					FSMC_D14			EVENTOUT
61	PortD	PD10								USART3_CK					FSMC_D15			EVENTOUT
62	PortD	PD11								USART3_CTS					FSMC_A16			EVENTOUT
63	PortD	PD12			TIM4_CH1					USART3_RTS					FSMC_A17			EVENTOUT
64	PortD	PD13			TIM4_CH2										FSMC_A18			EVENTOUT
65	PortD	PD14			TIM4_CH3										FSMC_D0			EVENTOUT
66	PortD	PD15			TIM4_CH4										FSMC_D1			EVENTOUT
67	PortE	PE0			TIM4_ETR										FSMC_NBL0	DCMI_D2		EVENTOUT
68	PortE	PE1													FSMC_NBL1	DCMI_D3		EVENTOUT
69	PortE	PE2	TRACECLK											ETH_MII_TXD3	FSMC_A23			EVENTOUT
70	PortE	PE3	TRACED0												FSMC_A19			EVENTOUT
71	PortE	PE4	TRACED1												FSMC_A20	DCMI_D4		EVENTOUT
72	PortE	PE5	TRACED2			TIM9_CH1									FSMC_A21	DCMI_D6		EVENTOUT
73	PortE	PE6	TRACED3			TIM9_CH2									FSMC_A22	DCMI_D7		EVENTOUT
74	PortE	PE7		TIM1_ETR											FSMC_D4			EVENTOUT
75	PortE	PE8		TIM1_CH1N											FSMC_D5			EVENTOUT
76	PortE	PE9		TIM1_CH1											FSMC_D6			EVENTOUT
77	PortE	PE10		TIM1_CH2N											FSMC_D7			EVENTOUT
78	PortE	PE11		TIM1_CH2											FSMC_D8			EVENTOUT
79	PortE	PE12		TIM1_CH3N											FSMC_D9			EVENTOUT
80	PortE	PE13		TIM1_CH3											FSMC_D10			EVENTOUT
81	PortE	PE14		TIM1_CH4											FSMC_D11			EVENTOUT
82	PortE	PE15		TIM1_BKIN											FSMC_D12			EVENTOUT
83	PortF	PF0					I2C2_SDA								FSMC_A0			EVENTOUT
84	PortF	PF1					I2C2_SCL								FSMC_A1			EVENTOUT
85	PortF	PF2					I2C2_SMBA								FSMC_A2			EVENTOUT
86	PortF	PF3													FSMC_A3			EVENTOUT
87	PortF	PF4													FSMC_A4			EVENTOUT
88	PortF	PF5													FSMC_A5			EVENTOUT
89	PortF	PF6				TIM10_CH1									FSMC_NIORD			EVENTOUT
90	PortF	PF7				TIM11_CH1									FSMC_NREG			EVENTOUT
91	PortF	PF8										TIM13_CH1			FSMC_NIOWR			EVENTOUT
92	PortF	PF9										TIM14_CH1			FSMC_CD			EVENTOUT
93	PortF	PF10													FSMC_INTR			EVENTOUT
94	PortF	PF11														DCMI_D12		EVENTOUT
95	PortF	PF12													FSMC_A6			EVENTOUT
96	PortF	PF13													FSMC_A7			EVENTOUT
97	PortF	PF14													FSMC_A8			EVENTOUT
98	PortF	PF15													FSMC_A9			EVENTOUT
99	PortG	PG0													FSMC_A10			EVENTOUT
100	PortG	PG1													FSMC_A11			EVENTOUT
101	PortG	PG2													FSMC_A12			EVENTOUT
102	PortG	PG3													FSMC_A13			EVENTOUT
103	PortG	PG4													FSMC_A14			EVENTOUT
104	PortG	PG5													FSMC_A15			EVENTOUT
105	PortG	PG6													FSMC_INT2			EVENTOUT
106	PortG	PG7									USART6_CK				FSMC_INT3			EVENTOUT
107	PortG	PG8									USART6_RTS			ETH_PPS_OUT				EVENTOUT
108	PortG	PG9									USART6_RX				FSMC_NE2/FSMC_NCE3			EVENTOUT
109	PortG	PG10													FSMC_NCE4_1/FSMC_NE3			EVENTOUT
110	PortG	PG11												ETH_MII_TX_EN/ETH_RMII_TX_EN	FSMC_NCE4_2			EVENTOUT
111	PortG	PG12									USART6_RTS				FSMC_NE4			EVENTOUT
112	PortG	PG13									USART6_CTS			ETH_MII_TXD0/ETH_RMII_TXD0	FSMC_A24			EVENTOUT
113	PortG	PG14									USART6_TX			ETH_MII_TXD1/ETH_RMII_TXD1	FSMC_A25			EVENTOUT
114	PortG	PG15									USART6_CTS					DCMI_D13		EVENTOUT
115	PortH	PH0																EVENTOUT
116	PortH	PH1																EVENTOUT
117	PortH	PH2												ETH_MII_CRS				EVENTOUT
118	PortH	PH3												ETH_MII_COL				EVENTOUT
119	PortH	PH4					I2C2_SCL						OTG_HS_ULPI_NXT					EVENTOUT
120	PortH	PH5					I2C2_SDA											EVENTOUT
121	PortH	PH6					I2C2_SMBA					TIM12_CH1		ETH_MII_RXD2				EVENTOUT
122	PortH	PH7					I2C3_SCL							ETH_MII_RXD3				EVENTOUT
123	PortH	PH8					I2C3_SDA									DCMI_HSYNC		EVENTOUT
124	PortH	PH9					I2C3_SMBA					TIM12_CH2				DCMI_D0		EVENTOUT
125	PortH	PH10			TIM5_CH1											DCMI_D1		EVENTOUT
126	PortH	PH11			TIM5_CH2											DCMI_D2		EVENTOUT
127	PortH	PH12			TIM5_CH3											DCMI_D3		EVENTOUT
128	PortH	PH13				TIM8_CH1N						CAN1_TX						EVENTOUT
129	PortH	PH14				TIM8_CH2N										DCMI_D4		EVENTOUT
130	PortH	PH15				TIM8_CH3N										DCMI_D11		EVENTOUT
131	PortI	PI0			TIM5_CH4			SPI2_NSS/I2S2_WS								DCMI_D13		EVENTOUT
132	PortI	PI1						SPI2_SCKI2S2_CK								DCMI_D8		EVENTOUT
133	PortI	PI2				TIM8_CH4		SPI2_MISO	I2S2ext_SD							DCMI_D9		EVENTOUT
134	PortI	PI3				TIM8_ETR		SPI2_MOSI/I2S2_SD								DCMI_D10		EVENTOUT
135	PortI	PI4				TIM8_BKIN										DCMI_D5		EVENTOUT
136	PortI	PI5				TIM8_CH1										DCMI_VSYNC		EVENTOUT
137	PortI	PI6				TIM8_CH2										DCMI_D6		EVENTOUT
138	PortI	PI7				TIM8_CH3										DCMI_D7		EVENTOUT
139	PortI	PI8																EVENTOUT
140	PortI	PI9										CAN1_RX						EVENTOUT
141	PortI	PI10												ETH_MII_RX_ER				EVENTOUT
142	PortI	PI11											OTG_HS_ULPI_DIR					EVENTOUT