circuitpython/MIMXRT1021_af.csv at 6a3bc0e1a1f4dc0ad0b71ca0f168ad1a87d28859

robert-hh 81f706aee4 mimxrt: Support PWM using the FLEXPWM and QTMR modules.

Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the
duty cycle.  The basic API is supported as documentated, except that
keyword parameters are accepted for both the instatiaton and the
PWM.init() call.

Extensions: support PWM for channel pairs.  Channel pairs are declared by
supplying 2-element tuples for the pins.  The two channels of a pair must
be the A/B channel of a FLEXPWM module.  These form than a complementary
pair.

Additional supported keyword arguments:

- center=value Defines the center position of a pulse within the pulse
  cycle.  The align keyword is actually shortcut for center.

- sync=True|False: If set to True, the channels will be synchronized to a
  submodule 0 channel, which has already to be enabled.

- align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized
  channels are Center-Aligned or Edge-aligned.  The channels must be either
  complementary a channel pair or a group of synchronized channels.  It may
  as well be applied to a single channel, but withiout any benefit.

- invert= 0..3. Controls ouput inversion of the pins.  Bit 0 controls the
  first pin, bit 1 the second.

- deadtime=time_ns time of complementary channels for delaying the rising
  slope.

- xor=0|1|2 xor causes the output of channel A and B to be xored.  If
  applied to a X channel, it shows the value oif A ^ B.  If applied to an A
  or B channel, both channel show the xored signal for xor=1.  For xor=2,
  the xored signal is split between channels A and B.  See also the
  Reference Manual, chapter about double pulses.  The behavior of xor=2 can
  also be achieved using the center method for locating a pulse within a
  clock period.

The output is enabled for board pins only.

CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal
will not be routed to the output.  That applies only to FLEXPWM pins.  The
use of QTMR pins which are not board pins will be rejected.

As part of this commit, the _WFE() statement is removed from
ticks_delay_us64() to prevent PWM glitching during calls to sleep().

2021-11-24 13:48:27 +11:00

11 KiB

Raw Blame History

1	Pad	ALT0	ALT1	ALT2	ALT3	ALT4	ALT5	ALT6	ALT7	ADC	ACMP	Default
2	GPIO_AD_B0_00	JTAG_TMS					GPIO1_IO00	USBPHY1_TSTI_TX_EN	GPT1_COMPARE1			ALT0
3	GPIO_AD_B0_01	JTAG_TCK					GPIO1_IO01	USBPHY1_TSTI_TX_HIZ	GPT1_CAPTURE2			ALT0
4	GPIO_AD_B0_02	JTAG_MOD					GPIO1_IO02	USBPHY1_TSTI_TX_LS_MODE	GPT1_CAPTURE1			ALT0
5	GPIO_AD_B0_03	JTAG_TDI	USDHC2_CD_B	WDOG1_B	SAI1_MCLK	USDHC1_WP	GPIO1_IO03	USB_OTG1_OC	CCM_PMIC_RDY			ALT0
6	GPIO_AD_B0_04	JTAG_TDO	FLEXCAN1_TX	USDHC1_WP	TMR2_TIMER0	ENET_MDIO	GPIO1_IO04	USB_OTG1_PWR	EWM_OUT_B			ALT0
7	GPIO_AD_B0_05	JTAG_TRSTB	FLEXCAN1_RX	USDHC1_CD_B	TMR2_TIMER1	ENET_MDC	GPIO1_IO05	USB_OTG1_ID	ARM_NMI			ALT0
8	GPIO_AD_B0_06	PIT_TRIGGER0	MQS_RIGHT	LPUART1_TXD	TMR2_TIMER2	FLEXPWM2_PWM3_A	GPIO1_IO06	REF_32K_OUT				ALT5
9	GPIO_AD_B0_07	PIT_TRIGGER1	MQS_LEFT	LPUART1_RXD	TMR2_TIMER3	FLEXPWM2_PWM3_B	GPIO1_IO07	REF_24M_OUT				ALT5
10	GPIO_AD_B0_08	ENET_TX_CLK	LPI2C3_SCL	LPUART1_CTS_B	KPP_COL0	ENET_REF_CLK	GPIO1_IO08	ARM_CM7_TXEV			ACMP1_IN4	ALT5
11	GPIO_AD_B0_09	ENET_RX_DATA1	LPI2C3_SDA	LPUART1_RTS_B	KPP_ROW0		GPIO1_IO09	ARM_CM7_RXEV			ACMP2_IN4	ALT5
12	GPIO_AD_B0_10	ENET_RX_DATA0	LPSPI1_SCK	LPUART5_TXD	KPP_COL1	FLEXPWM2_PWM2_A	GPIO1_IO10	ARM_TRACE_CLK			ACMP3_IN4	ALT5
13	GPIO_AD_B0_11	ENET_RX_EN	LPSPI1_PCS0	LPUART5_RXD	KPP_ROW1	FLEXPWM2_PWM2_B	GPIO1_IO11	ARM_TRACE_SWO			ACMP4_IN4	ALT5
14	GPIO_AD_B0_12	ENET_RX_ER	LPSPI1_SDO	LPUART3_CTS_B	KPP_COL2	FLEXPWM2_PWM1_A	GPIO1_IO12	ARM_TRACE0	SNVS_VIO_5_CTL	ADC1_IN0		ALT5
15	GPIO_AD_B0_13	ENET_TX_EN	LPSPI1_SDI	LPUART3_RTS_B	KPP_ROW2	FLEXPWM2_PWM1_B	GPIO1_IO13		SNVS_VIO_5_B	ADC2_IN0		ALT5
16	GPIO_AD_B0_14	ENET_TX_DATA0	FLEXCAN2_TX	LPUART3_TXD	KPP_COL3	FLEXPWM2_PWM0_A	GPIO1_IO14		WDOG1_ANY	ADC1_IN1,ADC2_IN1	ACMP1_IN0,ACMP2_IN0,ACMP3_IN0,ACMP4_IN0	ALT5
17	GPIO_AD_B0_15	ENET_TX_DATA1	FLEXCAN2_RX	LPUART3_RXD	KPP_ROW3	FLEXPWM2_PWM0_B	GPIO1_IO15			ADC1_IN2,ADC2_IN2	ACMP1_IN1,ACMP2_IN1,ACMP3_IN1,ACMP4_IN1	ALT5
18	GPIO_AD_B1_00	SEMC_RDY	FLEXSPI_A_DATA3	FLEXCAN2_TX	SAI1_MCLK	FLEXIO1_D15	GPIO1_IO16	ENET_1588_EVENT2_OUT	KPP_COL4		ACMP1_IN2	ALT5
19	GPIO_AD_B1_01	SEMC_CSX0	FLEXSPI_A_SCLK	FLEXCAN2_RX	SAI1_TX_BCLK	FLEXIO1_D14	GPIO1_IO17	ENET_1588_EVENT2_IN	KPP_ROW4	ADC1_IN3	ACMP2_IN2	ALT5
20	GPIO_AD_B1_02	SEMC_CSX1	FLEXSPI_A_DATA0	LPSPI4_SCK	SAI1_TX_SYNC	FLEXIO1_D13	GPIO1_IO18	ENET_1588_EVENT3_OUT	KPP_COL5	ADC2_IN3	ACMP3_IN2	ALT5
21	GPIO_AD_B1_03	SEMC_CSX2	FLEXSPI_A_DATA2	LPSPI4_PCS0	SAI1_TX_DATA0	FLEXIO1_D12	GPIO1_IO19	ENET_1588_EVENT3_IN	KPP_ROW5	ADC1_IN4	ACMP4_IN2	ALT5
22	GPIO_AD_B1_04	SEMC_CSX3	FLEXSPI_A_DATA1	LPSPI4_SDO	SAI1_RX_SYNC	FLEXIO1_D11	GPIO1_IO20	LPSPI1_PCS1	KPP_COL6	ADC2_IN4	ACMP1_IN3	ALT5
23	GPIO_AD_B1_05	USDHC1_WP	FLEXSPI_A_SS0_B	LPSPI4_SDI	SAI1_RX_DATA0	FLEXIO1_D10	GPIO1_IO21	LPSPI1_PCS2	KPP_ROW6	ADC1_IN5,ADC2_IN5	ACMP2_IN3	ALT5
24	GPIO_AD_B1_06	USDHC1_RESET_B	FLEXPWM1_PWM0_A	LPUART2_CTS_B	SAI1_RX_BCLK	FLEXIO1_D09	GPIO1_IO22	LPSPI1_PCS3	KPP_COL7	ADC1_IN6,ADC2_IN6	ACMP3_IN3	ALT5
25	GPIO_AD_B1_07	USDHC1_VSELECT	FLEXPWM1_PWM0_B	LPUART2_RTS_B	SAI1_TX_DATA1	FLEXIO1_D08	GPIO1_IO23	LPSPI3_PCS3	KPP_ROW7	ADC1_IN7,ADC2_IN7	ACMP4_IN3	ALT5
26	GPIO_AD_B1_08	LPI2C2_SCL	FLEXPWM1_PWM1_A	LPUART2_TXD	SAI1_TX_DATA2	FLEXIO1_D07	GPIO1_IO24	LPSPI3_PCS2	XBAR_INOUT12	ADC1_IN8,ADC2_IN8	ACMP1_IN5	ALT5
27	GPIO_AD_B1_09	LPI2C2_SDA	FLEXPWM1_PWM1_B	LPUART2_RXD	SAI1_TX_DATA3	FLEXIO1_D06	GPIO1_IO25	LPSPI3_PCS1	XBAR_INOUT13	ADC1_IN9,ADC2_IN9	ACMP2_IN5	ALT5
28	GPIO_AD_B1_10	USB_OTG1_PWR	FLEXPWM1_PWM2_A	LPUART4_TXD	USDHC1_CD_B	FLEXIO1_D05	GPIO1_IO26	GPT2_CAPTURE1		ADC1_IN10,ADC2_IN10	ACMP3_IN5	ALT5
29	GPIO_AD_B1_11	USB_OTG1_ID	FLEXPWM1_PWM2_B	LPUART4_RXD	USDHC1_WP	FLEXIO1_D04	GPIO1_IO27	GPT2_COMPARE1		ADC1_IN11,ADC2_IN11	ACMP4_IN5	ALT5
30	GPIO_AD_B1_12	USB_OTG1_OC	ACMP1_OUT	LPSPI3_SCK	USDHC2_CD_B	FLEXIO1_D03	GPIO1_IO28	FLEXPWM1_PWM3_A		ADC1_IN12,ADC2_IN12	ACMP1_IN6,ACMP1_OUT	ALT5
31	GPIO_AD_B1_13	LPI2C1_HREQ	ACMP2_OUT	LPSPI3_PCS0	USDHC2_WP	FLEXIO1_D02	GPIO1_IO29	FLEXPWM1_PWM3_B		ADC1_IN13,ADC2_IN13	ACMP2_IN6,ACMP2_OUT	ALT5
32	GPIO_AD_B1_14	LPI2C1_SCL	ACMP3_OUT	LPSPI3_SDO	ENET_1588_EVENT0_OUT	FLEXIO1_D01	GPIO1_IO30			ADC1_IN14,ADC2_IN14	ACMP3_IN6,ACMP3_OUT	ALT5
33	GPIO_AD_B1_15	LPI2C1_SDA	ACMP4_OUT	LPSPI3_SDI	ENET_1588_EVENT0_IN	FLEXIO1_D00	GPIO1_IO31			ADC1_IN15,ADC2_IN15	ACMP4_IN6,ACMP4_OUT	ALT5
34	GPIO_EMC_00	SEMC_DA00	TMR2_TIMER0	LPUART4_CTS_B	SPDIF_SR_CLK	LPSPI2_SCK	GPIO2_IO00	FLEXCAN1_TX	PIT_TRIGGER2			ALT5
35	GPIO_EMC_01	SEMC_DA01	TMR2_TIMER1	LPUART4_RTS_B	SPDIF_OUT	LPSPI2_PCS0	GPIO2_IO01	FLEXCAN1_RX	PIT_TRIGGER3			ALT5
36	GPIO_EMC_02	SEMC_DA02	TMR2_TIMER2	LPUART4_TXD	SPDIF_LOCK	LPSPI2_SDO	GPIO2_IO02	LPI2C1_SCL				ALT5
37	GPIO_EMC_03	SEMC_DA03	TMR2_TIMER3	LPUART4_RXD	SPDIF_EXT_CLK	LPSPI2_SDI	GPIO2_IO03	LPI2C1_SDA				ALT5
38	GPIO_EMC_04	SEMC_DA04	XBAR_INOUT04	SPDIF_OUT	SAI2_TX_BCLK	FLEXIO1_D16	GPIO2_IO04	USBPHY1_TSTO_PLL_CLK20DIV				ALT5
39	GPIO_EMC_05	SEMC_DA05	XBAR_INOUT05	SPDIF_IN	SAI2_TX_SYNC	FLEXIO1_D17	GPIO2_IO05	USBPHY1_TSTI_TX_HS_MODE				ALT5
40	GPIO_EMC_06	SEMC_DA06	XBAR_INOUT06	LPUART3_TXD	SAI2_TX_DATA	FLEXIO1_D18	GPIO2_IO06	USBPHY1_TSTI_TX_DN				ALT5
41	GPIO_EMC_07	SEMC_DA07	XBAR_INOUT07	LPUART3_RXD	SAI2_RX_SYNC	FLEXIO1_D19	GPIO2_IO07	USBPHY1_TSTO_RX_SQUELCH				ALT5
42	GPIO_EMC_08	SEMC_DM0	XBAR_INOUT08	FLEXCAN2_TX	SAI2_RX_DATA	FLEXIO1_D20	GPIO2_IO08	USBPHY1_TSTO_RX_DISCON_DET				ALT5
43	GPIO_EMC_09	SEMC_WE	XBAR_INOUT09	FLEXCAN2_RX	SAI2_RX_BCLK	FLEXIO1_D21	GPIO2_IO09	USBPHY1_TSTO_RX_HS_RXD				ALT5
44	GPIO_EMC_10	SEMC_CAS	XBAR_INOUT10	LPI2C4_SDA	SAI1_TX_SYNC	LPSPI2_SCK	GPIO2_IO10	FLEXPWM2_PWM0_X				ALT5
45	GPIO_EMC_11	SEMC_RAS	XBAR_INOUT11	LPI2C4_SCL	SAI1_TX_BCLK	LPSPI2_PCS0	GPIO2_IO11	FLEXPWM2_PWM1_X				ALT5
46	GPIO_EMC_12	SEMC_CS0	XBAR_INOUT12	LPUART6_TXD	SAI1_TX_DATA0	LPSPI2_SDO	GPIO2_IO12	FLEXPWM2_PWM2_X				ALT5
47	GPIO_EMC_13	SEMC_BA0	XBAR_INOUT13	LPUART6_RXD	SAI1_RX_DATA0	LPSPI2_SDI	GPIO2_IO13	FLEXPWM2_PWM3_X	CCM_PMIC_RDY			ALT5
48	GPIO_EMC_14	SEMC_BA1	XBAR_INOUT14	LPUART6_CTS_B	SAI1_RX_BCLK	LPSPI2_PCS1	GPIO2_IO14	FLEXCAN1_TX				ALT5
49	GPIO_EMC_15	SEMC_ADDR10	XBAR_INOUT15	LPUART6_RTS_B	SAI1_RX_SYNC	WDOG1_B	GPIO2_IO15	FLEXCAN1_RX				ALT5
50	GPIO_EMC_16	SEMC_ADDR00		MQS_RIGHT	SAI2_MCLK		GPIO2_IO16	SRC_BOOT_MODE0				ALT5
51	GPIO_EMC_17	SEMC_ADDR01		MQS_LEFT	SAI3_MCLK		GPIO2_IO17	SRC_BOOT_MODE1				ALT5
52	GPIO_EMC_18	SEMC_ADDR02	XBAR_INOUT16	LPI2C2_SDA	SAI1_RX_SYNC	FLEXIO1_D22	GPIO2_IO18	SRC_BT_CFG0				ALT5
53	GPIO_EMC_19	SEMC_ADDR03	XBAR_INOUT17	LPI2C2_SCL	SAI1_RX_BCLK	FLEXIO1_D23	GPIO2_IO19	SRC_BT_CFG1				ALT5
54	GPIO_EMC_20	SEMC_ADDR04	FLEXPWM1_PWM3_A	LPUART2_CTS_B	SAI1_MCLK	FLEXIO1_D24	GPIO2_IO20	SRC_BT_CFG2				ALT5
55	GPIO_EMC_21	SEMC_ADDR05	FLEXPWM1_PWM3_B	LPUART2_RTS_B	SAI1_RX_DATA0	FLEXIO1_D25	GPIO2_IO21	SRC_BT_CFG3				ALT5
56	GPIO_EMC_22	SEMC_ADDR06	FLEXPWM1_PWM2_A	LPUART2_TXD	SAI1_TX_DATA3	FLEXIO1_D26	GPIO2_IO22	SRC_BT_CFG4				ALT5
57	GPIO_EMC_23	SEMC_ADDR07	FLEXPWM1_PWM2_B	LPUART2_RXD	SAI1_TX_DATA2	FLEXIO1_D27	GPIO2_IO23	SRC_BT_CFG5				ALT5
58	GPIO_EMC_24	SEMC_ADDR08	FLEXPWM1_PWM1_A	LPUART8_CTS_B	SAI1_TX_DATA1	FLEXIO1_D28	GPIO2_IO24	SRC_BT_CFG6				ALT5
59	GPIO_EMC_25	SEMC_ADDR09	FLEXPWM1_PWM1_B	LPUART8_RTS_B	SAI1_TX_DATA0	FLEXIO1_D29	GPIO2_IO25	SRC_BT_CFG7				ALT5
60	GPIO_EMC_26	SEMC_ADDR11	FLEXPWM1_PWM0_A	LPUART8_TXD	SAI1_TX_BCLK	FLEXIO1_D30	GPIO2_IO26	SRC_BT_CFG8				ALT5
61	GPIO_EMC_27	SEMC_ADDR12	FLEXPWM1_PWM0_B	LPUART8_RXD	SAI1_TX_SYNC	FLEXIO1_D31	GPIO2_IO27	SRC_BT_CFG9				ALT5
62	GPIO_EMC_28	SEMC_DQS	FLEXPWM2_PWM3_A	XBAR_INOUT18	SAI3_MCLK	EWM_OUT_B	GPIO2_IO28	GPT2_CAPTURE2	FLEXPWM1_PWM0_X			ALT5
63	GPIO_EMC_29	SEMC_CKE	FLEXPWM2_PWM3_B	XBAR_INOUT19	SAI3_RX_BCLK	WDOG2_RST_B_DEB	GPIO2_IO29	GPT2_COMPARE2	FLEXPWM1_PWM1_X			ALT5
64	GPIO_EMC_30	SEMC_CLK	FLEXPWM2_PWM2_A	LPUART4_CTS_B	SAI3_RX_SYNC	WDOG1_RST_B_DEB	GPIO2_IO30	GPT2_COMPARE3	FLEXPWM1_PWM2_X			ALT5
65	GPIO_EMC_31	SEMC_DM1	FLEXPWM2_PWM2_B	LPUART4_RTS_B	SAI3_RX_DATA	WDOG2_B	GPIO2_IO31	GPT2_CLK	FLEXPWM1_PWM3_X			ALT5
66	GPIO_EMC_32	SEMC_DA08	TMR1_TIMER0	LPUART4_TXD	SAI3_TX_DATA	LPSPI4_SCK	GPIO3_IO00	USBPHY1_TSTO_RX_FS_RXD	REF_24M_OUT			ALT5
67	GPIO_EMC_33	SEMC_DA09	TMR1_TIMER1	LPUART4_RXD	SAI3_TX_BCLK	LPSPI4_PCS0	GPIO3_IO01	USBPHY1_TSTI_TX_DP	SRC_TESTER_ACK			ALT5
68	GPIO_EMC_34	SEMC_DA10	TMR1_TIMER2	LPUART7_TXD	SAI3_TX_SYNC	LPSPI4_SDO	GPIO3_IO02	ENET_CRS				ALT5
69	GPIO_EMC_35	SEMC_DA11	TMR1_TIMER3	LPUART7_RXD	USDHC2_WP	LPSPI4_SDI	GPIO3_IO03	ENET_COL				ALT5
70	GPIO_EMC_36	SEMC_DA12	FLEXPWM2_PWM1_A	LPUART5_CTS_B	CCM_PMIC_RDY	LPSPI4_PCS1	GPIO3_IO04	ENET_RX_CLK	USDHC1_WP			ALT5
71	GPIO_EMC_37	SEMC_DA13	FLEXPWM2_PWM1_B	LPUART5_RTS_B	MQS_RIGHT	LPSPI4_PCS2	GPIO3_IO05	ENET_RX_DATA3	USDHC1_VSELECT			ALT5
72	GPIO_EMC_38	SEMC_DA14	FLEXPWM2_PWM0_A	LPUART5_TXD	MQS_LEFT	LPSPI4_PCS3	GPIO3_IO06	ENET_RX_DATA2	USDHC1_CD_B			ALT5
73	GPIO_EMC_39	SEMC_DA15	FLEXPWM2_PWM0_B	LPUART5_RXD	USB_OTG1_OC	WDOG1_B	GPIO3_IO07	ENET_TX_ER	GPT1_CLK			ALT5
74	GPIO_EMC_40	SEMC_CSX0	XBAR_INOUT18	SPDIF_OUT	USB_OTG1_ID	ENET_MDIO	GPIO3_IO08	ENET_TX_DATA3	GPT1_COMPARE3			ALT5
75	GPIO_EMC_41	SEMC_RDY	XBAR_INOUT19	SPDIF_IN	USB_OTG1_PWR	ENET_MDC	GPIO3_IO09	ENET_TX_DATA2	GPT1_COMPARE2			ALT5
76	GPIO_SD_B0_00	USDHC1_DATA2	TMR1_TIMER0	SAI1_MCLK	SAI2_MCLK	LPI2C3_SCL	GPIO3_IO13	FLEXSPI_A_SS1_B	XBAR_INOUT14			ALT5
77	GPIO_SD_B0_01	USDHC1_DATA3	TMR1_TIMER1	REF_24M_OUT	SAI2_RX_SYNC	LPI2C3_SDA	GPIO3_IO14	FLEXSPI_B_SS1_B	XBAR_INOUT15			ALT5
78	GPIO_SD_B0_02	USDHC1_CMD	TMR1_TIMER2	LPUART7_CTS_B	SAI2_RX_BCLK	LPSPI1_SCK	GPIO3_IO15	ENET_MDIO	XBAR_INOUT16			ALT5
79	GPIO_SD_B0_03	USDHC1_CLK	TMR1_TIMER3	LPUART7_RTS_B	SAI2_RX_DATA	LPSPI1_PCS0	GPIO3_IO16	ENET_MDC				ALT5
80	GPIO_SD_B0_04	USDHC1_DATA0	FLEXCAN2_TX	LPUART7_TXD	SAI2_TX_DATA	LPSPI1_SDO	GPIO3_IO17	FLEXSPI_B_SS0_B				ALT5
81	GPIO_SD_B0_05	USDHC1_DATA1	FLEXCAN2_RX	LPUART7_RXD	SAI2_TX_BCLK	LPSPI1_SDI	GPIO3_IO18	FLEXSPI_B_DQS				ALT5
82	GPIO_SD_B0_06	USDHC1_CD_B	USDHC1_RESET_B	REF_32K_OUT	SAI2_TX_SYNC	WDOG1_B	GPIO3_IO19	XBAR_INOUT17				ALT5
83	GPIO_SD_B1_00	USDHC2_DATA2	FLEXSPI_B_DATA3	LPUART6_TXD	XBAR_INOUT10	FLEXCAN1_TX	GPIO3_IO20					ALT5
84	GPIO_SD_B1_01	USDHC2_DATA3	FLEXSPI_B_SCLK	LPUART6_RXD	FLEXSPI_A_SS1_B	FLEXCAN1_RX	GPIO3_IO21					ALT5
85	GPIO_SD_B1_02	USDHC2_CMD	FLEXSPI_B_DATA0	LPUART8_TXD	LPI2C4_SCL	ENET_1588_EVENT1_OUT	GPIO3_IO22	CCM_CLKO1				ALT5
86	GPIO_SD_B1_03	USDHC2_CLK	FLEXSPI_B_DATA2	LPUART8_RXD	LPI2C4_SDA	ENET_1588_EVENT1_IN	GPIO3_IO23	CCM_CLKO2				ALT5
87	GPIO_SD_B1_04	USDHC2_DATA0	FLEXSPI_B_DATA1	ENET_TX_CLK	ENET_REF_CLK	EWM_OUT_B	GPIO3_IO24	CCM_WAIT				ALT5
88	GPIO_SD_B1_05	USDHC2_DATA1	FLEXSPI_A_DQS	ENET_RX_DATA1	SAI3_MCLK	FLEXSPI_B_SS0_B	GPIO3_IO25	CCM_PMIC_RDY				ALT5
89	GPIO_SD_B1_06	USDHC2_CD_B	FLEXSPI_A_DATA3	ENET_RX_DATA0	SAI3_TX_BCLK	LPSPI2_PCS0	GPIO3_IO26	CCM_STOP				ALT5
90	GPIO_SD_B1_07	USDHC2_RESET_B	FLEXSPI_A_SCLK	ENET_RX_EN	SAI3_TX_SYNC	LPSPI2_SCK	GPIO3_IO27					ALT5
91	GPIO_SD_B1_08	USDHC2_DATA4	FLEXSPI_A_DATA0	ENET_RX_ER	SAI3_TX_DATA	LPSPI2_SDO	GPIO3_IO28					ALT5
92	GPIO_SD_B1_09	USDHC2_DATA5	FLEXSPI_A_DATA2	ENET_TX_EN	SAI3_RX_BCLK	LPSPI2_SDI	GPIO3_IO29	CCM_REF_EN_B				ALT5
93	GPIO_SD_B1_10	USDHC2_DATA6	FLEXSPI_A_DATA1	ENET_TX_DATA0	SAI3_RX_SYNC	LPSPI2_PCS2	GPIO3_IO30	SRC_SYSTEM_RESET				ALT5
94	GPIO_SD_B1_11	USDHC2_DATA7	FLEXSPI_A_SS0_B	ENET_TX_DATA1	SAI3_RX_DATA	LPSPI2_PCS3	GPIO3_IO31	SRC_EARLY_RESET				ALT5

11 KiB Raw Blame History

11 KiB

Raw Blame History