256 lines
10 KiB
C
256 lines
10 KiB
C
/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "shared_dma.h"
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#include "py/gc.h"
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#include "py/mpstate.h"
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#include "asf/sam0/drivers/events/events.h"
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#include "asf/sam0/drivers/system/interrupt/system_interrupt.h"
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#include "asf/sam0/drivers/tc/tc.h"
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#undef ENABLE
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// We allocate two DMA resources for the entire lifecycle of the board (not the
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// vm) because the general_dma resource will be shared between the REPL and SPI
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// flash. Both uses must block each other in order to prevent conflict.
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struct dma_resource audio_dma;
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struct dma_resource general_dma_tx;
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struct dma_resource general_dma_rx;
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void init_shared_dma(void) {
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struct dma_resource_config config;
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dma_get_config_defaults(&config);
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// This allocates the lowest channel first so make sure the audio is first
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// so it gets the highest priority.
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config.peripheral_trigger = DAC_DMAC_ID_EMPTY;
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config.trigger_action = DMA_TRIGGER_ACTION_BEAT;
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config.event_config.input_action = DMA_EVENT_INPUT_TRIG;
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config.event_config.event_output_enable = true;
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dma_allocate(&audio_dma, &config);
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// Turn on the transfer complete interrupt so that the job_status changes to done.
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g_chan_interrupt_flag[audio_dma.channel_id] |= (1UL << DMA_CALLBACK_TRANSFER_DONE);
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// Prioritize the RX channel over the TX channel because TX can cause an RX
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// overflow.
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dma_get_config_defaults(&config);
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config.trigger_action = DMA_TRIGGER_ACTION_BEAT;
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config.event_config.input_action = DMA_EVENT_INPUT_TRIG;
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dma_allocate(&general_dma_rx, &config);
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g_chan_interrupt_flag[general_dma_rx.channel_id] |= (1UL << DMA_CALLBACK_TRANSFER_DONE);
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dma_get_config_defaults(&config);
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config.trigger_action = DMA_TRIGGER_ACTION_BEAT;
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config.event_config.input_action = DMA_EVENT_INPUT_TRIG;
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dma_allocate(&general_dma_tx, &config);
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g_chan_interrupt_flag[general_dma_tx.channel_id] |= (1UL << DMA_CALLBACK_TRANSFER_DONE);
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// Be sneaky and reuse the active descriptor memory.
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audio_dma.descriptor = &descriptor_section[audio_dma.channel_id];
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general_dma_rx.descriptor = &descriptor_section[general_dma_rx.channel_id];
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general_dma_tx.descriptor = &descriptor_section[general_dma_tx.channel_id];
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}
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static uint8_t sercom_index(Sercom* sercom) {
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return ((uint32_t) sercom - (uint32_t) SERCOM0) / 0x400;
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}
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static void dma_configure(uint8_t channel, uint8_t trigsrc, bool output_event) {
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system_interrupt_enter_critical_section();
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/** Select the DMA channel and clear software trigger */
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DMAC->CHID.reg = DMAC_CHID_ID(channel);
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DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
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DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
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DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << channel));
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uint32_t event_output_enable = 0;
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if (output_event) {
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event_output_enable = DMAC_CHCTRLB_EVOE;
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}
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DMAC->CHCTRLB.reg = DMAC_CHCTRLB_LVL(DMA_PRIORITY_LEVEL_0) |
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DMAC_CHCTRLB_TRIGSRC(trigsrc) |
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DMAC_CHCTRLB_TRIGACT(DMA_TRIGGER_ACTION_BEAT) |
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event_output_enable;
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system_interrupt_leave_critical_section();
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}
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enum status_code shared_dma_write(Sercom* sercom, const uint8_t* buffer, uint32_t length) {
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if (general_dma_tx.job_status != STATUS_OK) {
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return general_dma_tx.job_status;
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}
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dma_configure(general_dma_tx.channel_id, sercom_index(sercom) * 2 + 2, false);
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// Set up TX second.
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struct dma_descriptor_config descriptor_config;
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dma_descriptor_get_config_defaults(&descriptor_config);
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descriptor_config.beat_size = DMA_BEAT_SIZE_BYTE;
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descriptor_config.dst_increment_enable = false;
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descriptor_config.block_transfer_count = length;
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descriptor_config.source_address = ((uint32_t)buffer + length);
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// DATA register is consistently addressed across all SERCOM modes.
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descriptor_config.destination_address = ((uint32_t)&sercom->SPI.DATA.reg);
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dma_descriptor_create(general_dma_tx.descriptor, &descriptor_config);
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enum status_code status = dma_start_transfer_job(&general_dma_tx);
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if (status != STATUS_OK) {
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return status;
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}
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// Wait for the dma transfer to finish.
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while (general_dma_tx.job_status == STATUS_BUSY) {}
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// Wait for the SPI transfer to complete.
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while (sercom->SPI.INTFLAG.bit.TXC == 0) {}
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// This transmit will cause the RX buffer overflow but we're OK with that.
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// So, read the garbage and clear the overflow flag.
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while (sercom->SPI.INTFLAG.bit.RXC == 1) {
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sercom->SPI.DATA.reg;
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}
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sercom->SPI.STATUS.bit.BUFOVF = 1;
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return general_dma_tx.job_status;
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}
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enum status_code shared_dma_read(Sercom* sercom, uint8_t* buffer, uint32_t length, uint8_t tx) {
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if (general_dma_tx.job_status != STATUS_OK) {
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return general_dma_tx.job_status;
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}
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dma_configure(general_dma_tx.channel_id, sercom_index(sercom) * 2 + 2, false);
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dma_configure(general_dma_rx.channel_id, sercom_index(sercom) * 2 + 1, false);
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// Set up RX first.
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struct dma_descriptor_config descriptor_config;
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dma_descriptor_get_config_defaults(&descriptor_config);
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descriptor_config.beat_size = DMA_BEAT_SIZE_BYTE;
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descriptor_config.src_increment_enable = false;
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descriptor_config.block_transfer_count = length;
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// DATA register is consistently addressed across all SERCOM modes.
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descriptor_config.source_address = ((uint32_t)&sercom->SPI.DATA.reg);
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descriptor_config.destination_address = ((uint32_t)buffer + length);
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dma_descriptor_create(general_dma_rx.descriptor, &descriptor_config);
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// Set up TX to retransmit the same byte over and over.
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dma_descriptor_get_config_defaults(&descriptor_config);
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descriptor_config.beat_size = DMA_BEAT_SIZE_BYTE;
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descriptor_config.src_increment_enable = false;
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descriptor_config.dst_increment_enable = false;
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descriptor_config.block_transfer_count = length;
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descriptor_config.source_address = ((uint32_t)&tx);
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// DATA register is consistently addressed across all SERCOM modes.
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descriptor_config.destination_address = ((uint32_t)&sercom->SPI.DATA.reg);
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dma_descriptor_create(general_dma_tx.descriptor, &descriptor_config);
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// Start the RX job first so we don't miss the first byte. The TX job clocks
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// the output.
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general_dma_rx.transfered_size = 0;
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dma_start_transfer_job(&general_dma_rx);
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general_dma_tx.transfered_size = 0;
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dma_start_transfer_job(&general_dma_tx);
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// Wait for the transfer to finish.
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while (general_dma_rx.job_status == STATUS_BUSY) {}
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while (sercom->SPI.INTFLAG.bit.RXC == 1) {}
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return general_dma_rx.job_status;
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}
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bool allocate_block_counter() {
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// Find a timer to count DMA block completions.
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Tc *t = NULL;
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Tc *tcs[TC_INST_NUM] = TC_INSTS;
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for (uint8_t i = TC_INST_NUM; i > 0; i--) {
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if (tcs[i - 1]->COUNT16.CTRLA.bit.ENABLE == 0) {
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t = tcs[i - 1];
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break;
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}
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}
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if (t == NULL) {
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return false;
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}
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MP_STATE_VM(audiodma_block_counter) = gc_alloc(sizeof(struct tc_module), false);
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if (MP_STATE_VM(audiodma_block_counter) == NULL) {
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return false;
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}
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// Don't bother setting the period. We set it before you playback anything.
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struct tc_config config_tc;
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tc_get_config_defaults(&config_tc);
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config_tc.counter_size = TC_COUNTER_SIZE_16BIT;
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config_tc.clock_prescaler = TC_CLOCK_PRESCALER_DIV1;
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if (tc_init(MP_STATE_VM(audiodma_block_counter), t, &config_tc) != STATUS_OK) {
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return false;
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};
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struct tc_events events_tc;
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events_tc.generate_event_on_overflow = false;
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events_tc.on_event_perform_action = true;
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events_tc.event_action = TC_EVENT_ACTION_INCREMENT_COUNTER;
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tc_enable_events(MP_STATE_VM(audiodma_block_counter), &events_tc);
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// Connect the timer overflow event, which happens at the target frequency,
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// to the DAC conversion trigger.
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MP_STATE_VM(audiodma_block_event) = gc_alloc(sizeof(struct events_resource), false);
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if (MP_STATE_VM(audiodma_block_event) == NULL) {
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return false;
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}
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struct events_config config;
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events_get_config_defaults(&config);
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uint8_t user = EVSYS_ID_USER_TC3_EVU;
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if (t == TC4) {
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user = EVSYS_ID_USER_TC4_EVU;
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} else if (t == TC5) {
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user = EVSYS_ID_USER_TC5_EVU;
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#ifdef TC6
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} else if (t == TC6) {
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user = EVSYS_ID_USER_TC6_EVU;
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#endif
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#ifdef TC7
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} else if (t == TC7) {
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user = EVSYS_ID_USER_TC7_EVU;
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#endif
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}
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config.generator = EVSYS_ID_GEN_DMAC_CH_0;
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config.path = EVENTS_PATH_ASYNCHRONOUS;
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if (events_allocate(MP_STATE_VM(audiodma_block_event), &config) != STATUS_OK ||
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events_attach_user(MP_STATE_VM(audiodma_block_event), user) != STATUS_OK) {
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return false;
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}
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tc_enable(MP_STATE_VM(audiodma_block_counter));
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tc_stop_counter(MP_STATE_VM(audiodma_block_counter));
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return true;
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}
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void switch_audiodma_trigger(uint8_t trigger_dmac_id) {
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dma_configure(audio_dma.channel_id, trigger_dmac_id, true);
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}
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