circuitpython/ports/stm/tools/examples/stm32l4r5zi.csv
Brandon Satrom 48f67d007e feat: add Blues Swan R5 support
complete pin mapping for Feather pins

stubbed out files needed for complilation. still to be modified

0 out all CPY modules in mpconfigboard.mk until we get the build running

add csv for pin generation for STM32L4R5

add F4R5 references in peripherals files

refactored out board files BECAUSE I AM AN IDIOT; add L4 series system clocks file from CubeMX

took a guess at the number of USB endpoint pairs to get the build done

guess was close, but wrong. It is 8

clean up peripheral DEFs

Fixes build error:
```
In file included from ../../py/mpstate.h:33,
                 from ../../py/mpstate.c:27:
../../py/misc.h: In function 'vstr_str':
../../py/misc.h:196:1: sorry, unimplemented: Thumb-1 hard-float VFP ABI
 static inline char *vstr_str(vstr_t *vstr) {
 ^~~~~~
```
Sleuthing steps:
* verify that the feather_stm32f4_express board builds correctly
* put a `#error` at the bottom of the `mpstate.c` file.
* build for the feather and swan boards, with V=2 to capture the build command for that file.
* use a differencing tool to inspect the differences between the two invocations
* inspecting the differences, I saw a missing `-mcpu=cortex-m4` I tested by adding that to the Swan build command. The file built fine (stopping at the hard error, but no other warnings.)

A grep through the sources revealed where this flag was being set for the stm ports.

With this commit, the build gets further, but does not complete. The next exciting episode in this unfolding coding saga is just a commit away!

working build with minimal set of modules for the Blues Swan r5

chore:change header copyright name to Blues Wireless Contributors

USB operational.  Fixed up clocks to be hardwired for LSE no HSE case. (Trying to combine HSE in there made the code much more complex, and I don't have a board to test it out on.)

USART working

adds support for `ENABLE_3V3` and `DISCHARGE_3V3` pins.  I am surprised that pin definitions are quite low-level and don't include default direction and state, so the code currently has to initialize `ENABLE_3V3` pin as output.  The LED takes over a second to discharge, so I wonder if the board startup code is not having the desired affect.

short circuit implementation of backup memory for the STM32L4

all the ports

remove company name from board name to be consistent with the Arduino board definition.

add default pins for I2C, SPI and UART, so that `board.I2C` et al. works as expected.  Confirmed I2C timing.

fix board name

fix incorrect pin definition. add test to allow manual check of each output pin

analog IO

code changes for WebUSB. Doesn't appear to work, will revisit later.

ensure that `sys.platform` is available

checkin missing file

feat: make room for a larger filesystem so the sensor tutorial will fit on the device.

fix:(stm32l4r5zi.csv): merged AF0-7 and AF8-15 into single lines and removed extraneous headers mixed in with the data.

fix(parse_af_csv.py): pin index in the csv is 0 not 1, and AF index made 1 larger

chore(Swan R5): update peripherals pins from `parse_af_csv.py` output

optimize flash sector access
2021-09-28 18:52:02 -07:00

12 KiB

1PortAF0AF1AF2AF3AF4AF5AF6AF7AF8AF9AF10AF11AF12AF13AF14AF15
2PA0-TIM2_CH1TIM5_CH1TIM8_ETR---USART2_CTS_NSSUART4_TX----SAI1_EXTCLKTIM2_ETREVENTOUT
3PA1-TIM2_CH2TIM5_CH2-I2C1_SMBASPI1_SCK-USART2_RTS_DEUART4_RX-OCTOSPIM_P1_DQS---TIM15_CH1NEVENTOUT
4PA2-TIM2_CH3TIM5_CH3----USART2_TXLPUART1_TX-OCTOSPIM_P1_NCS--SAI2_EXTCLKTIM15_CH1EVENTOUT
5PA3-TIM2_CH4TIM5_CH4SAI1_CK1---USART2_RXLPUART1_RX-OCTOSPIM_P1_CLK--SAI1_MCLK_ATIM15_CH2EVENTOUT
6PA4---OCTOSPIM_P1_NCS-SPI1_NSSSPI3_NSSUSART2_CK--DCMI_HSYNC--SAI1_FS_BLPTIM2_OUTEVENTOUT
7PA5-TIM2_CH1TIM2_ETRTIM8_CH1N-SPI1_SCK--------LPTIM2_ETREVENTOUT
8PA6-TIM1_BKINTIM3_CH1TIM8_BKINDCMI_PIXCLKSPI1_MISO-USART3_CTS_NSSLPUART1_CTS-OCTOSPIM_P1_IO3-TIM1_BKINTIM8_BKINTIM16_CH1EVENTOUT
9PA7-TIM1_CH1NTIM3_CH2TIM8_CH1NI2C3_SCLSPI1_MOSI----OCTOSPIM_P1_IO2---TIM17_CH1EVENTOUT
10PA8MCOTIM1_CH1-SAI1_CK2---USART1_CK--OTG_FS_SOF--SAI1_SCK_ALPTIM2_OUTEVENTOUT
11PA9-TIM1_CH2-SPI2_SCK-DCMI_D0-USART1_TX-----SAI1_FS_ATIM15_BKINEVENTOUT
12PA10-TIM1_CH3-SAI1_D1-DCMI_D1-USART1_RX--OTG_FS_ID--SAI1_SD_ATIM17_BKINEVENTOUT
13PA11-TIM1_CH4TIM1_BKIN2--SPI1_MISO-USART1_CTS_NSS-CAN1_RXOTG_FS_DM-TIM1_BKIN2--EVENTOUT
14PA12-TIM1_ETR---SPI1_MOSI-USART1_RTS_DE-CAN1_TXOTG_FS_DP----EVENTOUT
15PA13JTMS/SWDIOIR_OUT--------OTG_FS_NOE--SAI1_SD_B-EVENTOUT
16PA14JTCK/SWCLKLPTIM1_OUT--I2C1_SMBAI2C4_SMBA----OTG_FS_SOF--SAI1_FS_B-EVENTOUT
17PA15JTDITIM2_CH1TIM2_ETRUSART2_RX-SPI1_NSSSPI3_NSSUSART3_RTS_DEUART4_RTS_DETSC_G3_IO1---SAI2_FS_B-EVENTOUT
18PB0-TIM1_CH2NTIM3_CH3TIM8_CH2N-SPI1_NSS-USART3_CK--OCTOSPIM_P1_IO1-COMP1_OUTSAI1_EXTCLK-EVENTOUT
19PB1-TIM1_CH3NTIM3_CH4TIM8_CH3N--DFSDM1_DATIN0USART3_RTS_DELPUART1_RTS_DE-OCTOSPIM_P1_IO0---LPTIM2_IN1EVENTOUT
20PB2RTC_OUTLPTIM1_OUT--I2C3_SMBA-DFSDM1_CKIN0---OCTOSPIM_P1_DQSLCD_B1---EVENTOUT
21PB3JTDO/TRACESWOTIM2_CH2---SPI1_SCKSPI3_SCKUSART1_RTS_DE--OTG_FS_CRS_SYNC--SAI1_SCK_B-EVENTOUT
22PB4NJTRST-TIM3_CH1-I2C3_SDASPI1_MISOSPI3_MISOUSART1_CTS_NSSUART5_RTS_DETSC_G2_IO1DCMI_D12--SAI1_MCLK_BTIM17_BKINEVENTOUT
23PB5-LPTIM1_IN1TIM3_CH2-I2C1_SMBASPI1_MOSISPI3_MOSIUSART1_CKUART5_CTSTSC_G2_IO2DCMI_D10-COMP2_OUTSAI1_SD_BTIM16_BKINEVENTOUT
24PB6-LPTIM1_ETRTIM4_CH1TIM8_BKIN2I2C1_SCLI2C4_SCLDFSDM1_DATIN5USART1_TX-TSC_G2_IO3DCMI_D5-TIM8_BKIN2SAI1_FS_BTIM16_CH1NEVENTOUT
25PB7-LPTIM1_IN2TIM4_CH2TIM8_BKINI2C1_SDAI2C4_SDADFSDM1_CKIN5USART1_RXUART4_CTSTSC_G2_IO4DCMI_VSYNCDSI_TEFMC_NLTIM8_BKINTIM17_CH1NEVENTOUT
26PB8--TIM4_CH3SAI1_CK1I2C1_SCLDFSDM1_CKOUTDFSDM1_DATIN6-SDMMC1_CKINCAN1_RXDCMI_D6LCD_B1SDMMC1_D4SAI1_MCLK_ATIM16_CH1EVENTOUT
27PB9-IR_OUTTIM4_CH4SAI1_D2I2C1_SDASPI2_NSSDFSDM1_CKIN6-SDMMC1_CDIRCAN1_TXDCMI_D7-SDMMC1_D5SAI1_FS_ATIM17_CH1EVENTOUT
28PB10-TIM2_CH3-I2C4_SCLI2C2_SCLSPI2_SCKDFSDM1_DATIN7USART3_TXLPUART1_RXTSC_SYNCOCTOSPIM_P1_CLK-COMP1_OUTSAI1_SCK_A-EVENTOUT
29PB11-TIM2_CH4-I2C4_SDAI2C2_SDA-DFSDM1_CKIN7USART3_RXLPUART1_TX-OCTOSPIM_P1_NCSDSI_TECOMP2_OUT--EVENTOUT
30PB12-TIM1_BKIN-TIM1_BKINI2C2_SMBASPI2_NSSDFSDM1_DATIN1USART3_CKLPUART1_RTS_DETSC_G1_IO1---SAI2_FS_ATIM15_BKINEVENTOUT
31PB13-TIM1_CH1N--I2C2_SCLSPI2_SCKDFSDM1_CKIN1USART3_CTS_NSSLPUART1_CTSTSC_G1_IO2---SAI2_SCK_ATIM15_CH1NEVENTOUT
32PB14-TIM1_CH2N-TIM8_CH2NI2C2_SDASPI2_MISODFSDM1_DATIN2USART3_RTS_DE-TSC_G1_IO3---SAI2_MCLK_ATIM15_CH1EVENTOUT
33PB15RTC_REFINTIM1_CH3N-TIM8_CH3N-SPI2_MOSIDFSDM1_CKIN2--TSC_G1_IO4---SAI2_SD_ATIM15_CH2EVENTOUT
34PC0-LPTIM1_IN1--I2C3_SCL-DFSDM1_DATIN4-LPUART1_RX----SAI2_FS_ALPTIM2_IN1EVENTOUT
35PC1TRACED0LPTIM1_OUT-SPI2_MOSII2C3_SDA-DFSDM1_CKIN4-LPUART1_TX-OCTOSPIM_P1_IO4--SAI1_SD_A-EVENTOUT
36PC2-LPTIM1_IN2---SPI2_MISODFSDM1_CKOUT---OCTOSPIM_P1_IO5----EVENTOUT
37PC3-LPTIM1_ETR-SAI1_D1-SPI2_MOSI----OCTOSPIM_P1_IO6--SAI1_SD_ALPTIM2_ETREVENTOUT
38PC4-------USART3_TX--OCTOSPIM_P1_IO7----EVENTOUT
39PC5---SAI1_D3---USART3_RX-------EVENTOUT
40PC6--TIM3_CH1TIM8_CH1--DFSDM1_CKIN3-SDMMC1_D0DIRTSC_G4_IO1DCMI_D0LCD_R0SDMMC1_D6SAI2_MCLK_A-EVENTOUT
41PC7--TIM3_CH2TIM8_CH2--DFSDM1_DATIN3-SDMMC1_D123DIRTSC_G4_IO2DCMI_D1LCD_R1SDMMC1_D7SAI2_MCLK_B-EVENTOUT
42PC8--TIM3_CH3TIM8_CH3-----TSC_G4_IO3DCMI_D2-SDMMC1_D0--EVENTOUT
43PC9TRACED0TIM8_BKIN2TIM3_CH4TIM8_CH4DCMI_D3-I2C3_SDA--TSC_G4_IO4OTG_FS_NOE-SDMMC1_D1SAI2_EXTCLKTIM8_BKIN2EVENTOUT
44PC10TRACED1-----SPI3_SCKUSART3_TXUART4_TXTSC_G3_IO2DCMI_D8-SDMMC1_D2SAI2_SCK_B-EVENTOUT
45PC11----DCMI_D2OCTOSPIM_P1_NCSSPI3_MISOUSART3_RXUART4_RXTSC_G3_IO3DCMI_D4-SDMMC1_D3SAI2_MCLK_B-EVENTOUT
46PC12TRACED3-----SPI3_MOSIUSART3_CKUART5_TXTSC_G3_IO4DCMI_D9-SDMMC1_CKSAI2_SD_B-EVENTOUT
47PC13---------------EVENTOUT
48PC14---------------EVENTOUT
49PC15---------------EVENTOUT
50PD0-----SPI2_NSSDFSDM1_DATIN7--CAN1_RX-LCD_B4FMC_D2--EVENTOUT
51PD1-----SPI2_SCKDFSDM1_CKIN7--CAN1_TX-LCD_B5FMC_D3--EVENTOUT
52PD2TRACED2-TIM3_ETR----USART3_RTS_DEUART5_RXTSC_SYNCDCMI_D11-SDMMC1_CMD--EVENTOUT
53PD3---SPI2_SCKDCMI_D5SPI2_MISODFSDM1_DATIN0USART2_CTS_NSS--OCTOSPIM_P2_NCSLCD_CLKFMC_CLK--EVENTOUT
54PD4-----SPI2_MOSIDFSDM1_CKIN0USART2_RTS_DE--OCTOSPIM_P1_IO4-FMC_NOE--EVENTOUT
55PD5-------USART2_TX--OCTOSPIM_P1_IO5-FMC_NWE--EVENTOUT
56PD6---SAI1_D1DCMI_D10SPI3_MOSIDFSDM1_DATIN1USART2_RX--OCTOSPIM_P1_IO6LCD_DEFMC_NWAITSAI1_SD_A-EVENTOUT
57PD7------DFSDM1_CKIN1USART2_CK--OCTOSPIM_P1_IO7-FMC_NCE/FMC_NE1--EVENTOUT
58PD8-------USART3_TX--DCMI_HSYNCLCD_R3FMC_D13--EVENTOUT
59PD9-------USART3_RX--DCMI_PIXCLKLCD_R4FMC_D14SAI2_MCLK_A-EVENTOUT
60PD10-------USART3_CK-TSC_G6_IO1-LCD_R5FMC_D15SAI2_SCK_A-EVENTOUT
61PD11----I2C4_SMBA--USART3_CTS_NSS-TSC_G6_IO2-LCD_R6FMC_A16SAI2_SD_ALPTIM2_ETREVENTOUT
62PD12--TIM4_CH1-I2C4_SCL--USART3_RTS_DE-TSC_G6_IO3-LCD_R7FMC_A17SAI2_FS_ALPTIM2_IN1EVENTOUT
63PD13--TIM4_CH2-I2C4_SDA----TSC_G6_IO4--FMC_A18-LPTIM2_OUTEVENTOUT
64PD14--TIM4_CH3--------LCD_B2FMC_D0--EVENTOUT
65PD15--TIM4_CH4--------LCD_B3FMC_D1--EVENTOUT
66PE0--TIM4_ETR-------DCMI_D2LCD_HSYNCFMC_NBL0-TIM16_CH1EVENTOUT
67PE1----------DCMI_D3LCD_VSYNCFMC_NBL1-TIM17_CH1EVENTOUT
68PE2TRACECK-TIM3_ETRSAI1_CK1-----TSC_G7_IO1-LCD_R0FMC_A23SAI1_MCLK_A-EVENTOUT
69PE3TRACED0-TIM3_CH1OCTOSPIM_P1_DQS-----TSC_G7_IO2-LCD_R1FMC_A19SAI1_SD_B-EVENTOUT
70PE4TRACED1-TIM3_CH2SAI1_D2--DFSDM1_DATIN3--TSC_G7_IO3DCMI_D4LCD_B0FMC_A20SAI1_FS_A-EVENTOUT
71PE5TRACED2-TIM3_CH3SAI1_CK2--DFSDM1_CKIN3--TSC_G7_IO4DCMI_D6LCD_G0FMC_A21SAI1_SCK_A-EVENTOUT
72PE6TRACED3-TIM3_CH4SAI1_D1------DCMI_D7LCD_G1FMC_A22SAI1_SD_A-EVENTOUT
73PE7-TIM1_ETR----DFSDM1_DATIN2----LCD_B6FMC_D4SAI1_SD_B-EVENTOUT
74PE8-TIM1_CH1N----DFSDM1_CKIN2----LCD_B7FMC_D5SAI1_SCK_B-EVENTOUT
75PE9-TIM1_CH1----DFSDM1_CKOUT----LCD_G2FMC_D6SAI1_FS_B-EVENTOUT
76PE10-TIM1_CH2N----DFSDM1_DATIN4--TSC_G5_IO1OCTOSPIM_P1_CLKLCD_G3FMC_D7SAI1_MCLK_B-EVENTOUT
77PE11-TIM1_CH2----DFSDM1_CKIN4--TSC_G5_IO2OCTOSPIM_P1_NCSLCD_G4FMC_D8--EVENTOUT
78PE12-TIM1_CH3N---SPI1_NSSDFSDM1_DATIN5--TSC_G5_IO3OCTOSPIM_1_IO0LCD_G5FMC_D9--EVENTOUT
79PE13-TIM1_CH3---SPI1_SCKDFSDM1_CKIN5--TSC_G5_IO4OCTOSPIM_P1_IO1LCD_G6FMC_D10--EVENTOUT
80PE14-TIM1_CH4TIM1_BKIN2TIM1_BKIN2-SPI1_MISO----OCTOSPIM_P1_IO2LCD_G7FMC_D11--EVENTOUT
81PE15-TIM1_BKIN-TIM1_BKIN-SPI1_MOSI----OCTOSPIM_P1_IO3LCD_R2FMC_D12--EVENTOUT
82PF0----I2C2_SDAOCTOSPIM_P2_IO0------FMC_A0--EVENTOUT
83PF1----I2C2_SCLOCTOSPIM_P2_IO1------FMC_A1--EVENTOUT
84PF2----I2C2_SMBAOCTOSPIM_P2_IO2------FMC_A2--EVENTOUT
85PF3-----OCTOSPIM_P2_IO3------FMC_A3--EVENTOUT
86PF4-----OCTOSPIM_P2_CLK------FMC_A4--EVENTOUT
87PF5------------FMC_A5--EVENTOUT
88PF6-TIM5_ETRTIM5_CH1-------OCTOSPIM_P1_IO3--SAI1_SD_B-EVENTOUT
89PF7--TIM5_CH2-------OCTOSPIM_P1_IO2--SAI1_MCLK_B-EVENTOUT
90PF8--TIM5_CH3-------OCTOSPIM_P1_IO0--SAI1_SCK_B-EVENTOUT
91PF9--TIM5_CH4-------OCTOSPIM_P1_IO1--SAI1_FS_BTIM15_CH1EVENTOUT
92PF10---OCTOSPIM_P1_CLK--DFSDM1_CKOUT---DCMI_D11--SAI1_D3TIM15_CH2EVENTOUT
93PF11---------LCD_DEDCMI_D12DSI_TE---EVENTOUT
94PF12-----OCTOSPIM_P2_DQS-----LCD_B0FMC_A6--EVENTOUT
95PF13----I2C4_SMBA-DFSDM1_DATIN6----LCD_B1FMC_A7--EVENTOUT
96PF14----I2C4_SCL-DFSDM1_CKIN6--TSC_G8_IO1-LCD_G0FMC_A8--EVENTOUT
97PF15----I2C4_SDA----TSC_G8_IO2-LCD_G1FMC_A9--EVENTOUT
98PG0-----OCTOSPIM_P2_IO4---TSC_G8_IO3--FMC_A10--EVENTOUT
99PG1-----OCTOSPIM_P2_IO5---TSC_G8_IO4--FMC_A11--EVENTOUT
100PG2-----SPI1_SCK------FMC_A12SAI2_SCK_B-EVENTOUT
101PG3-----SPI1_MISO------FMC_A13SAI2_FS_B-EVENTOUT
102PG4-----SPI1_MOSI------FMC_A14SAI2_MCLK_B-EVENTOUT
103PG5-----SPI1_NSS--LPUART1_CTS---FMC_A15SAI2_SD_B-EVENTOUT
104PG6---OCTOSPIM_P1_DQSI2C3_SMBA---LPUART1_RTS_DELCD_R1-DSI_TE---EVENTOUT
105PG7---SAI1_CK1I2C3_SCLOCTOSPIM_P2_DQSDFSDM1_CKOUT-LPUART1_TX---FMC_INTSAI1_MCLK_A-EVENTOUT
106PG8----I2C3_SDA---LPUART1_RX------EVENTOUT
107PG9-----OCTOSPIM_P2_IO6SPI3_SCKUSART1_TX----FMC_NCE/FMC_NE2SAI2_SCK_ATIM15_CH1NEVENTOUT
108PG10-LPTIM1_IN1---OCTOSPIM_P2_IO7SPI3_MISOUSART1_RX----FMC_NE3SAI2_FS_ATIM15_CH1EVENTOUT
109PG11-LPTIM1_IN2-OCTOSPIM_P1_IO5--SPI3_MOSIUSART1_CTS_NSS-----SAI2_MCLK_ATIM15_CH2EVENTOUT
110PG12-LPTIM1_ETR---OCTOSPIM_P2_NCSSPI3_NSSUSART1_RTS_DE----FMC_NE4SAI2_SD_A-EVENTOUT
111PG13----I2C1_SDA--USART1_CK---LCD_R0FMC_A24--EVENTOUT
112PG14----I2C1_SCL------LCD_R1FMC_A25--EVENTOUT
113PG15-LPTIM1_OUT--I2C1_SMBAOCTOSPIM_P2_DQS----DCMI_D13----EVENTOUT
114PH0---------------EVENTOUT
115PH1---------------EVENTOUT
116PH2---OCTOSPIM_P1_IO4-----------EVENTOUT
117PH3---------------EVENTOUT
118PH4----I2C2_SCLOCTOSPIM_P2_DQS---------EVENTOUT
119PH5----I2C2_SDA-----DCMI_PIXCLK----EVENTOUT
120PH6----I2C2_SMBAOCTOSPIM_P2_CLK----DCMI_D8----EVENTOUT
121PH7----I2C3_SCL-----DCMI_D9----EVENTOUT
122PH8----I2C3_SDAOCTOSPIM_P2_IO3----DCMI_HSYNC----EVENTOUT
123PH9----I2C3_SMBAOCTOSPIM_P2_IO4----DCMI_D0----EVENTOUT
124PH10--TIM5_CH1--OCTOSPIM_P2_IO5----DCMI_D1----EVENTOUT
125PH11--TIM5_CH2--OCTOSPIM_P2_IO6----DCMI_D2----EVENTOUT
126PH12--TIM5_CH3--OCTOSPIM_P2_IO7----DCMI_D3----EVENTOUT
127PH13---TIM8_CH1N-----CAN1_TX-----EVENTOUT
128PH14---TIM8_CH2N------DCMI_D4----EVENTOUT
129PH15---TIM8_CH3N-OCTOSPIM_P2_IO6----DCMI_D11----EVENTOUT
130PI0--TIM5_CH4OCTOSPIM_P1_IO5-SPI2_NSS----DCMI_D13----EVENTOUT
131PI1-----SPI2_SCK----DCMI_D8----EVENTOUT
132PI2---TIM8_CH4-SPI2_MISO----DCMI_D9----EVENTOUT
133PI3---TIM8_ETR-SPI2_MOSI----DCMI_D10----EVENTOUT
134PI4---TIM8_BKIN------DCMI_D5----EVENTOUT
135PI5---TIM8_CH1-OCTOSPIM_P2_NCS----DCMI_VSYNC----EVENTOUT
136PI6---TIM8_CH2-OCTOSPIM_P2_CLK----DCMI_D6----EVENTOUT
137PI7---TIM8_CH3------DCMI_D7----EVENTOUT
138PI8-----OCTOSPIM_P2_NCS----DCMI_D12----EVENTOUT
139PI9-----OCTOSPIM_P2_IO2---CAN1_RX-----EVENTOUT
140PI10-----OCTOSPIM_P2_IO1---------EVENTOUT
141PI11-----OCTOSPIM_P2_IO0---------EVENTOUT