312444bbd2
Also, fixed pin mappings for rev B Metro M4: swap PA12 and PA13 on SPI 2x3 header swap A3 and A5 Comment out all frozen modules in CPX again to make room while waiting for SPI flash.
132 lines
4.1 KiB
C
132 lines
4.1 KiB
C
/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017 Dan Halbert for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hpl/gclk/hpl_gclk_base.h"
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#include "hri/hri_mclk_d51.h"
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// The clock initializer values are rather random, so we need to put them in
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// tables for lookup. We can't compute them.
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static const uint8_t SERCOMx_GCLK_ID_CORE[] = {
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SERCOM0_GCLK_ID_CORE,
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SERCOM1_GCLK_ID_CORE,
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SERCOM2_GCLK_ID_CORE,
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SERCOM3_GCLK_ID_CORE,
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SERCOM4_GCLK_ID_CORE,
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SERCOM5_GCLK_ID_CORE,
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#ifdef SERCOM6
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SERCOM6_GCLK_ID_CORE,
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#endif
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#ifdef SERCOM7
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SERCOM7_GCLK_ID_CORE,
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#endif
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};
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static const uint8_t SERCOMx_GCLK_ID_SLOW[] = {
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SERCOM0_GCLK_ID_SLOW,
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SERCOM1_GCLK_ID_SLOW,
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SERCOM2_GCLK_ID_SLOW,
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SERCOM3_GCLK_ID_SLOW,
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SERCOM4_GCLK_ID_SLOW,
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SERCOM5_GCLK_ID_SLOW,
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#ifdef SERCOM6
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SERCOM6_GCLK_ID_SLOW,
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#endif
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#ifdef SERCOM7
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SERCOM7_GCLK_ID_SLOW,
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#endif
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};
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// Clock initialization as done in Atmel START.
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void samd_peripheral_sercom_clock_init(Sercom* sercom, uint8_t sercom_index) {
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hri_gclk_write_PCHCTRL_reg(GCLK,
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SERCOMx_GCLK_ID_CORE[sercom_index],
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GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos));
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hri_gclk_write_PCHCTRL_reg(GCLK,
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SERCOMx_GCLK_ID_SLOW[sercom_index],
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GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos));
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// hri_mclk_set_APBAMASK_SERCOMx_bit is an inline, so let's use a switch, not a table.
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switch (sercom_index) {
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case 0:
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hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK);
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break;
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case 1:
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hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK);
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break;
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case 2:
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hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
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break;
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case 3:
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hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK);
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break;
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case 4:
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hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);
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break;
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case 5:
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hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);
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break;
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#ifdef SERCOM6
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case 6:
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hri_mclk_set_APBDMASK_SERCOM6_bit(MCLK);
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break;
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#endif
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#ifdef SERCOM7
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case 7:
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hri_mclk_set_APBDMASK_SERCOM7_bit(MCLK);
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break;
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#endif
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}
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}
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// Figure out the DOPO value given the chosen clock pad and mosi pad.
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// Return an out-of-range value (255) if the combination is not permitted
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// The ASF4 config files list this, but the SAMD51 datasheet
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// says 0x1 and 0x3 are reserved, so don't allow pad 3 SCK.
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// Transmit Data Pinout
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// <0x0=>PAD[0,1]_DO_SCK
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// <0x1=>PAD[2,3]_DO_SCK [RESERVED]
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// <0x2=>PAD[3,1]_DO_SCK
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// <0x3=>PAD[0,3]_DO_SCK [RESERVED]
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uint8_t samd_peripheral_get_spi_dopo(uint8_t clock_pad, uint8_t mosi_pad) {
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if (clock_pad != 1) {
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return 255;
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}
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if (mosi_pad == 0) {
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return 0x1;
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}
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if (mosi_pad == 3) {
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return 0x2;
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}
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return 255;
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}
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bool samd_peripheral_valid_spi_clock_pad(uint8_t clock_pad) {
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return clock_pad == 1;
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}
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