circuitpython/stm32l152_af.csv at 17f2783e4aa4534823e2dc33e77389ad498f2d24

yn386 427d72667f stm32: Add support for STM32L1 MCUs.

This change adds STM32L1 support to the STM32 port.

2022-09-25 23:56:41 +10:00

5.6 KiB

Raw Blame History

1	Port		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF15
2			SYS_AF	TIM2	TIM3/TIM4/TIM5	TIM9/TIM10/TIM11	I2C1/I2C2	SPI1/SPI2	SPI3	USART1/USART2/USART3	UART4/UART5		ADC
3	PortA	PA0		TIM2_CH1_ETR	TIM5_CH1					USART2_CTS		EVENTOUT	ADC1_IN0
4	PortA	PA1		TIM2_CH2	TIM5_CH2					USART2_RTS		EVENTOUT	ADC1_IN1
5	PortA	PA2		TIM2_CH3	TIM5_CH3	TIM9_CH1				USART2_TX		EVENTOUT	ADC1_IN2
6	PortA	PA3		TIM2_CH4	TIM5_CH4	TIM9_CH2				USART2_RX		EVENTOUT	ADC1_IN3
7	PortA	PA4						SPI1_NSS	SPI3_NSS/I2S3_WS	USART2_CK		EVENTOUT	ADC1_IN4
8	PortA	PA5		TIM2_CH1_ETR				SPI1_SCK				EVENTOUT	ADC1_IN5
9	PortA	PA6			TIM3_CH1	TIM10_CH1		SPI1_MISO				EVENTOUT	ADC1_IN6
10	PortA	PA7			TIM3_CH2	TIM11_CH1		SPI1_MOSI				EVENTOUT	ADC1_IN7
11	PortA	PA8	MCO							USART1_CK		EVENTOUT
12	PortA	PA9								USART1_TX		EVENTOUT
13	PortA	PA10								USART1_RX		EVENTOUT
14	PortA	PA11						SPI1_MISO		USART1_CTS		EVENTOUT
15	PortA	PA12						SPI1_MOSI		USART1_RTS		EVENTOUT
16	PortA	PA13	JTMS/SWDIO									EVENTOUT
17	PortA	PA14	JTCK/SWCLK									EVENTOUT
18	PortA	PA15	JTDI	TIM2_CH1_ETR				SPI1_NSS	SPI3_NSS/I2S3_WS			EVENTOUT
19	PortB	PB0			TIM3_CH3							EVENTOUT	ADC1_IN8
20	PortB	PB1			TIM3_CH4							EVENTOUT	ADC1_IN9
21	PortB	PB2	BOOT1									EVENTOUT
22	PortB	PB3	JTDO	TIM2_CH2				SPI1_SCK	SPI3_SCK/I2S3_CK			EVENTOUT
23	PortB	PB4	NJTRST		TIM3_CH1			SPI1_MISO	SPI3_MISO			EVENTOUT
24	PortB	PB5			TIM3_CH2		I2C1_SMBA	SPI1_MOSI	SPI3_MOSI/I2S3_SD			EVENTOUT
25	PortB	PB6			TIM4_CH1		I2C1_SCL			USART1_TX		EVENTOUT
26	PortB	PB7			TIM4_CH2		I2C1_SDA			USART1_RX		EVENTOUT
27	PortB	PB8			TIM4_CH3	TIM10_CH1	I2C1_SCL					EVENTOUT
28	PortB	PB9			TIM4_CH4	TIM11_CH1	I2C1_SDA					EVENTOUT
29	PortB	PB10		TIM2_CH3			I2C2_SCL			USART3_TX		EVENTOUT
30	PortB	PB11		TIM2_CH4			I2C2_SDA			USART3_RX		EVENTOUT
31	PortB	PB12				TIM10_CH1	I2C2_SMBA	SPI2_NSS/I2S2_WS		USART3_CK		EVENTOUT	ADC1_IN18
32	PortB	PB13				TIM9_CH1		SPI2_SCK/I2S2_CK		USART3_CTS		EVENTOUT	ADC1_IN19
33	PortB	PB14				TIM9_CH2		SPI2_MISO		USART3_RTS		EVENTOUT	ADC1_IN20
34	PortB	PB15				TIM11_CH1		SPI2_MOSI/I2S2_SD				EVENTOUT	ADC1_IN21
35	PortC	PC0										EVENTOUT	ADC1_IN10
36	PortC	PC1										EVENTOUT	ADC1_IN11
37	PortC	PC2										EVENTOUT	ADC1_IN12
38	PortC	PC3										EVENTOUT	ADC1_IN13
39	PortC	PC4										EVENTOUT	ADC1_IN14
40	PortC	PC5										EVENTOUT	ADC1_IN15
41	PortC	PC6			TIM3_CH1			I2S2_MCK				EVENTOUT
42	PortC	PC7			TIM3_CH2				I2S3_MCK			EVENTOUT
43	PortC	PC8			TIM3_CH3							EVENTOUT
44	PortC	PC9			TIM3_CH4							EVENTOUT
45	PortC	PC10							SPI3_SCK/I2S3_CK	USART3_TX	UART4_TX	EVENTOUT
46	PortC	PC11							SPI3_MISO	USART3_RX	UART4_RX	EVENTOUT
47	PortC	PC12							SPI3_MOSI/I2S3_SD	USART3_CK	UART5_TX	EVENTOUT
48	PortC	PC13										EVENTOUT
49	PortC	PC14										EVENTOUT
50	PortC	PC15										EVENTOUT
51	PortD	PD0				TIM9_CH1		SPI2_NSS/I2S2_WS				EVENTOUT
52	PortD	PD1						SPI2_SCK/I2S2_CK				EVENTOUT
53	PortD	PD2			TIM3_ETR						UART5_RX	EVENTOUT
54	PortD	PD3						SPI2_MISO		USART2_CTS		EVENTOUT
55	PortD	PD4						SPI2_MOSI/I2S2_SD		USART2_RTS		EVENTOUT
56	PortD	PD5								USART2_TX		EVENTOUT
57	PortD	PD6								USART2_RX		EVENTOUT
58	PortD	PD7				TIM9_CH2				USART2_CK		EVENTOUT
59	PortD	PD8								USART3_TX		EVENTOUT
60	PortD	PD9								USART3_RX		EVENTOUT
61	PortD	PD10								USART3_CK		EVENTOUT
62	PortD	PD11								USART3_CTS		EVENTOUT
63	PortD	PD12			TIM4_CH1					USART3_RTS		EVENTOUT
64	PortD	PD13			TIM4_CH2							EVENTOUT
65	PortD	PD14			TIM4_CH3							EVENTOUT
66	PortD	PD15			TIM4_CH4							EVENTOUT
67	PortE	PE0			TIM4_ETR	TIM10_CH1						EVENTOUT
68	PortE	PE1				TIM11_CH1						EVENTOUT
69	PortE	PE2	TRACECK		TIM3_ETR							EVENTOUT
70	PortE	PE3	TRACED0		TIM3_CH1							EVENTOUT
71	PortE	PE4	TRACED1		TIM3_CH2							EVENTOUT
72	PortE	PE5	TRACED2			TIM9_CH1						EVENTOUT
73	PortE	PE6	TRACED3			TIM9_CH2						EVENTOUT
74	PortE	PE7										EVENTOUT
75	PortE	PE8										EVENTOUT
76	PortE	PE9		TIM2_CH1_ETR								EVENTOUT
77	PortE	PE10		TIM2_CH2								EVENTOUT
78	PortE	PE11		TIM2_CH3								EVENTOUT
79	PortE	PE12		TIM2_CH4				SPI1_NSS				EVENTOUT
80	PortE	PE13						SPI1_SCK				EVENTOUT
81	PortE	PE14						SPI1_MISO				EVENTOUT
82	PortE	PE15						SPI1_MOSI				EVENTOUT
83	PortF	PF0										EVENTOUT
84	PortF	PF1										EVENTOUT
85	PortF	PF2										EVENTOUT
86	PortF	PF3										EVENTOUT
87	PortF	PF4										EVENTOUT
88	PortF	PF5										EVENTOUT
89	PortF	PF6			TIM5_ETR							EVENTOUT
90	PortF	PF7			TIM5_CH2							EVENTOUT
91	PortF	PF8			TIM5_CH3							EVENTOUT
92	PortF	PF9			TIM5_CH4							EVENTOUT
93	PortF	PF10										EVENTOUT
94	PortF	PF11										EVENTOUT
95	PortF	PF12										EVENTOUT
96	PortF	PF13										EVENTOUT
97	PortF	PF14										EVENTOUT
98	PortF	PF15										EVENTOUT
99	PortG	PG0										EVENTOUT
100	PortG	PG1										EVENTOUT
101	PortG	PG2										EVENTOUT
102	PortG	PG3										EVENTOUT
103	PortG	PG4										EVENTOUT
104	PortG	PG5										EVENTOUT
105	PortG	PG6										EVENTOUT
106	PortG	PG7										EVENTOUT
107	PortG	PG8										EVENTOUT
108	PortG	PG9										EVENTOUT
109	PortG	PG10										EVENTOUT
110	PortG	PG11										EVENTOUT
111	PortG	PG12										EVENTOUT
112	PortG	PG13										EVENTOUT
113	PortG	PG14										EVENTOUT
114	PortG	PG15										EVENTOUT
115	PortH	PH0
116	PortH	PH1
117	PortH	PH2

5.6 KiB Raw Blame History

5.6 KiB

Raw Blame History