circuitpython/mk20dx256_af.csv at 0d3de686692e25c85d322c626921bc982a79581d

Damien George 01dd7804b8 ports: Make new ports/ sub-directory and move all ports there.

This is to keep the top-level directory clean, to make it clear what is
core and what is a port, and to allow the repository to grow with new ports
in a sustainable way.

2017-09-06 13:40:51 +10:00

4.5 KiB

Raw Blame History

1	Pin	Name	Default	ALT0	ALT1	ALT2	ALT3	ALT4	ALT5	ALT6	ALT7	EzPort
2	1	PTE0	ADC1_SE4a	ADC1_SE4a	PTE0	SPI1_PCS1	UART1_TX			I2C1_SDA	RTC_CLKOUT
3	2	PTE1/LLWU_P0	ADC1_SE5a	ADC1_SE5a	PTE1/LLWU_P0	SPI1_SOUT	UART1_RX			I2C1_SCL	SPI1_SIN
4	3	VDD	VDD	VDD
5	4	VSS	VSS	VSS
6	5	USB0_DP	USB0_DP	USB0_DP
7	6	USB0_DM	USB0_DM	USB0_DM
8	7	VOUT33	VOUT33	VOUT33
9	8	VREGIN	VREGIN	VREGIN
10	9	PGA0_DP/ADC0_DP0/ADC1_DP3	PGA0_DP/ADC0_DP0/ADC1_DP3	PGA0_DP/ADC0_DP0/ADC1_DP3	PTZ0
11	10	PGA0_DM/ADC0_DM0/ADC1_DM3	PGA0_DM/ADC0_DM0/ADC1_DM3	PGA0_DM/ADC0_DM0/ADC1_DM3	PTZ1
12	11	PGA1_DP/ADC1_DP0/ADC0_DP3	PGA1_DP/ADC1_DP0/ADC0_DP3	PGA1_DP/ADC1_DP0/ADC0_DP3	PTZ2
13	12	PGA1_DM/ADC1_DM0/ADC0_DM3	PGA1_DM/ADC1_DM0/ADC0_DM3	PGA1_DM/ADC1_DM0/ADC0_DM3	PTZ3
14	13	VDDA	VDDA	VDDA
15	14	VREFH	VREFH	VREFH
16	15	VREFL	VREFL	VREFL
17	16	VSSA	VSSA	VSSA
18	17	VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18	VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18	VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18	PTZ4
19	18	DAC0_OUT/CMP1_IN3/ADC0_SE23	DAC0_OUT/CMP1_IN3/ADC0_SE23	DAC0_OUT/CMP1_IN3/ADC0_SE23	PTZ5
20	19	XTAL32	XTAL32	XTAL32
21	20	EXTAL32	EXTAL32	EXTAL32
22	21	VBAT	VBAT	VBAT
23	22	PTA0	JTAG_TCLK/SWD_CLK/EZP_CLK	TSI0_CH1	PTA0	UART0_CTS_b/UART0_COL_b	FTM0_CH5				JTAG_TCLK/SWD_CLK	EZP_CLK
24	23	PTA1	JTAG_TDI/EZP_DI	TSI0_CH2	PTA1	UART0_RX	FTM0_CH6				JTAG_TDI	EZP_DI
25	24	PTA2	JTAG_TDO/TRACE_SWO/EZP_DO	TSI0_CH3	PTA2	UART0_TX	FTM0_CH7				JTAG_TDO/TRACE_SWO	EZP_DO
26	25	PTA3	JTAG_TMS/SWD_DIO	TSI0_CH4	PTA3	UART0_RTS_b	FTM0_CH0				JTAG_TMS/SWD_DIO
27	26	PTA4/LLWU_P3	NMI_b/EZP_CS_b	TSI0_CH5	PTA4/LLWU_P3		FTM0_CH1			NMI_b	EZP_CS_b
28	27	PTA5	DISABLED		PTA5	USB_CLKIN	FTM0_CH2		CMP2_OUT	I2S0_TX_BCLK	JTAG_TRST_b
29	28	PTA12	CMP2_IN0	CMP2_IN0	PTA12	CAN0_TX	FTM1_CH0			I2S0_TXD0	FTM1_QD_PHA
30	29	PTA13/LLWU_P4	CMP2_IN1	CMP2_IN1	PTA13/LLWU_P4	CAN0_RX	FTM1_CH1			I2S0_TX_FS	FTM1_QD_PHB
31	30	VDD	VDD	VDD
32	31	VSS	VSS	VSS
33	32	PTA18	EXTAL0	EXTAL0	PTA18		FTM0_FLT2	FTM_CLKIN0
34	33	PTA19	XTAL0	XTAL0	PTA19		FTM1_FLT0	FTM_CLKIN1		LPTMR0_ALT1
35	34	RESET_b	RESET_b	RESET_b
36	35	PTB0/LLWU_P5	ADC0_SE8/ADC1_SE8/TSI0_CH0	ADC0_SE8/ADC1_SE8/TSI0_CH0	PTB0/LLWU_P5	I2C0_SCL	FTM1_CH0			FTM1_QD_PHA
37	36	PTB1	ADC0_SE9/ADC1_SE9/TSI0_CH6	ADC0_SE9/ADC1_SE9/TSI0_CH6	PTB1	I2C0_SDA	FTM1_CH1			FTM1_QD_PHB
38	37	PTB2	ADC0_SE12/TSI0_CH7	ADC0_SE12/TSI0_CH7	PTB2	I2C0_SCL	UART0_RTS_b			FTM0_FLT3
39	38	PTB3	ADC0_SE13/TSI0_CH8	ADC0_SE13/TSI0_CH8	PTB3	I2C0_SDA	UART0_CTS_b/UART0_COL_b			FTM0_FLT0
40	39	PTB16	TSI0_CH9	TSI0_CH9	PTB16	SPI1_SOUT	UART0_RX		FB_AD17	EWM_IN
41	40	PTB17	TSI0_CH10	TSI0_CH10	PTB17	SPI1_SIN	UART0_TX		FB_AD16	EWM_OUT_b
42	41	PTB18	TSI0_CH11	TSI0_CH11	PTB18	CAN0_TX	FTM2_CH0	I2S0_TX_BCLK	FB_AD15	FTM2_QD_PHA
43	42	PTB19	TSI0_CH12	TSI0_CH12	PTB19	CAN0_RX	FTM2_CH1	I2S0_TX_FS	FB_OE_b	FTM2_QD_PHB
44	43	PTC0	ADC0_SE14/TSI0_CH13	ADC0_SE14/TSI0_CH13	PTC0	SPI0_PCS4	PDB0_EXTRG		FB_AD14	I2S0_TXD1
45	44	PTC1/LLWU_P6	ADC0_SE15/TSI0_CH14	ADC0_SE15/TSI0_CH14	PTC1/LLWU_P6	SPI0_PCS3	UART1_RTS_b	FTM0_CH0	FB_AD13	I2S0_TXD0
46	45	PTC2	ADC0_SE4b/CMP1_IN0/TSI0_CH15	ADC0_SE4b/CMP1_IN0/TSI0_CH15	PTC2	SPI0_PCS2	UART1_CTS_b	FTM0_CH1	FB_AD12	I2S0_TX_FS
47	46	PTC3/LLWU_P7	CMP1_IN1	CMP1_IN1	PTC3/LLWU_P7	SPI0_PCS1	UART1_RX	FTM0_CH2	CLKOUT	I2S0_TX_BCLK
48	47	VSS	VSS	VSS
49	48	VDD	VDD	VDD
50	49	PTC4/LLWU_P8	DISABLED		PTC4/LLWU_P8	SPI0_PCS0	UART1_TX	FTM0_CH3	FB_AD11	CMP1_OUT
51	50	PTC5/LLWU_P9	DISABLED		PTC5/LLWU_P9	SPI0_SCK	LPTMR0_ALT2	I2S0_RXD0	FB_AD10	CMP0_OUT
52	51	PTC6/LLWU_P10	CMP0_IN0	CMP0_IN0	PTC6/LLWU_P10	SPI0_SOUT	PDB0_EXTRG	I2S0_RX_BCLK	FB_AD9	I2S0_MCLK
53	52	PTC7	CMP0_IN1	CMP0_IN1	PTC7	SPI0_SIN	USB_SOF_OUT	I2S0_RX_FS	FB_AD8
54	53	PTC8	ADC1_SE4b/CMP0_IN2	ADC1_SE4b/CMP0_IN2	PTC8			I2S0_MCLK	FB_AD7
55	54	PTC9	ADC1_SE5b/CMP0_IN3	ADC1_SE5b/CMP0_IN3	PTC9			I2S0_RX_BCLK	FB_AD6	FTM2_FLT0
56	55	PTC10	ADC1_SE6b	ADC1_SE6b	PTC10	I2C1_SCL		I2S0_RX_FS	FB_AD5
57	56	PTC11/LLWU_P11	ADC1_SE7b	ADC1_SE7b	PTC11/LLWU_P11	I2C1_SDA		I2S0_RXD1	FB_RW_b
58	57	PTD0/LLWU_P12	DISABLED		PTD0/LLWU_P12	SPI0_PCS0	UART2_RTS_b		FB_ALE/FB_CS1_b/FB_TS_b
59	58	PTD1	ADC0_SE5b	ADC0_SE5b	PTD1	SPI0_SCK	UART2_CTS_b		FB_CS0_b
60	59	PTD2/LLWU_P13	DISABLED		PTD2/LLWU_P13	SPI0_SOUT	UART2_RX		FB_AD4
61	60	PTD3	DISABLED		PTD3	SPI0_SIN	UART2_TX		FB_AD3
62	61	PTD4/LLWU_P14	DISABLED		PTD4/LLWU_P14	SPI0_PCS1	UART0_RTS_b	FTM0_CH4	FB_AD2	EWM_IN
63	62	PTD5	ADC0_SE6b	ADC0_SE6b	PTD5	SPI0_PCS2	UART0_CTS_b/UART0_COL_b	FTM0_CH5	FB_AD1	EWM_OUT_b
64	63	PTD6/LLWU_P15	ADC0_SE7b	ADC0_SE7b	PTD6/LLWU_P15	SPI0_PCS3	UART0_RX	FTM0_CH6	FB_AD0	FTM0_FLT0f
65	64	PTD7	DISABLED		PTD7	CMT_IRO	UART0_TX	FTM0_CH7		FTM0_FLT1

4.5 KiB Raw Blame History

4.5 KiB

Raw Blame History