circuitpython/ports/stm32/boards/STM32F7DISC/pins.csv
forester3 02fbb0a455 stm32/boards/STM32F7DISC: Enable onboard SDRAM.
The default SYSCLK frequency is reduced to 192MHz because SDRAM requires it
to be 200MHz or less.
2018-08-14 16:04:10 +10:00

94 lines
1.1 KiB
Plaintext

A0,PA0
A1,PF10
A2,PF9
A3,PF8
A4,PF7
A5,PF6
D0,PC7
D1,PC6
D2,PG6
D3,PB4
D4,PG7
D5,PA8
D6,PH6
D7,PI3
D8,PI2
D9,PA15
D10,PI0
D11,PB15
D12,PB14
D13,PI1
D14,PB9
D15,PB8
LED,PI1
SW,PI11
TP1,PH2
TP2,PI8
TP3,PH15
AUDIO_INT,PD6
AUDIO_SDA,PH8
AUDIO_SCL,PH7
EXT_SDA,PB9
EXT_SCL,PB8
EXT_RST,PG3
SD_D0,PC8
SD_D1,PC9
SD_D2,PC10
SD_D3,PC11
SD_CK,PC12
SD_CMD,PD2
SD_SW,PC13
LCD_BL_CTRL,PK3
LCD_INT,PI13
LCD_SDA,PH8
LCD_SCL,PH7
OTG_FS_POWER,PD5
OTG_FS_OVER_CURRENT,PD4
OTG_HS_OVER_CURRENT,PE3
USB_VBUS,PJ12
USB_ID,PA10
USB_DM,PA11
USB_DP,PA12
VCP_TX,PA9
VCP_RX,PB7
CAN_TX,PB13
CAN_RX,PB12
SDRAM_SDCKE0,PC3
SDRAM_SDNE0,PH3
SDRAM_SDCLK,PG8
SDRAM_SDNCAS,PG15
SDRAM_SDNRAS,PF11
SDRAM_SDNWE,PH5
SDRAM_BA0,PG4
SDRAM_BA1,PG5
SDRAM_NBL0,PE0
SDRAM_NBL1,PE1
SDRAM_A0,PF0
SDRAM_A1,PF1
SDRAM_A2,PF2
SDRAM_A3,PF3
SDRAM_A4,PF4
SDRAM_A5,PF5
SDRAM_A6,PF12
SDRAM_A7,PF13
SDRAM_A8,PF14
SDRAM_A9,PF15
SDRAM_A10,PG0
SDRAM_A11,PG1
SDRAM_D0,PD14
SDRAM_D1,PD15
SDRAM_D2,PD0
SDRAM_D3,PD1
SDRAM_D4,PE7
SDRAM_D5,PE8
SDRAM_D6,PE9
SDRAM_D7,PE10
SDRAM_D8,PE11
SDRAM_D9,PE12
SDRAM_D10,PE13
SDRAM_D11,PE14
SDRAM_D12,PE15
SDRAM_D13,PD8
SDRAM_D14,PD9
SDRAM_D15,PD10