Commit Graph

9 Commits

Author SHA1 Message Date
Jeff Epler
c6bc9c48c9
mimxrt10xx: implement i2sout
tested on metro m7 (green prototype version) with max98357a i2s amplifier and the following test code:
```py
import board
import time
import digitalio
from audiobusio import I2SOut
from audiocore import RawSample
from microcontroller import pin
from ulab import numpy as np

n = np.array(np.sin(np.linspace(0, np.pi*2, 218, endpoint=False)) * 200, dtype=np.int16)
print(n)
r = RawSample(n, sample_rate=8000, channel_count=2)
def main():
    with digitalio.DigitalInOut(board.LED) as l:
        l.switch_to_output(True)
        value = False
        while True:
            with I2SOut(pin.GPIO_06, pin.GPIO_07, pin.GPIO_04) as i:
                time.sleep(.01)
                l.value = value = not value
                i.play(r, loop=True)
                print(i.playing)
                time.sleep(.5)
                i.stop()
                print("STOPPED")
                print(i.playing)
                time.sleep(.5)
                i.play(r, loop=True)
                print(i.playing)
                print("PLAY AGAIN")
                time.sleep(.5)
            time.sleep(1)
```

Only stereo, 16-bit, raw samples were tested; the sample rate is actually fixed
at 48kHz in the core right now. There is more to do, but the basics work.

# Conflicts:
#	ports/mimxrt10xx/Makefile
#	ports/mimxrt10xx/mpconfigport.mk
2023-03-22 12:15:25 -05:00
Scott Shawcroft
5bb8a7a7c6
Improve iMX RT performance
* Enable dcache for OCRAM where the VM heap lives.
* Add CIRCUITPY_SWO_TRACE for pushing program counters out over the
  SWO pin via the ITM module in the CPU. Exempt some functions from
  instrumentation to reduce traffic and allow inlining.
* Place more functions in ITCM to handle errors using code in RAM-only
  and speed up CP.
* Use SET and CLEAR registers for digitalio. The SDK does read, mask
  and write.
* Switch to 2MiB reserved for CircuitPython code. Up from 1MiB.
* Run USB interrupts during flash erase and write.
* Allow storage writes from CP if the USB drive is disabled.
* Get perf bench tests running on CircuitPython and increase timeouts
  so it works when instrumentation is active.
2023-03-14 12:30:58 -07:00
Scott Shawcroft
931c7c1c51
Add Bangle.js 2, JDI memory displays and ACeP epd
This 2-in-1 PR started with the goal of support the Bangle.js 2
smartwatch with *no USB*.
* Adds "secure" DFU build support with a committed private key.
* Adds 3-bit color support with one dummy bit for the JDI memory display
* Allows nrf boards to have a board_background_task() run in RUN_BACKGROUND_TASK.
  This is needed because the Bangle.js 2 uses the watchdog to reset.
* Renamed port_background_task() to port_background_tick() to indicate it
  runs on tick, not RUN_BACKGROUND_TASK.
* Marks serial connected when the display terminal is inited. This means
  that safe mode messages show up on the display.

ACep, 7-color epaper displays also pack 3 bits in 4. So, I added that
support as well.
* Adds 3-bit ACeP color support for 7-color e-paper displays. (Not
  watch related but similar due to color depth.)
* Allows a refresh sequence instead of a single int command. The 7" ACeP
  display requires a data byte for refresh.
* Adds optional delay after resetting the display. The ACeP displays
  need this. (Probably to load LUTs from flash.)
* Adds a cleaning phase for ACeP displays before the real refresh.

For both:
* Add dither support to Palette.
* Palette no longer converts colors when set. Instead, it caches
  converted colors at each index.
* ColorConverter now caches the last converted color. It should make
  conversions faster for repeated colors (not dithering.)
2023-02-15 15:03:40 -08:00
microDev
a52eb88031
run code formatting script 2021-03-15 19:27:36 +05:30
Jeff Epler
1df48176ce supervisor: factor supervisor_background_tasks from sundry ports 2020-07-15 11:49:44 -05:00
Scott Shawcroft
5e1e4d32db
Get basic sleep going on the iMX RT 1011 2020-03-24 15:46:10 -07:00
arturo182
feac87901a mimxrt10xx: Enable displayio
Closes #2466
2020-02-19 22:26:00 +01:00
Scott Shawcroft
7d8dac9211
Refine iMX RT memory layout and add three boards
Introduces a way to place CircuitPython code and data into
tightly coupled memory (TCM) which is accessible by the CPU in a
single cycle. It also frees up room in the corresponding cache for
intermittent data. Loading from external flash is slow!

The data cache is also now enabled.

Adds support for the iMX RT 1021 chip. Adds three new boards:
* iMX RT 1020 EVK
* iMX RT 1060 EVK
* Teensy 4.0

Related to #2492, #2472 and #2477. Fixes #2475.
2020-01-17 17:36:08 -08:00
arturo182
13e0cba6f1 Add initial MIMXRT10XX port 2020-01-06 21:08:49 +01:00