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Refine iMX RT memory layout and add three boards 

Introduces a way to place CircuitPython code and data into
tightly coupled memory (TCM) which is accessible by the CPU in a
single cycle. It also frees up room in the corresponding cache for
intermittent data. Loading from external flash is slow!

The data cache is also now enabled.

Adds support for the iMX RT 1021 chip. Adds three new boards:
* iMX RT 1020 EVK
* iMX RT 1060 EVK
* Teensy 4.0

Related to #2492, #2472 and #2477. Fixes #2475.
This commit is contained in:
Scott Shawcroft 2020-01-08 20:32:45 -08:00
parent 85c731734a
commit 7d8dac9211
No known key found for this signature in database
GPG Key ID: 9349BC7E64B1921E
82 changed files with 2717 additions and 530 deletions
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3
.github/workflows/build.yml vendored
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@ -113,6 +113,8 @@ jobs:
- "hallowing_m0_express"
- "hallowing_m4_express"
- "imxrt1010_evk"
- "imxrt1020_evk"
- "imxrt1060_evk"
- "itsybitsy_m0_express"
- "itsybitsy_m4_express"
- "itsybitsy_nrf52840_express"
@ -163,6 +165,7 @@ jobs:
- "stm32f411ve_discovery"
- "stm32f412zg_discovery"
- "stringcar_m0_express"
- "teensy40"
- "teknikio_bluebird"
- "trellis_m4_express"
- "trinket_m0"

2
.gitmodules vendored
View File

@ -110,4 +110,4 @@
url = https://github.com/adafruit/Adafruit_MP3
[submodule "ports/mimxrt10xx/sdk"]
path = ports/mimxrt10xx/sdk
url = https://github.com/arturo182/MIMXRT10xx_SDK
url = https://github.com/adafruit/MIMXRT10xx_SDK

2
lib/tinyusb

@ -1 +1 @@
Subproject commit dda4c9a94b509238faa7b5ab5b9464c1d2e63ff0
Subproject commit 1f95f439e11f519e69d75a4a8b7b9f28eaf5060e

20
ports/mimxrt10xx/Makefile
View File

@ -71,6 +71,7 @@ INC += \
-Isdk/CMSIS/Include \
-Isdk/devices/$(CHIP_FAMILY) \
-Isdk/devices/$(CHIP_FAMILY)/drivers \
-Isdk/devices/$(CHIP_FAMILY)/xip \
# NDEBUG disables assert() statements. This reduces code size pretty dramatically, per tannewt.
@ -114,6 +115,7 @@ CFLAGS += \
-mfpu=fpv5-sp-d16 \
-DCPU_$(CHIP_VARIANT) \
-DDEBUG \
-DIMXRT10XX \
-DXIP_EXTERNAL_FLASH=1 \
-DXIP_BOOT_HEADER_ENABLE=1 \
-D__START=main \
@ -121,7 +123,11 @@ CFLAGS += \
-ffunction-sections -fdata-sections -fstack-usage \
-D__STARTUP_CLEAR_BSS
LDFLAGS = $(CFLAGS) -nostartfiles -fshort-enums -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs
LD_FILES = $(wildcard boards/$(BOARD)/*.ld) $(addprefix linking/, flash/$(FLASH).ld chip_family/$(CHIP_FAMILY).ld common.ld)
LD_SCRIPT_FLAG := -Wl,-T,
LDFLAGS = $(CFLAGS) -nostartfiles -fshort-enums -Wl,-nostdlib $(addprefix $(LD_SCRIPT_FLAG), $(LD_FILES)) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs
LIBS := -lgcc -lc -lnosys -lm
# Use toolchain libm if we're not using our own.
@ -154,6 +160,7 @@ SRC_SDK := $(addprefix sdk/devices/$(CHIP_FAMILY)/, $(SRC_SDK))
SRC_C = \
background.c \
boards/$(BOARD)/board.c \
boards/$(BOARD)/flash_config.c \
boards/$(BOARD)/pins.c \
fatfs_port.c \
lib/mp-readline/readline.c \
@ -231,20 +238,23 @@ OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
all: $(BUILD)/firmware.bin $(BUILD)/firmware.uf2
all: $(BUILD)/firmware.bin $(BUILD)/firmware.uf2 $(BUILD)/firmware.hex
$(BUILD)/firmware.elf: $(LD_FILE) $(OBJ)
$(BUILD)/firmware.elf: $(OBJ) $(LD_FILES)
$(STEPECHO) "LINK $@"
$(Q)$(CC) -o $@ $(LDFLAGS) $(filter-out $<,$^) -Wl,--start-group $(LIBS) -Wl,--end-group
$(Q)$(CC) -o $@ $(LDFLAGS) $(filter-out %.ld, $^) -Wl,--start-group $(LIBS) -Wl,--end-group
$(BUILD)/firmware.bin: $(BUILD)/firmware.elf
$(STEPECHO) "Create $@"
$(Q)$(OBJCOPY) -O binary -j .interrupts -j .text -j .ARM.exidx -j .data $^ $@
$(Q)$(OBJCOPY) -O binary -j .text -j .ARM.exidx -j .data -j .itcm -j .dtcm_data $^ $@
$(BUILD)/firmware.uf2: $(BUILD)/firmware.bin
$(STEPECHO) "Create $@"
$(Q)$(PYTHON3) $(TOP)/tools/uf2/utils/uf2conv.py -b $(BOOTLOADER_SIZE) -f MIMXRT10XX -c -o $@ $^
$(BUILD)/firmware.hex: $(BUILD)/firmware.elf
$(Q)$(OBJCOPY) -O ihex -j .flash_config -j .ivt -j .text -j .ARM.exidx -j .data -j .itcm -j .dtcm_data $< $@
include $(TOP)/py/mkrules.mk
# Print out the value of a make variable.

3
ports/mimxrt10xx/background.c
View File

@ -34,6 +34,7 @@
#include "py/runtime.h"
#include "shared-module/network/__init__.h"
#include "supervisor/linker.h"
#include "supervisor/shared/stack.h"
// TODO
@ -51,7 +52,7 @@ void background_tasks_reset(void) {
running_background_tasks = false;
}
void run_background_tasks(void) {
void PLACE_IN_ITCM(run_background_tasks)(void) {
// Don't call ourselves recursively.
if (running_background_tasks) {
return;

16
ports/mimxrt10xx/boards/feather_mimxrt1011/board.c
View File

@ -27,24 +27,8 @@
#include "boards/board.h"
#include "mpconfigboard.h"
#include "fsl_iomuxc.h"
void board_init(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_12_FLEXSPI_A_DQS, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B,0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_12_FLEXSPI_A_DQS, 0x10E1U);
}
bool board_requests_safe_mode(void) {

122
ports/mimxrt10xx/boards/feather_mimxrt1011/flash_config.c Normal file
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@ -0,0 +1,122 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexspi_nor_boot.h"
#include "fsl_flexspi_nor_config.h"
__attribute__((section(".boot_hdr.ivt")))
/*************************************
* IVT Data
*************************************/
const ivt image_vector_table = {
IVT_HEADER, /* IVT Header */
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
IVT_RSVD, /* Reserved = 0 */
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
IVT_RSVD /* Reserved = 0 */
};
__attribute__((section(".boot_hdr.boot_data")))
/*************************************
* Boot Data
*************************************/
const BOOT_DATA_T boot_data = {
FLASH_BASE, /* boot start location */
FLASH_SIZE, /* size */
PLUGIN_FLAG, /* Plugin flag*/
0xFFFFFFFF /* empty - extra data word */
};
__attribute__((section(".boot_hdr.conf")))
// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 1u,
.csSetupTime = 2u,
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
0,
0,
0x24040405,
0,
0,
0,
0,
0,
0,
0,
0x00000406,
0,
0,
0,
0,
0,
0,
0,
0x08180420,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0x081804D8,
0,
0,
0,
0x08180402,
0x00002004,
0,
0,
0,
0,
0,
0,
0x00000460,
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
.blockSize = 0x00010000,
.isUniformBlockSize = false,
};

11
ports/mimxrt10xx/boards/feather_mimxrt1011/mpconfigboard.h
View File

@ -1,19 +1,8 @@
#define MICROPY_HW_BOARD_NAME "Feather MIMXRT1011"
#define MICROPY_HW_MCU_NAME "IMXRT1011DAE5A"
//TODO
//#define MICROPY_HW_LED_STATUS (&pin_PA27)
#define MICROPY_HW_NEOPIXEL (&pin_GPIO_SD_05)
// These are pins not to reset.
// QSPI Data pins
//#define MICROPY_PORT_A ( PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 )
// QSPI CS, and QSPI SCK
//#define MICROPY_PORT_B ( PORT_PB10 | PORT_PB11 | PORT_PB22 )
//#define MICROPY_PORT_C ( 0 )
//#define MICROPY_PORT_D ( 0 )
// If you change this, then make sure to update the linker scripts as well to
// make sure you don't overwrite code
#define CIRCUITPY_INTERNAL_NVM_SIZE 0

15
ports/mimxrt10xx/boards/feather_mimxrt1011/mpconfigboard.mk
View File

@ -1,21 +1,8 @@
LD_FILE = boards/mimxrt1011-bootloader-external-flash.ld
USB_VID = 0x239A
USB_PID = 0x8074
USB_PRODUCT = "Feather MIMXRT1011"
USB_MANUFACTURER = "arturo182"
USB_DEVICES = "CDC,MSC,HID"
CHIP_VARIANT = MIMXRT1011DAE5A
CHIP_FAMILY = MIMXRT1011
INTERNAL_FLASH_FILESYSTEM = 1
CIRCUITPY_DISPLAYIO = 0
CIRCUITPY_AUDIOIO = 0
CIRCUITPY_AUDIOBUSIO = 0
CIRCUITPY_FREQUENCYIO = 0
CIRCUITPY_I2CSLAVE = 0
CIRCUITPY_NVM = 0
CIRCUITPY_ROTARYIO = 0
LONGINT_IMPL = MPZ
FLASH = W25Q64JV

16
ports/mimxrt10xx/boards/feather_mimxrt1062/board.c
View File

@ -27,24 +27,8 @@
#include "boards/board.h"
#include "mpconfigboard.h"
#include "fsl_iomuxc.h"
void board_init(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B,0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0x10E1U);
}
bool board_requests_safe_mode(void) {

122
ports/mimxrt10xx/boards/feather_mimxrt1062/flash_config.c Normal file
View File

@ -0,0 +1,122 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexspi_nor_boot.h"
#include "fsl_flexspi_nor_config.h"
__attribute__((section(".boot_hdr.ivt")))
/*************************************
* IVT Data
*************************************/
const ivt image_vector_table = {
IVT_HEADER, /* IVT Header */
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
IVT_RSVD, /* Reserved = 0 */
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
IVT_RSVD /* Reserved = 0 */
};
__attribute__((section(".boot_hdr.boot_data")))
/*************************************
* Boot Data
*************************************/
const BOOT_DATA_T boot_data = {
FLASH_BASE, /* boot start location */
FLASH_SIZE, /* size */
PLUGIN_FLAG, /* Plugin flag*/
0xFFFFFFFF /* empty - extra data word */
};
__attribute__((section(".boot_hdr.conf")))
// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 1u,
.csSetupTime = 2u,
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
0,
0,
0x24040405,
0,
0,
0,
0,
0,
0,
0,
0x00000406,
0,
0,
0,
0,
0,
0,
0,
0x08180420,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0x081804D8,
0,
0,
0,
0x08180402,
0x00002004,
0,
0,
0,
0,
0,
0,
0x00000460,
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
.blockSize = 0x00010000,
.isUniformBlockSize = false,
};

8
ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.h
View File

@ -6,14 +6,6 @@
//#define MICROPY_HW_NEOPIXEL (&pin_PB22)
// These are pins not to reset.
// QSPI Data pins
//#define MICROPY_PORT_A ( PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 )
// QSPI CS, and QSPI SCK
//#define MICROPY_PORT_B ( PORT_PB10 | PORT_PB11 | PORT_PB22 )
//#define MICROPY_PORT_C ( 0 )
//#define MICROPY_PORT_D ( 0 )
// If you change this, then make sure to update the linker scripts as well to
// make sure you don't overwrite code
#define CIRCUITPY_INTERNAL_NVM_SIZE 0

15
ports/mimxrt10xx/boards/feather_mimxrt1062/mpconfigboard.mk
View File

@ -1,21 +1,8 @@
LD_FILE = boards/mimxrt1062-bootloader-external-flash.ld
USB_VID = 0x239A
USB_PID = 0x8076
USB_PRODUCT = "Feather MIMXRT1062"
USB_MANUFACTURER = "arturo182"
USB_DEVICES = "CDC,MSC,HID"
CHIP_VARIANT = MIMXRT1062DVJ6A
CHIP_FAMILY = MIMXRT1062
INTERNAL_FLASH_FILESYSTEM = 1
CIRCUITPY_DISPLAYIO = 0
CIRCUITPY_AUDIOIO = 0
CIRCUITPY_AUDIOBUSIO = 0
CIRCUITPY_FREQUENCYIO = 0
CIRCUITPY_I2CSLAVE = 0
CIRCUITPY_NVM = 0
CIRCUITPY_ROTARYIO = 0
LONGINT_IMPL = MPZ
FLASH = W25Q64JV

16
ports/mimxrt10xx/boards/imxrt1010_evk/board.c
View File

@ -27,24 +27,8 @@
#include "boards/board.h"
#include "mpconfigboard.h"
#include "fsl_iomuxc.h"
void board_init(void) {
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_12_FLEXSPI_A_DQS, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B,0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3, 0x10E1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_12_FLEXSPI_A_DQS, 0x10E1U);
}
bool board_requests_safe_mode(void) {

141
ports/mimxrt10xx/boards/imxrt1010_evk/flash_config.c Normal file
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@ -0,0 +1,141 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexspi_nor_boot.h"
#include "fsl_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_device"
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.ivt")))
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.ivt"
#endif
/*************************************
* IVT Data
*************************************/
const ivt image_vector_table = {
IVT_HEADER, /* IVT Header */
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
IVT_RSVD, /* Reserved = 0 */
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
IVT_RSVD /* Reserved = 0 */
};
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.boot_data")))
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.boot_data"
#endif
/*************************************
* Boot Data
*************************************/
const BOOT_DATA_T boot_data = {
FLASH_BASE, /* boot start location */
FLASH_SIZE, /* size */
PLUGIN_FLAG, /* Plugin flag*/
0xFFFFFFFF /* empty - extra data word */
};
#endif
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 1u,
.csSetupTime = 2u,
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
0,
0,
0x24040405,
0,
0,
0,
0,
0,
0,
0,
0x00000406,
0,
0,
0,
0,
0,
0,
0,
0x08180420,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0x081804D8,
0,
0,
0,
0x08180402,
0x00002004,
0,
0,
0,
0,
0,
0,
0x00000460,
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
.blockSize = 0x00010000,
.isUniformBlockSize = false,
};

17
ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.h
View File

@ -1,19 +1,6 @@
#define MICROPY_HW_BOARD_NAME "IMXRT1010-EVK"
#define MICROPY_HW_MCU_NAME "IMXRT1011DAE5A"
//TODO
//#define MICROPY_HW_LED_STATUS (&pin_PA27)
//#define MICROPY_HW_NEOPIXEL (&pin_PB22)
// These are pins not to reset.
// QSPI Data pins
//#define MICROPY_PORT_A ( PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11 )
// QSPI CS, and QSPI SCK
//#define MICROPY_PORT_B ( PORT_PB10 | PORT_PB11 | PORT_PB22 )
//#define MICROPY_PORT_C ( 0 )
//#define MICROPY_PORT_D ( 0 )
// If you change this, then make sure to update the linker scripts as well to
// make sure you don't overwrite code
#define CIRCUITPY_INTERNAL_NVM_SIZE 0
@ -23,9 +10,5 @@
#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_02)
#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_01)
#define DEFAULT_SPI_BUS_SCK (&pin_GPIO_AD_06)
#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO_AD_04)
#define DEFAULT_SPI_BUS_MISO (&pin_GPIO_AD_03)
#define DEFAULT_UART_BUS_RX (&pin_GPIO_09)
#define DEFAULT_UART_BUS_TX (&pin_GPIO_10)

16
ports/mimxrt10xx/boards/imxrt1010_evk/mpconfigboard.mk
View File

@ -1,22 +1,8 @@
LD_FILE = boards/mimxrt1011-bootloader-external-flash.ld
USB_VID = 0x239A
USB_PID = 0x8078
USB_PRODUCT = "IMXRT1010-EVK"
USB_MANUFACTURER = "NXP"
USB_DEVICES = "CDC,MSC,HID"
CHIP_VARIANT = MIMXRT1011DAE5A
CHIP_FAMILY = MIMXRT1011
INTERNAL_FLASH_FILESYSTEM = 1
CIRCUITPY_DISPLAYIO = 0
CIRCUITPY_AUDIOIO = 0
CIRCUITPY_AUDIOBUSIO = 0
CIRCUITPY_FREQUENCYIO = 0
CIRCUITPY_I2CSLAVE = 0
CIRCUITPY_NEOPIXEL_WRITE = 0
CIRCUITPY_NVM = 0
CIRCUITPY_ROTARYIO = 0
LONGINT_IMPL = MPZ
FLASH = AT25SF128A

30
ports/mimxrt10xx/boards/imxrt1010_evk/pins.c
View File

@ -4,21 +4,25 @@
STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_AD_06) },
//{ MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_08) }, // Connected to audio codec
//{ MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_01) }, // Connected to audio codec
{ MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_08) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_AD_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_AD_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_SD_02) },
//{ MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_03) }, // Connected to audio codec
{ MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_AD_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_AD_04) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_AD_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_AD_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_09) },
@ -27,8 +31,24 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USR_LED), MP_ROM_PTR(&pin_GPIO_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USR_SW), MP_ROM_PTR(&pin_GPIO_SD_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USER_SW), MP_ROM_PTR(&pin_GPIO_SD_05) },
// Audio Interface
{ MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_GPIO_00) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_SYNC), MP_ROM_PTR(&pin_GPIO_07) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_BCLK), MP_ROM_PTR(&pin_GPIO_06) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_RXD), MP_ROM_PTR(&pin_GPIO_03) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_TXD), MP_ROM_PTR(&pin_GPIO_04) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_MCLK), MP_ROM_PTR(&pin_GPIO_08) },
// SPDIF
{ MP_ROM_QSTR(MP_QSTR_SPDIF_IN), MP_ROM_PTR(&pin_GPIO_10) },
{ MP_ROM_QSTR(MP_QSTR_SPDIF_OUT), MP_ROM_PTR(&pin_GPIO_11) },
// Freelink UART
{ MP_ROM_QSTR(MP_QSTR_FREELINK_TX), MP_ROM_PTR(&pin_GPIO_10) },
{ MP_ROM_QSTR(MP_QSTR_FREELINK_RX), MP_ROM_PTR(&pin_GPIO_09) },
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
{ MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },

39
ports/mimxrt10xx/boards/imxrt1020_evk/board.c Normal file
View File

@ -0,0 +1,39 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
* Copyright (c) 2019 Artur Pacholec
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "boards/board.h"
#include "mpconfigboard.h"
void board_init(void) {
}
bool board_requests_safe_mode(void) {
return false;
}
void reset_board(void) {
}

122
ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c Normal file
View File

@ -0,0 +1,122 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexspi_nor_boot.h"
#include "fsl_flexspi_nor_config.h"
__attribute__((section(".boot_hdr.ivt")))
/*************************************
* IVT Data
*************************************/
const ivt image_vector_table = {
IVT_HEADER, /* IVT Header */
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
IVT_RSVD, /* Reserved = 0 */
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
IVT_RSVD /* Reserved = 0 */
};
__attribute__((section(".boot_hdr.boot_data")))
/*************************************
* Boot Data
*************************************/
const BOOT_DATA_T boot_data = {
FLASH_BASE, /* boot start location */
FLASH_SIZE, /* size */
PLUGIN_FLAG, /* Plugin flag*/
0xFFFFFFFF /* empty - extra data word */
};
__attribute__((section(".boot_hdr.conf")))
// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 1u,
.csSetupTime = 2u,
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
0,
0,
0x24040405,
0,
0,
0,
0,
0,
0,
0,
0x00000406,
0,
0,
0,
0,
0,
0,
0,
0x08180420,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0x081804D8,
0,
0,
0,
0x08180402,
0x00002004,
0,
0,
0,
0,
0,
0,
0x00000460,
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
.blockSize = 0x00010000,
.isUniformBlockSize = false,
};

14
ports/mimxrt10xx/boards/imxrt1020_evk/mpconfigboard.h Normal file
View File

@ -0,0 +1,14 @@
#define MICROPY_HW_BOARD_NAME "iMX RT 1020 EVK"
#define MICROPY_HW_MCU_NAME "IMXRT1021DAG5A"
// If you change this, then make sure to update the linker scripts as well to
// make sure you don't overwrite code
#define CIRCUITPY_INTERNAL_NVM_SIZE 0
#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_SD_B1_03)
#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_SD_B1_02)
#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B1_09)
#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B1_08)

8
ports/mimxrt10xx/boards/imxrt1020_evk/mpconfigboard.mk Normal file
View File

@ -0,0 +1,8 @@
USB_VID = 0x16C0
USB_PID = 0x8888
USB_PRODUCT = "iMX RT 1020 EVK"
USB_MANUFACTURER = "NXP"
CHIP_VARIANT = MIMXRT1021DAG5A
CHIP_FAMILY = MIMXRT1021
FLASH = IS25LP064A

84
ports/mimxrt10xx/boards/imxrt1020_evk/pins.c Normal file
View File

@ -0,0 +1,84 @@
#include "shared-bindings/board/__init__.h"
#include "boards/board.h"
STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_AD_B0_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_AD_B0_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_AD_B0_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_SD_B1_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_SD_B1_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_SD_B1_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_SD_B1_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_05) },
// SD Card
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_GPIO_SD_B0_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_PWREN), MP_ROM_PTR(&pin_GPIO_SD_B1_04) },
// // Audio Interface
{ MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_SYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_BCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_RXD), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_TXD), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
// // Ethernet
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_MDIO), MP_ROM_PTR(&pin_GPIO_EMC_40) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_MDC), MP_ROM_PTR(&pin_GPIO_EMC_41) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD0), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD1), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_CRS_DV), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD0), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD1), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXEN), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_INT), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_04) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_CLK), MP_ROM_PTR(&pin_GPIO_AD_B0_08) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXER), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
// // Freelink UART
{ MP_ROM_QSTR(MP_QSTR_FREELINK_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_06) },
{ MP_ROM_QSTR(MP_QSTR_FREELINK_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_07) },
// CAN
{ MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_GPIO_SD_B1_00) },
{ MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_GPIO_SD_B1_01) },
{ MP_ROM_QSTR(MP_QSTR_CAN_STBY), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
//
{ MP_ROM_QSTR(MP_QSTR_ACCELEROMETER_SDA), MP_ROM_PTR(&pin_GPIO_SD_B1_03) },
{ MP_ROM_QSTR(MP_QSTR_ACCELEROMETER_SCL), MP_ROM_PTR(&pin_GPIO_SD_B1_02) },
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
};
MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);

39
ports/mimxrt10xx/boards/imxrt1060_evk/board.c Normal file
View File

@ -0,0 +1,39 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
* Copyright (c) 2019 Artur Pacholec
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "boards/board.h"
#include "mpconfigboard.h"
void board_init(void) {
}
bool board_requests_safe_mode(void) {
return false;
}
void reset_board(void) {
}

141
ports/mimxrt10xx/boards/imxrt1060_evk/flash_config.c Normal file
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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexspi_nor_boot.h"
#include "fsl_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_device"
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.ivt")))
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.ivt"
#endif
/*************************************
* IVT Data
*************************************/
const ivt image_vector_table = {
IVT_HEADER, /* IVT Header */
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
IVT_RSVD, /* Reserved = 0 */
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
IVT_RSVD /* Reserved = 0 */
};
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.boot_data")))
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.boot_data"
#endif
/*************************************
* Boot Data
*************************************/
const BOOT_DATA_T boot_data = {
FLASH_BASE, /* boot start location */
FLASH_SIZE, /* size */
PLUGIN_FLAG, /* Plugin flag*/
0xFFFFFFFF /* empty - extra data word */
};
#endif
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 1u,
.csSetupTime = 2u,
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
.sflashA1Size = FLASH_SIZE,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
0,
0,
0x24040405,
0,
0,
0,
0,
0,
0,
0,
0x00000406,
0,
0,
0,
0,
0,
0,
0,
0x08180420,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0x081804D8,
0,
0,
0,
0x08180402,
0x00002004,
0,
0,
0,
0,
0,
0,
0x00000460,
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
.blockSize = 0x00010000,
.isUniformBlockSize = false,
};

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ports/mimxrt10xx/boards/imxrt1060_evk/mpconfigboard.h Normal file
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#define MICROPY_HW_BOARD_NAME "iMX RT 1060 EVK"
#define MICROPY_HW_MCU_NAME "IMXRT1062DVJ6A"
// If you change this, then make sure to update the linker scripts as well to
// make sure you don't overwrite code
#define CIRCUITPY_INTERNAL_NVM_SIZE 0
#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_AD_B1_00)
#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_AD_B1_01)
#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B1_07)
#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B1_06)

8
ports/mimxrt10xx/boards/imxrt1060_evk/mpconfigboard.mk Normal file
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USB_VID = 0x16C0
USB_PID = 0x8888
USB_PRODUCT = "iMX RT 1060 EVK"
USB_MANUFACTURER = "NXP"
CHIP_VARIANT = MIMXRT1062DVJ6A
CHIP_FAMILY = MIMXRT1062
FLASH = IS25WP064A

128
ports/mimxrt10xx/boards/imxrt1060_evk/pins.c Normal file
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#include "shared-bindings/board/__init__.h"
#include "boards/board.h"
STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
{ MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_AD_B0_09) }, // Connected to audio codec
{ MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_AD_B0_10) }, // Connected to audio codec
{ MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_AD_B0_02) }, // Connected to audio codec
{ MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
// i2c sensor is on I2C1_SCL/SDA
{ MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
// Camera Sensor Interface
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_VSYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_PWDN), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_HSYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D9), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D8), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_PIXCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D2), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D5), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D3), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D4), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
// SD Card
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_GPIO_B1_12) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_PWREN), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
// LCD Interface
{ MP_ROM_QSTR(MP_QSTR_LCD_BACKLIGHT), MP_ROM_PTR(&pin_GPIO_B1_15) },
{ MP_ROM_QSTR(MP_QSTR_LCD_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
{ MP_ROM_QSTR(MP_QSTR_LCD_ENABLE), MP_ROM_PTR(&pin_GPIO_B0_01) },
{ MP_ROM_QSTR(MP_QSTR_LCD_VSYNC), MP_ROM_PTR(&pin_GPIO_B0_03) },
{ MP_ROM_QSTR(MP_QSTR_LCD_HSYNC), MP_ROM_PTR(&pin_GPIO_B0_02) },
{ MP_ROM_QSTR(MP_QSTR_LCD_CLK), MP_ROM_PTR(&pin_GPIO_B0_00) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D0), MP_ROM_PTR(&pin_GPIO_B0_04) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D1), MP_ROM_PTR(&pin_GPIO_B0_05) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D2), MP_ROM_PTR(&pin_GPIO_B0_06) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D3), MP_ROM_PTR(&pin_GPIO_B0_07) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D4), MP_ROM_PTR(&pin_GPIO_B0_08) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D5), MP_ROM_PTR(&pin_GPIO_B0_09) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D6), MP_ROM_PTR(&pin_GPIO_B0_10) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D7), MP_ROM_PTR(&pin_GPIO_B0_11) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D8), MP_ROM_PTR(&pin_GPIO_B0_12) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D9), MP_ROM_PTR(&pin_GPIO_B0_13) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D10), MP_ROM_PTR(&pin_GPIO_B0_14) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D11), MP_ROM_PTR(&pin_GPIO_B0_15) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D12), MP_ROM_PTR(&pin_GPIO_B1_00) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D13), MP_ROM_PTR(&pin_GPIO_B1_01) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D14), MP_ROM_PTR(&pin_GPIO_B1_02) },
{ MP_ROM_QSTR(MP_QSTR_LCD_D15), MP_ROM_PTR(&pin_GPIO_B1_03) },
// Touch Interface
{ MP_ROM_QSTR(MP_QSTR_LCD_TOUCH_INT), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
// Audio Interface
{ MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_SYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_BCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_RXD), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_TXD), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
{ MP_ROM_QSTR(MP_QSTR_AUDIO_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
// SPDIF
{ MP_ROM_QSTR(MP_QSTR_SPDIF_IN), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
{ MP_ROM_QSTR(MP_QSTR_SPDIF_OUT), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
// Ethernet
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_MDIO), MP_ROM_PTR(&pin_GPIO_EMC_41) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_MDC), MP_ROM_PTR(&pin_GPIO_EMC_40) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD0), MP_ROM_PTR(&pin_GPIO_B1_04) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD1), MP_ROM_PTR(&pin_GPIO_B1_05) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_CRS_DV), MP_ROM_PTR(&pin_GPIO_B1_06) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD0), MP_ROM_PTR(&pin_GPIO_B1_07) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD1), MP_ROM_PTR(&pin_GPIO_B1_08) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXEN), MP_ROM_PTR(&pin_GPIO_B1_09) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_INT), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_CLK), MP_ROM_PTR(&pin_GPIO_B1_10) },
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXER), MP_ROM_PTR(&pin_GPIO_B1_11) },
// Freelink UART
{ MP_ROM_QSTR(MP_QSTR_FREELINK_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
{ MP_ROM_QSTR(MP_QSTR_FREELINK_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
// CAN
{ MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
{ MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
{ MP_ROM_QSTR(MP_QSTR_CAN_STBY), MP_ROM_PTR(&pin_GPIO_AD_B0_05) },
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
};
MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);

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ports/mimxrt10xx/boards/mimxrt1011-bootloader-external-flash.ld
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ENTRY(Reset_Handler)
_minimum_stack_size = 64K;
_minimum_heap_size = 0;
MEMORY
{
FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 8M
FLASH_BOOTLOADER (rx) : ORIGIN = 0x60000000, LENGTH = 48K
FLASH_ISR (rx) : ORIGIN = 0x6000C000, LENGTH = 1K
FLASH_TEXT (rx) : ORIGIN = 0x6000C400, LENGTH = 975K
FLASH_FATFS (r) : ORIGIN = 0x60100000, LENGTH = 7M
RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 32K
OCRAM (rwx) : ORIGIN = 0x20200000, LENGTH = 64K
}
_estack = ORIGIN(OCRAM) + LENGTH(OCRAM);
_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;
__fatfs_flash_start_addr = ORIGIN(FLASH_FATFS);
__fatfs_flash_length = LENGTH(FLASH_FATFS);
__RAM_VECTOR_TABLE_SIZE_BYTES = 0;
SECTIONS
{
.interrupts :
{
__VECTOR_TABLE = .;
__VECTOR_RAM = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > FLASH_ISR
.text :
{
. = ALIGN(4);
*(EXCLUDE_FILE(
*flexspi_nor_flash_ops.o
*fsl_flexspi.o
) .text*) /* .text* sections (code) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} > FLASH_TEXT
.ARM.exidx :
{
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
_etext = .; /* define a global symbol at end of code */
__etext = .; /* define a global symbol at end of code */
} > FLASH_TEXT
/* used by the startup to initialize data */
_sidata = .;
.data : AT (_sidata)
{
. = ALIGN(4);
__data_start__ = .; /* create a global symbol at data start */
*(.data*) /* .data* sections */
*flexspi_nor_flash_ops.o(.text*)
*fsl_flexspi.o(.text*)
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > RAM
/* Uninitialized data section */
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
PROVIDE(end = .);
} > RAM
.heap :
{
. = ALIGN(8);
_heap_start = .; /* define a global symbol at heap start */
. += _minimum_heap_size;
__HeapLimit = .;
} > OCRAM
.stack :
{
. = ALIGN(8);
. += _minimum_stack_size;
} > OCRAM
.ARM.attributes 0 : { *(.ARM.attributes) }
}
ASSERT(__data_end__ <= ORIGIN(FLASH_TEXT) + LENGTH(FLASH_TEXT), "region FLASH_TEXT overflowed with text and data")
ASSERT(_estack - _minimum_stack_size >= __HeapLimit, "region OCRAM overflowed with stack and heap")

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ports/mimxrt10xx/boards/mimxrt1011-external-flash.ld
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ENTRY(Reset_Handler)
_minimum_stack_size = 64K;
_minimum_heap_size = 0;
MEMORY
{
FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 8M
FLASH_CONFIG (rx) : ORIGIN = 0x60000400, LENGTH = 3K
FLASH_IVT (rx) : ORIGIN = 0x60001000, LENGTH = 4K
FLASH_ISR (rx) : ORIGIN = 0x60002000, LENGTH = 1K
FLASH_TEXT (rx) : ORIGIN = 0x60002400, LENGTH = 1015K
FLASH_FATFS (r) : ORIGIN = 0x60100000, LENGTH = 7M
RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 32K
OCRAM (rwx) : ORIGIN = 0x20200000, LENGTH = 64K
}
_estack = ORIGIN(OCRAM) + LENGTH(OCRAM);
_bootloader_dbl_tap = 0;
__fatfs_flash_start_addr = ORIGIN(FLASH_FATFS);
__fatfs_flash_length = LENGTH(FLASH_FATFS);
__RAM_VECTOR_TABLE_SIZE_BYTES = 0;
SECTIONS
{
.flash_config :
{
. = ALIGN(4);
KEEP(* (.boot_hdr.conf))
. = ALIGN(4);
} > FLASH_CONFIG
.ivt :
{
. = ALIGN(4);
KEEP(* (.boot_hdr.ivt))
KEEP(* (.boot_hdr.boot_data))
KEEP(* (.boot_hdr.dcd_data))
. = ALIGN(4);
} > FLASH_IVT
.interrupts :
{
__VECTOR_TABLE = .;
__VECTOR_RAM = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > FLASH_ISR
.text :
{
. = ALIGN(4);
*(EXCLUDE_FILE(
*flexspi_nor_flash_ops.o
*fsl_flexspi.o
) .text*) /* .text* sections (code) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} > FLASH_TEXT
.ARM.exidx :
{
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
_etext = .; /* define a global symbol at end of code */
__etext = .; /* define a global symbol at end of code */
} > FLASH_TEXT
/* used by the startup to initialize data */
_sidata = .;
.data : AT (_sidata)
{
. = ALIGN(4);
__data_start__ = .; /* create a global symbol at data start */
*(.data*) /* .data* sections */
*flexspi_nor_flash_ops.o(.text*)
*fsl_flexspi.o(.text*)
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > RAM
/* Uninitialized data section */
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
PROVIDE(end = .);
} > RAM
.heap :
{
. = ALIGN(8);
_heap_start = .; /* define a global symbol at heap start */
. += _minimum_heap_size;
__HeapLimit = .;
} > OCRAM
.stack :
{
. = ALIGN(8);
. += _minimum_stack_size;
} > OCRAM
.ARM.attributes 0 : { *(.ARM.attributes) }
}
ASSERT(__data_end__ <= ORIGIN(FLASH_TEXT) + LENGTH(FLASH_TEXT), "region FLASH_TEXT overflowed with text and data")
ASSERT(_estack - _minimum_stack_size >= __HeapLimit, "region OCRAM overflowed with stack and heap")

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ports/mimxrt10xx/boards/mimxrt1062-bootloader-external-flash.ld
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ENTRY(Reset_Handler)
_minimum_stack_size = 64K;
_minimum_heap_size = 0;
MEMORY
{
FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 8M
FLASH_BOOTLOADER (rx) : ORIGIN = 0x60000000, LENGTH = 48K
FLASH_ISR (rx) : ORIGIN = 0x6000C000, LENGTH = 1K
FLASH_TEXT (rx) : ORIGIN = 0x6000C400, LENGTH = 975K
FLASH_FATFS (r) : ORIGIN = 0x60100000, LENGTH = 7M
RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 128K
OCRAM (rwx) : ORIGIN = 0x20200000, LENGTH = 768K
}
_estack = ORIGIN(OCRAM) + LENGTH(OCRAM);
_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;
__fatfs_flash_start_addr = ORIGIN(FLASH_FATFS);
__fatfs_flash_length = LENGTH(FLASH_FATFS);
__RAM_VECTOR_TABLE_SIZE_BYTES = 0;
SECTIONS
{
.interrupts :
{
__VECTOR_TABLE = .;
__VECTOR_RAM = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > FLASH_ISR
.text :
{
. = ALIGN(4);
*(EXCLUDE_FILE(
*flexspi_nor_flash_ops.o
*fsl_flexspi.o
) .text*) /* .text* sections (code) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} > FLASH_TEXT
.ARM.exidx :
{
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
_etext = .; /* define a global symbol at end of code */
__etext = .; /* define a global symbol at end of code */
} > FLASH_TEXT
/* used by the startup to initialize data */
_sidata = .;
.data : AT (_sidata)
{
. = ALIGN(4);
__data_start__ = .; /* create a global symbol at data start */
*(.data*) /* .data* sections */
*flexspi_nor_flash_ops.o(.text*)
*fsl_flexspi.o(.text*)
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > RAM
/* Uninitialized data section */
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
PROVIDE(end = .);
} > RAM
.heap :
{
. = ALIGN(8);
_heap_start = .; /* define a global symbol at heap start */
. += _minimum_heap_size;
__HeapLimit = .;
} > OCRAM
.stack :
{
. = ALIGN(8);
. += _minimum_stack_size;
} > OCRAM
.ARM.attributes 0 : { *(.ARM.attributes) }
}
ASSERT(__data_end__ <= ORIGIN(FLASH_TEXT) + LENGTH(FLASH_TEXT), "region FLASH_TEXT overflowed with text and data")
ASSERT(_estack - _minimum_stack_size >= __HeapLimit, "region OCRAM overflowed with stack and heap")

39
ports/mimxrt10xx/boards/teensy40/board.c Normal file
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@ -0,0 +1,39 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
* Copyright (c) 2019 Artur Pacholec
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "boards/board.h"
#include "mpconfigboard.h"
void board_init(void) {
}
bool board_requests_safe_mode(void) {
return false;
}
void reset_board(void) {
}

1
ports/mimxrt10xx/boards/teensy40/board.ld Normal file
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@ -0,0 +1 @@
_ld_reserved_flash_size = 4K;

141
ports/mimxrt10xx/boards/teensy40/flash_config.c Normal file
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@ -0,0 +1,141 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_flexspi_nor_boot.h"
#include "fsl_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_device"
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.ivt")))
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.ivt"
#endif
/*************************************
* IVT Data
*************************************/
const ivt image_vector_table = {
IVT_HEADER, /* IVT Header */
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
IVT_RSVD, /* Reserved = 0 */
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
IVT_RSVD /* Reserved = 0 */
};
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.boot_data")))
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.boot_data"
#endif
/*************************************
* Boot Data
*************************************/
const BOOT_DATA_T boot_data = {
FLASH_BASE, /* boot start location */
FLASH_SIZE, /* size */
PLUGIN_FLAG, /* Plugin flag*/
0xFFFFFFFF /* empty - extra data word */
};
#endif
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 1u,
.csSetupTime = 2u,
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
.sflashA1Size = 0x00200000,
.lookupTable =
{
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
0,
0,
0x24040405,
0,
0,
0,
0,
0,
0,
0,
0x00000406,
0,
0,
0,
0,
0,
0,
0,
0x08180420,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0x081804D8,
0,
0,
0,
0x08180402,
0x00002004,
0,
0,
0,
0,
0,
0,
0x00000460,
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
.blockSize = 0x00010000,
.isUniformBlockSize = false,
};

18
ports/mimxrt10xx/boards/teensy40/mpconfigboard.h Normal file
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@ -0,0 +1,18 @@
#define MICROPY_HW_BOARD_NAME "Teensy 4.0"
#define MICROPY_HW_MCU_NAME "IMXRT1062DVJ6A"
// If you change this, then make sure to update the linker scripts as well to
// make sure you don't overwrite code
#define CIRCUITPY_INTERNAL_NVM_SIZE 0
#define BOARD_FLASH_SIZE (2 * 1024 * 1024)
#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_AD_B1_00)
#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_AD_B1_01)
#define DEFAULT_SPI_BUS_SCK (&pin_GPIO_B0_03)
#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO_B0_02)
#define DEFAULT_SPI_BUS_MISO (&pin_GPIO_B0_01)
#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B0_03)
#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B0_02)

8
ports/mimxrt10xx/boards/teensy40/mpconfigboard.mk Normal file
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@ -0,0 +1,8 @@
USB_VID = 0x239A
USB_PID = 0x8888
USB_PRODUCT = "Teensy 4.0"
USB_MANUFACTURER = "PJRC"
CHIP_VARIANT = MIMXRT1062DVJ6A
CHIP_FAMILY = MIMXRT1062
FLASH = W25Q16JV

87
ports/mimxrt10xx/boards/teensy40/pins.c Normal file
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@ -0,0 +1,87 @@
#include "shared-bindings/board/__init__.h"
#include "boards/board.h"
STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
// With USB on left. Bottom edge.
{ MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_RX1), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_TX1), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_EMC_04) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_EMC_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_EMC_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_EMC_08) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_B0_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_B1_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_B1_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_B0_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_B0_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_B0_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO_B0_01) },
// Top edge
{ MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA0), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL0), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
// Back side
{ MP_OBJ_NEW_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_GPIO_EMC_32) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_GPIO_EMC_31) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_GPIO_EMC_37) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_GPIO_EMC_36) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_GPIO_B0_12) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_GPIO_EMC_07) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAT1), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAT0), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAT3), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
{ MP_OBJ_NEW_QSTR(MP_QSTR_DAT2), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
{ MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
};
MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);

6
ports/mimxrt10xx/common-hal/microcontroller/__init__.c
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@ -72,10 +72,10 @@ void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) {
}
// Pretend to be the first of the two reset presses needed to enter the
// bootloader. That way one reset will end in the bootloader.
_bootloader_dbl_tap = DBL_TAP_MAGIC;
SNVS->LPGPR[0] = DBL_TAP_MAGIC;
} else {
// Set up the default.
_bootloader_dbl_tap = DBL_TAP_MAGIC_QUICK_BOOT;
SNVS->LPGPR[0] = DBL_TAP_MAGIC_QUICK_BOOT;
}
if (runmode == RUNMODE_SAFE_MODE) {
safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE);
@ -229,6 +229,7 @@ STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_13), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
{ MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_14), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
{ MP_ROM_QSTR(MP_QSTR_GPIO_AD_B1_15), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
#ifdef MIMXRT1062_SERIES
{ MP_ROM_QSTR(MP_QSTR_GPIO_B0_00), MP_ROM_PTR(&pin_GPIO_B0_00) },
{ MP_ROM_QSTR(MP_QSTR_GPIO_B0_01), MP_ROM_PTR(&pin_GPIO_B0_01) },
{ MP_ROM_QSTR(MP_QSTR_GPIO_B0_02), MP_ROM_PTR(&pin_GPIO_B0_02) },
@ -261,6 +262,7 @@ STATIC const mp_rom_map_elem_t mcu_pin_global_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_GPIO_B1_13), MP_ROM_PTR(&pin_GPIO_B1_13) },
{ MP_ROM_QSTR(MP_QSTR_GPIO_B1_14), MP_ROM_PTR(&pin_GPIO_B1_14) },
{ MP_ROM_QSTR(MP_QSTR_GPIO_B1_15), MP_ROM_PTR(&pin_GPIO_B1_15) },
#endif
{ MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_00), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
{ MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_01), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
{ MP_ROM_QSTR(MP_QSTR_GPIO_SD_B0_02), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },

2
ports/mimxrt10xx/linking/chip_family/MIMXRT1011.ld Normal file
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@ -0,0 +1,2 @@
ram_size = 128K;
flash_config_location = 0x60000400;

2
ports/mimxrt10xx/linking/chip_family/MIMXRT1021.ld Normal file
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@ -0,0 +1,2 @@
ram_size = 256K;
flash_config_location = 0x60000000;

2
ports/mimxrt10xx/linking/chip_family/MIMXRT1062.ld Normal file
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@ -0,0 +1,2 @@
ram_size = 1M;
flash_config_location = 0x60000000;

158
ports/mimxrt10xx/linking/common.ld Normal file
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@ -0,0 +1,158 @@
/* Template for iMX RT 10xx linking. This is the last of four linker scripts passed in.
The first three provide variables for this one.
Boards can setup reserved flash with _ld_reserved_flash_size in board.ld. */
ENTRY(Reset_Handler)
code_size = 1M;
_ld_default_stack_size = 20K;
/* Default reserved flash to nothing. */
_ld_reserved_flash_size = DEFINED(_ld_reserved_flash_size) ? _ld_reserved_flash_size : 0K ;
MEMORY
{
/* These next two sections are included in place of a bootloader. If a UF2 is used to load, it
will ignore these two sections because it lives there. */
/* This is the first block and is read so that the bootrom knows the optimal way to interface with the flash chip. */
FLASH_CONFIG (rx) : ORIGIN = flash_config_location, LENGTH = 512
/* This can't move because the bootrom looks at this address. */
FLASH_IVT (rx) : ORIGIN = 0x60001000, LENGTH = 4K
/* Place the ISRs 48k in to leave room for the bootloader when it is available. */
FLASH_TEXT (rx) : ORIGIN = 0x6000C000, LENGTH = code_size - 48K
FLASH_FATFS (r) : ORIGIN = 0x60100000, LENGTH = _ld_flash_size - code_size - _ld_reserved_flash_size
/* Teensy uses the last bit of flash for recovery. */
RESERVED_FLASH : ORIGIN = 0x60100000 + _ld_flash_size - _ld_reserved_flash_size, LENGTH = _ld_reserved_flash_size
OCRAM (rwx) : ORIGIN = 0x20200000, LENGTH = ram_size - 64K
DTCM (x) : ORIGIN = 0x20000000, LENGTH = 32K
ITCM (x) : ORIGIN = 0x00000000, LENGTH = 32K
}
__RAM_VECTOR_TABLE_SIZE_BYTES = 0;
SECTIONS
{
.flash_config :
{
. = ALIGN(4);
KEEP(* (.boot_hdr.conf))
. = ALIGN(4);
} > FLASH_CONFIG
.ivt :
{
. = ALIGN(4);
KEEP(* (.boot_hdr.ivt))
KEEP(* (.boot_hdr.boot_data))
KEEP(* (.boot_hdr.dcd_data))
. = ALIGN(4);
} > FLASH_IVT
image_vector_table = LOADADDR(.ivt);
.text :
{
. = ALIGN(4);
__VECTOR_TABLE = .;
__VECTOR_RAM = .;
_ld_isr_table = .;
KEEP(*(.isr_vector)) /* Startup code */
*(EXCLUDE_FILE(
*flexspi_nor_flash_ops.o
*fsl_flexspi.o
) .text*) /* .text* sections (code) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} > FLASH_TEXT
.ARM.exidx :
{
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
_etext = .; /* define a global symbol at end of code */
__etext = .; /* define a global symbol at end of code */
} > FLASH_TEXT
_ld_filesystem_start = ORIGIN(FLASH_FATFS);
_ld_filesystem_end = _ld_filesystem_start + LENGTH(FLASH_FATFS);
.data :
{
. = ALIGN(4);
_sidata = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data*) /* .data* sections */
*flexspi_nor_flash_ops.o(.text*)
*fsl_flexspi.o(.text*)
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > OCRAM AT> FLASH_TEXT
/* Uninitialized data section */
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
_ld_heap_start = .;
PROVIDE(end = .);
} > OCRAM
_ld_heap_end = ORIGIN(OCRAM) + LENGTH(OCRAM);
.itcm :
{
. = ALIGN(4);
*(.itcm.*)
. = ALIGN(4);
} > ITCM AT> FLASH_TEXT
_ld_itcm_destination = ADDR(.itcm);
_ld_itcm_flash_copy = LOADADDR(.itcm);
_ld_itcm_size = SIZEOF(.itcm);
.dtcm_data :
{
. = ALIGN(4);
*(.dtcm_data.*)
. = ALIGN(4);
} > DTCM AT> FLASH_TEXT
_ld_dtcm_data_destination = ADDR(.dtcm_data);
_ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data);
_ld_dtcm_data_size = SIZEOF(.dtcm_data);
.dtcm_bss :
{
. = ALIGN(4);
*(.dtcm_bss.*)
. = ALIGN(4);
} > DTCM AT> DTCM
_ld_dtcm_bss_start = ADDR(.dtcm_bss);
_ld_dtcm_bss_end = ADDR(.dtcm_bss) + SIZEOF(.dtcm_bss);
.stack :
{
. = ALIGN(8);
_ld_stack_bottom = .;
. += _ld_default_stack_size;
} > DTCM
_ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM);
_estack = _ld_stack_top;
.ARM.attributes 0 : { *(.ARM.attributes) }
}
ASSERT(__data_end__ <= ORIGIN(FLASH_TEXT) + LENGTH(FLASH_TEXT), "region FLASH_TEXT overflowed with text and data")

1
ports/mimxrt10xx/linking/flash/AT25SF128A.ld Normal file
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@ -0,0 +1 @@
_ld_flash_size = 16M;

1
ports/mimxrt10xx/linking/flash/IS25LP064A.ld Normal file
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@ -0,0 +1 @@
_ld_flash_size = 8M;

1
ports/mimxrt10xx/linking/flash/IS25WP064A.ld Normal file
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@ -0,0 +1 @@
_ld_flash_size = 8M;

1
ports/mimxrt10xx/linking/flash/W25Q16JV.ld Normal file
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@ -0,0 +1 @@
_ld_flash_size = 2M;

1
ports/mimxrt10xx/linking/flash/W25Q64JV.ld Normal file
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@ -0,0 +1 @@
_ld_flash_size = 8M;

12
ports/mimxrt10xx/mpconfigport.h
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@ -28,11 +28,17 @@
#ifndef __INCLUDED_MPCONFIGPORT_H
#define __INCLUDED_MPCONFIGPORT_H
#include <stdint.h>
#define MICROPY_PY_SYS_PLATFORM "NXP IMXRT10XX"
#define SPI_FLASH_MAX_BAUDRATE 24000000
extern uint8_t _ld_filesystem_start;
extern uint8_t _ld_filesystem_end;
extern uint8_t _ld_default_stack_size;
// 20kiB stack
#define CIRCUITPY_DEFAULT_STACK_SIZE 0x5000
#define CIRCUITPY_DEFAULT_STACK_SIZE ((uint32_t) &_ld_default_stack_size)
#define MICROPY_PY_BUILTINS_NOTIMPLEMENTED (0)
#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (0)
#define MICROPY_PY_FUNCTION_ATTRS (0)
@ -40,6 +46,10 @@
#define MICROPY_PY_UJSON (1)
#define MICROPY_PY_REVERSE_SPECIAL_METHODS (0)
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR ((uint32_t) &_ld_filesystem_start)
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE ((uint32_t) (&_ld_filesystem_end - &_ld_filesystem_start))
#include "py/circuitpy_mpconfig.h"
#define MICROPY_PORT_ROOT_POINTERS \

17
ports/mimxrt10xx/mpconfigport.mk
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@ -1,6 +1,4 @@
# Define an equivalent for MICROPY_LONGINT_IMPL, to pass to $(MPY-TOOL) in py/mkrules.mk
# $(MPY-TOOL) needs to know what kind of longint to use (if any) to freeze long integers.
# This should correspond to the MICROPY_LONGINT_IMPL definition in mpconfigport.h.
LD_FILE = $(FLASH).ld $(CHIP_FAMILY).ld imxrt10xx.ld
ifeq ($(LONGINT_IMPL),NONE)
MPY_TOOL_LONGINT_IMPL = -mlongint-impl=none
@ -16,5 +14,18 @@ endif
INTERNAL_LIBM = 1
USB_DEVICES = "CDC,MSC,HID"
USB_SERIAL_NUMBER_LENGTH = 32
USB_MSC_MAX_PACKET_SIZE = 512
INTERNAL_FLASH_FILESYSTEM = 1
CIRCUITPY_DISPLAYIO = 0
CIRCUITPY_AUDIOIO = 0
CIRCUITPY_AUDIOBUSIO = 0
CIRCUITPY_FREQUENCYIO = 0
CIRCUITPY_I2CSLAVE = 0
CIRCUITPY_NVM = 0
CIRCUITPY_ROTARYIO = 0
LONGINT_IMPL = MPZ

2
ports/mimxrt10xx/mphalport.c
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@ -49,7 +49,7 @@ void mp_hal_delay_ms(mp_uint_t delay) {
}
void mp_hal_delay_us(mp_uint_t delay) {
#ifdef MIMXRT1011_SERIES
#if defined(MIMXRT1011_SERIES) || defined(MIMXRT1021_SERIES)
SDK_DelayAtLeastUs(delay, SystemCoreClock);
#else
SDK_DelayAtLeastUs(delay);

371
ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/clocks.c Normal file
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@ -0,0 +1,371 @@
/*
* This file is part of the Micro Python project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2019 Artur Pacholec
* Copyright (c) 2020 Scott Shawcroft
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "mpconfigport.h"
#include "fsl_clock.h"
#include "fsl_iomuxc.h"
// These values are pulled from the SDK's devices/MIMXRT1021/project_template/clock_config.* files.
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = {
.enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
.loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
// Based on the hello_world example in the SDK
void clocks_init(void) {
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
* unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
* well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
* well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
#endif
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 2);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
* unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
* well.*/
#ifndef SKIP_SYSCLK_INIT
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
#endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
* well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Tx clock source. */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
CLOCK_EnableClock(kCLOCK_Iomuxc);
}

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
* Copyright (c) 2019 Artur Pacholec
* Copyright (c) 2020 Scott Shawcroft
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/obj.h"
#include "py/mphal.h"
#include "mimxrt10xx/periph.h"
LPI2C_Type *mcu_i2c_banks[] = { LPI2C1, LPI2C2, LPI2C3, LPI2C4 };
const mcu_periph_obj_t mcu_i2c_sda_list[8] = {
PERIPH_PIN(1, 0, kIOMUXC_LPI2C1_SDA_SELECT_INPUT, 0, &pin_GPIO_AD_B1_15),
PERIPH_PIN(1, 6, kIOMUXC_LPI2C1_SDA_SELECT_INPUT, 1, &pin_GPIO_EMC_03),
PERIPH_PIN(2, 0, kIOMUXC_LPI2C2_SDA_SELECT_INPUT, 0, &pin_GPIO_AD_B1_09),
PERIPH_PIN(2, 2, kIOMUXC_LPI2C2_SDA_SELECT_INPUT, 1, &pin_GPIO_EMC_18),
PERIPH_PIN(3, 1, kIOMUXC_LPI2C3_SDA_SELECT_INPUT, 0, &pin_GPIO_AD_B0_09),
PERIPH_PIN(3, 4, kIOMUXC_LPI2C3_SDA_SELECT_INPUT, 1, &pin_GPIO_SD_B0_01),
PERIPH_PIN(4, 2, kIOMUXC_LPI2C4_SDA_SELECT_INPUT, 0, &pin_GPIO_EMC_10),
PERIPH_PIN(4, 3, kIOMUXC_LPI2C4_SDA_SELECT_INPUT, 1, &pin_GPIO_SD_B1_03),
};
const mcu_periph_obj_t mcu_i2c_scl_list[8] = {
PERIPH_PIN(1, 0, kIOMUXC_LPI2C1_SCL_SELECT_INPUT, 0, &pin_GPIO_AD_B1_14),
PERIPH_PIN(1, 6, kIOMUXC_LPI2C1_SCL_SELECT_INPUT, 1, &pin_GPIO_EMC_02),
PERIPH_PIN(2, 0, kIOMUXC_LPI2C2_SCL_SELECT_INPUT, 0, &pin_GPIO_AD_B1_08),
PERIPH_PIN(2, 2, kIOMUXC_LPI2C2_SCL_SELECT_INPUT, 1, &pin_GPIO_EMC_19),
PERIPH_PIN(3, 1, kIOMUXC_LPI2C3_SCL_SELECT_INPUT, 0, &pin_GPIO_AD_B0_08),
PERIPH_PIN(3, 4, kIOMUXC_LPI2C3_SCL_SELECT_INPUT, 1, &pin_GPIO_SD_B0_00),
PERIPH_PIN(4, 2, kIOMUXC_LPI2C4_SCL_SELECT_INPUT, 0, &pin_GPIO_EMC_11),
PERIPH_PIN(4, 3, kIOMUXC_LPI2C4_SCL_SELECT_INPUT, 1, &pin_GPIO_SD_B1_02),
};
LPSPI_Type *mcu_spi_banks[] = { LPSPI1, LPSPI2, LPSPI3, LPSPI4 };
const mcu_periph_obj_t mcu_spi_sck_list[8] = {
PERIPH_PIN(1, 1, kIOMUXC_LPSPI1_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_B0_10),
PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SCK_SELECT_INPUT, 1, &pin_GPIO_SD_B0_02),
PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 0, &pin_GPIO_EMC_00),
PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 1, &pin_GPIO_EMC_10),
PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 2, &pin_GPIO_SD_B1_07),
PERIPH_PIN(3, 2, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_B1_12),
PERIPH_PIN(4, 2, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_B1_02),
PERIPH_PIN(4, 4, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 1, &pin_GPIO_EMC_32),
};
const mcu_periph_obj_t mcu_spi_mosi_list[8] = {
PERIPH_PIN(1, 1, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 0, &pin_GPIO_AD_B0_13),
PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDO_SELECT_INPUT, 1, &pin_GPIO_SD_B0_05),
PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 0, &pin_GPIO_EMC_03),
PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 1, &pin_GPIO_EMC_13),
PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 2, &pin_GPIO_SD_B1_09),
PERIPH_PIN(3, 2, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 0, &pin_GPIO_AD_B1_15),
PERIPH_PIN(4, 2, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 0, &pin_GPIO_AD_B1_05),
PERIPH_PIN(4, 4, kIOMUXC_LPSPI2_SDO_SELECT_INPUT, 1, &pin_GPIO_EMC_35),
};
const mcu_periph_obj_t mcu_spi_miso_list[8] = {
PERIPH_PIN(1, 1, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 0, &pin_GPIO_AD_B0_12),
PERIPH_PIN(1, 4, kIOMUXC_LPSPI1_SDI_SELECT_INPUT, 1, &pin_GPIO_SD_B0_04),
PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 0, &pin_GPIO_EMC_02),
PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 1, &pin_GPIO_EMC_12),
PERIPH_PIN(2, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 2, &pin_GPIO_SD_B1_08),
PERIPH_PIN(3, 2, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 0, &pin_GPIO_AD_B1_14),
PERIPH_PIN(4, 2, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 0, &pin_GPIO_AD_B1_04),
PERIPH_PIN(4, 4, kIOMUXC_LPSPI2_SDI_SELECT_INPUT, 1, &pin_GPIO_EMC_34),
};
LPUART_Type *mcu_uart_banks[] = { LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 };
const mcu_periph_obj_t mcu_uart_rx_list[16] = {
PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_07),
PERIPH_PIN(2, 2, kIOMUXC_LPUART2_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_23),
PERIPH_PIN(2, 2, kIOMUXC_LPUART2_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B1_09),
PERIPH_PIN(3, 2, kIOMUXC_LPUART3_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_07),
PERIPH_PIN(3, 2, kIOMUXC_LPUART3_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B0_15),
PERIPH_PIN(4, 2, kIOMUXC_LPUART4_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_03),
PERIPH_PIN(4, 2, kIOMUXC_LPUART4_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_33),
PERIPH_PIN(4, 2, kIOMUXC_LPUART4_RX_SELECT_INPUT, 2, &pin_GPIO_AD_B1_11),
PERIPH_PIN(5, 2, kIOMUXC_LPUART5_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_39),
PERIPH_PIN(5, 2, kIOMUXC_LPUART5_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B0_11),
PERIPH_PIN(6, 2, kIOMUXC_LPUART6_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_13),
PERIPH_PIN(6, 2, kIOMUXC_LPUART6_RX_SELECT_INPUT, 1, &pin_GPIO_SD_B1_01),
PERIPH_PIN(7, 2, kIOMUXC_LPUART7_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_35),
PERIPH_PIN(7, 2, kIOMUXC_LPUART7_RX_SELECT_INPUT, 1, &pin_GPIO_SD_B0_05),
PERIPH_PIN(8, 2, kIOMUXC_LPUART8_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_27),
PERIPH_PIN(8, 2, kIOMUXC_LPUART8_RX_SELECT_INPUT, 1, &pin_GPIO_SD_B1_03),
};
const mcu_periph_obj_t mcu_uart_tx_list[16] = {
PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_06),
PERIPH_PIN(2, 2, kIOMUXC_LPUART2_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_22),
PERIPH_PIN(2, 2, kIOMUXC_LPUART2_TX_SELECT_INPUT, 1, &pin_GPIO_AD_B1_08),
PERIPH_PIN(3, 2, kIOMUXC_LPUART3_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_06),
PERIPH_PIN(3, 2, kIOMUXC_LPUART3_TX_SELECT_INPUT, 1, &pin_GPIO_AD_B0_14),
PERIPH_PIN(4, 2, kIOMUXC_LPUART4_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_02),
PERIPH_PIN(4, 2, kIOMUXC_LPUART4_TX_SELECT_INPUT, 1, &pin_GPIO_EMC_32),
PERIPH_PIN(4, 2, kIOMUXC_LPUART4_TX_SELECT_INPUT, 2, &pin_GPIO_AD_B1_10),
PERIPH_PIN(5, 2, kIOMUXC_LPUART5_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_38),
PERIPH_PIN(5, 2, kIOMUXC_LPUART5_TX_SELECT_INPUT, 1, &pin_GPIO_AD_B0_10),
PERIPH_PIN(6, 2, kIOMUXC_LPUART6_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_12),
PERIPH_PIN(6, 2, kIOMUXC_LPUART6_TX_SELECT_INPUT, 1, &pin_GPIO_SD_B1_00),
PERIPH_PIN(7, 2, kIOMUXC_LPUART7_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_34),
PERIPH_PIN(7, 2, kIOMUXC_LPUART7_TX_SELECT_INPUT, 1, &pin_GPIO_SD_B0_04),
PERIPH_PIN(8, 2, kIOMUXC_LPUART8_TX_SELECT_INPUT, 0, &pin_GPIO_EMC_26),
PERIPH_PIN(8, 2, kIOMUXC_LPUART8_TX_SELECT_INPUT, 1, &pin_GPIO_SD_B1_02),
};
const mcu_pwm_obj_t mcu_pwm_list[39] = {
PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, 1, &pin_GPIO_EMC_26),
PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, 1, &pin_GPIO_AD_B1_06),
PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, 1, &pin_GPIO_EMC_24),
PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmA, 1, &pin_GPIO_AD_B1_08),
PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, 1, &pin_GPIO_EMC_22),
PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmA, 1, &pin_GPIO_AD_B1_10),
PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, 1, &pin_GPIO_EMC_20),
PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmA, 6, &pin_GPIO_AD_B1_12),
PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, 1, &pin_GPIO_EMC_27),
PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmB, 1, &pin_GPIO_AD_B1_07),
PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, 1, &pin_GPIO_EMC_25),
PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmB, 1, &pin_GPIO_AD_B1_09),
PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, 1, &pin_GPIO_EMC_23),
PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmB, 1, &pin_GPIO_AD_B1_11),
PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, 1, &pin_GPIO_EMC_21),
PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmB, 6, &pin_GPIO_AD_B1_13),
PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmX, 7, &pin_GPIO_EMC_28),
PWM_PIN(PWM1, kPWM_Module_1, kPWM_PwmX, 7, &pin_GPIO_EMC_29),
PWM_PIN(PWM1, kPWM_Module_2, kPWM_PwmX, 7, &pin_GPIO_EMC_30),
PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, 1, &pin_GPIO_EMC_38),
PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmA, 4, &pin_GPIO_AD_B0_14),
PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, 1, &pin_GPIO_EMC_36),
PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmA, 4, &pin_GPIO_AD_B0_12),
PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, 1, &pin_GPIO_EMC_30),
PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmA, 4, &pin_GPIO_AD_B0_10),
PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, 1, &pin_GPIO_EMC_28),
PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmA, 4, &pin_GPIO_AD_B0_06),
PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, 1, &pin_GPIO_EMC_39),
PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmB, 4, &pin_GPIO_AD_B0_15),
PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, 1, &pin_GPIO_EMC_37),
PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmB, 4, &pin_GPIO_AD_B0_13),
PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, 1, &pin_GPIO_EMC_31),
PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmB, 4, &pin_GPIO_AD_B0_11),
PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, 1, &pin_GPIO_EMC_29),
PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmB, 4, &pin_GPIO_AD_B0_07),
PWM_PIN(PWM2, kPWM_Module_0, kPWM_PwmX, 6, &pin_GPIO_EMC_10),
PWM_PIN(PWM2, kPWM_Module_1, kPWM_PwmX, 6, &pin_GPIO_EMC_11),
PWM_PIN(PWM2, kPWM_Module_2, kPWM_PwmX, 6, &pin_GPIO_EMC_12),
PWM_PIN(PWM2, kPWM_Module_3, kPWM_PwmX, 6, &pin_GPIO_EMC_13),
};

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2019 Artur Pacholec
* Copyright (c) 2020 Scott Shawcroft
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PERIPH_H
#define MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PERIPH_H
extern const mcu_periph_obj_t mcu_i2c_sda_list[8];
extern const mcu_periph_obj_t mcu_i2c_scl_list[8];
extern const mcu_periph_obj_t mcu_spi_sck_list[8];
extern const mcu_periph_obj_t mcu_spi_mosi_list[8];
extern const mcu_periph_obj_t mcu_spi_miso_list[8];
extern const mcu_periph_obj_t mcu_uart_rx_list[16];
extern const mcu_periph_obj_t mcu_uart_tx_list[16];
extern const mcu_pwm_obj_t mcu_pwm_list[39];
#endif // MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PERIP_H

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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2019 Lucian Copeland for Adafruit Industries
* Copyright (c) 2019 Artur Pacholec
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/obj.h"
#include "py/mphal.h"
#include "mimxrt10xx/pins.h"
const mcu_pin_obj_t pin_GPIO_AD_B0_00 = PIN(GPIO1, 0, GPIO_AD_B0_00, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_01 = PIN(GPIO1, 1, GPIO_AD_B0_01, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_02 = PIN(GPIO1, 2, GPIO_AD_B0_02, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_03 = PIN(GPIO1, 3, GPIO_AD_B0_03, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_04 = PIN(GPIO1, 4, GPIO_AD_B0_04, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_05 = PIN(GPIO1, 5, GPIO_AD_B0_05, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_06 = PIN(GPIO1, 6, GPIO_AD_B0_06, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_07 = PIN(GPIO1, 7, GPIO_AD_B0_07, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_08 = PIN(GPIO1, 8, GPIO_AD_B0_08, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_09 = PIN(GPIO1, 9, GPIO_AD_B0_09, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_10 = PIN(GPIO1, 10, GPIO_AD_B0_10, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_11 = PIN(GPIO1, 11, GPIO_AD_B0_11, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_12 = PIN(GPIO1, 12, GPIO_AD_B0_12, ADC1, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_13 = PIN(GPIO1, 13, GPIO_AD_B0_13, ADC2, 0);
const mcu_pin_obj_t pin_GPIO_AD_B0_14 = PIN(GPIO1, 14, GPIO_AD_B0_14, ADC2, 1);
const mcu_pin_obj_t pin_GPIO_AD_B0_15 = PIN(GPIO1, 15, GPIO_AD_B0_15, ADC1, 2);
const mcu_pin_obj_t pin_GPIO_AD_B1_00 = PIN(GPIO1, 16, GPIO_AD_B1_00, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_AD_B1_01 = PIN(GPIO1, 17, GPIO_AD_B1_01, ADC1, 3);
const mcu_pin_obj_t pin_GPIO_AD_B1_02 = PIN(GPIO1, 18, GPIO_AD_B1_02, ADC2, 3);
const mcu_pin_obj_t pin_GPIO_AD_B1_03 = PIN(GPIO1, 19, GPIO_AD_B1_03, ADC1, 4);
const mcu_pin_obj_t pin_GPIO_AD_B1_04 = PIN(GPIO1, 20, GPIO_AD_B1_04, ADC2, 4);
const mcu_pin_obj_t pin_GPIO_AD_B1_05 = PIN(GPIO1, 21, GPIO_AD_B1_05, ADC2, 5);
const mcu_pin_obj_t pin_GPIO_AD_B1_06 = PIN(GPIO1, 22, GPIO_AD_B1_06, ADC2, 6);
const mcu_pin_obj_t pin_GPIO_AD_B1_07 = PIN(GPIO1, 23, GPIO_AD_B1_07, ADC2, 7);
const mcu_pin_obj_t pin_GPIO_AD_B1_08 = PIN(GPIO1, 24, GPIO_AD_B1_08, ADC2, 8);
const mcu_pin_obj_t pin_GPIO_AD_B1_09 = PIN(GPIO1, 25, GPIO_AD_B1_09, ADC2, 9);
const mcu_pin_obj_t pin_GPIO_AD_B1_10 = PIN(GPIO1, 26, GPIO_AD_B1_10, ADC2, 10);
const mcu_pin_obj_t pin_GPIO_AD_B1_11 = PIN(GPIO1, 27, GPIO_AD_B1_11, ADC2, 11);
const mcu_pin_obj_t pin_GPIO_AD_B1_12 = PIN(GPIO1, 28, GPIO_AD_B1_12, ADC2, 12);
const mcu_pin_obj_t pin_GPIO_AD_B1_13 = PIN(GPIO1, 29, GPIO_AD_B1_13, ADC2, 13);
const mcu_pin_obj_t pin_GPIO_AD_B1_14 = PIN(GPIO1, 30, GPIO_AD_B1_14, ADC2, 14);
const mcu_pin_obj_t pin_GPIO_AD_B1_15 = PIN(GPIO1, 31, GPIO_AD_B1_15, ADC2, 15);
const mcu_pin_obj_t pin_GPIO_EMC_00 = PIN(GPIO2, 0, GPIO_EMC_00, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_01 = PIN(GPIO2, 1, GPIO_EMC_01, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_02 = PIN(GPIO2, 2, GPIO_EMC_02, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_03 = PIN(GPIO2, 3, GPIO_EMC_03, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_04 = PIN(GPIO2, 4, GPIO_EMC_04, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_05 = PIN(GPIO2, 5, GPIO_EMC_05, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_06 = PIN(GPIO2, 6, GPIO_EMC_06, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_07 = PIN(GPIO2, 7, GPIO_EMC_07, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_08 = PIN(GPIO2, 8, GPIO_EMC_08, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_09 = PIN(GPIO2, 9, GPIO_EMC_09, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_10 = PIN(GPIO2, 10, GPIO_EMC_10, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_11 = PIN(GPIO2, 11, GPIO_EMC_11, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_12 = PIN(GPIO2, 12, GPIO_EMC_12, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_13 = PIN(GPIO2, 13, GPIO_EMC_13, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_14 = PIN(GPIO2, 14, GPIO_EMC_14, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_15 = PIN(GPIO2, 15, GPIO_EMC_15, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_16 = PIN(GPIO2, 16, GPIO_EMC_16, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_17 = PIN(GPIO2, 17, GPIO_EMC_17, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_18 = PIN(GPIO2, 18, GPIO_EMC_18, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_19 = PIN(GPIO2, 19, GPIO_EMC_19, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_20 = PIN(GPIO2, 20, GPIO_EMC_20, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_21 = PIN(GPIO2, 21, GPIO_EMC_21, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_22 = PIN(GPIO2, 22, GPIO_EMC_22, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_23 = PIN(GPIO2, 23, GPIO_EMC_23, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_24 = PIN(GPIO2, 24, GPIO_EMC_24, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_25 = PIN(GPIO2, 25, GPIO_EMC_25, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_26 = PIN(GPIO2, 26, GPIO_EMC_26, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_27 = PIN(GPIO2, 27, GPIO_EMC_27, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_28 = PIN(GPIO2, 28, GPIO_EMC_28, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_29 = PIN(GPIO2, 29, GPIO_EMC_29, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_30 = PIN(GPIO2, 30, GPIO_EMC_30, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_31 = PIN(GPIO2, 31, GPIO_EMC_31, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_32 = PIN(GPIO3, 0, GPIO_EMC_32, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_33 = PIN(GPIO3, 1, GPIO_EMC_33, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_34 = PIN(GPIO3, 2, GPIO_EMC_34, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_35 = PIN(GPIO3, 3, GPIO_EMC_35, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_36 = PIN(GPIO3, 4, GPIO_EMC_36, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_37 = PIN(GPIO3, 5, GPIO_EMC_37, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_38 = PIN(GPIO3, 6, GPIO_EMC_38, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_39 = PIN(GPIO3, 7, GPIO_EMC_39, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_40 = PIN(GPIO3, 8, GPIO_EMC_40, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_EMC_41 = PIN(GPIO3, 9, GPIO_EMC_41, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B0_00 = PIN(GPIO3, 13, GPIO_SD_B0_00, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B0_01 = PIN(GPIO3, 14, GPIO_SD_B0_01, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B0_02 = PIN(GPIO3, 15, GPIO_SD_B0_02, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B0_03 = PIN(GPIO3, 16, GPIO_SD_B0_03, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B0_04 = PIN(GPIO3, 17, GPIO_SD_B0_04, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B0_05 = PIN(GPIO3, 18, GPIO_SD_B0_05, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B0_06 = PIN(GPIO3, 19, GPIO_SD_B0_06, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_00 = PIN(GPIO3, 20, GPIO_SD_B1_00, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_01 = PIN(GPIO3, 21, GPIO_SD_B1_01, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_02 = PIN(GPIO3, 22, GPIO_SD_B1_02, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_03 = PIN(GPIO3, 23, GPIO_SD_B1_03, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_04 = PIN(GPIO3, 24, GPIO_SD_B1_04, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_05 = PIN(GPIO3, 25, GPIO_SD_B1_05, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_06 = PIN(GPIO3, 26, GPIO_SD_B1_06, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_07 = PIN(GPIO3, 27, GPIO_SD_B1_07, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_08 = PIN(GPIO3, 28, GPIO_SD_B1_08, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_09 = PIN(GPIO3, 29, GPIO_SD_B1_09, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_10 = PIN(GPIO3, 30, GPIO_SD_B1_10, NO_ADC, 0);
const mcu_pin_obj_t pin_GPIO_SD_B1_11 = PIN(GPIO3, 31, GPIO_SD_B1_11, NO_ADC, 0);

129
ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1021/pins.h Normal file
View File

@ -0,0 +1,129 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2019 Artur Pacholec
* Copyright (c) 2020 Scott Shawcroft
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PINS_H
#define MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PINS_H
extern const mcu_pin_obj_t pin_GPIO_AD_B0_00;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_01;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_02;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_03;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_04;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_05;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_06;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_07;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_08;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_09;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_10;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_11;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_12;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_13;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_14;
extern const mcu_pin_obj_t pin_GPIO_AD_B0_15;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_00;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_01;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_02;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_03;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_04;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_05;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_06;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_07;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_08;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_09;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_10;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_11;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_12;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_13;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_14;
extern const mcu_pin_obj_t pin_GPIO_AD_B1_15;
extern const mcu_pin_obj_t pin_GPIO_EMC_00;
extern const mcu_pin_obj_t pin_GPIO_EMC_01;
extern const mcu_pin_obj_t pin_GPIO_EMC_02;
extern const mcu_pin_obj_t pin_GPIO_EMC_03;
extern const mcu_pin_obj_t pin_GPIO_EMC_04;
extern const mcu_pin_obj_t pin_GPIO_EMC_05;
extern const mcu_pin_obj_t pin_GPIO_EMC_06;
extern const mcu_pin_obj_t pin_GPIO_EMC_07;
extern const mcu_pin_obj_t pin_GPIO_EMC_08;
extern const mcu_pin_obj_t pin_GPIO_EMC_09;
extern const mcu_pin_obj_t pin_GPIO_EMC_10;
extern const mcu_pin_obj_t pin_GPIO_EMC_11;
extern const mcu_pin_obj_t pin_GPIO_EMC_12;
extern const mcu_pin_obj_t pin_GPIO_EMC_13;
extern const mcu_pin_obj_t pin_GPIO_EMC_14;
extern const mcu_pin_obj_t pin_GPIO_EMC_15;
extern const mcu_pin_obj_t pin_GPIO_EMC_16;
extern const mcu_pin_obj_t pin_GPIO_EMC_17;
extern const mcu_pin_obj_t pin_GPIO_EMC_18;
extern const mcu_pin_obj_t pin_GPIO_EMC_19;
extern const mcu_pin_obj_t pin_GPIO_EMC_20;
extern const mcu_pin_obj_t pin_GPIO_EMC_21;
extern const mcu_pin_obj_t pin_GPIO_EMC_22;
extern const mcu_pin_obj_t pin_GPIO_EMC_23;
extern const mcu_pin_obj_t pin_GPIO_EMC_24;
extern const mcu_pin_obj_t pin_GPIO_EMC_25;
extern const mcu_pin_obj_t pin_GPIO_EMC_26;
extern const mcu_pin_obj_t pin_GPIO_EMC_27;
extern const mcu_pin_obj_t pin_GPIO_EMC_28;
extern const mcu_pin_obj_t pin_GPIO_EMC_29;
extern const mcu_pin_obj_t pin_GPIO_EMC_30;
extern const mcu_pin_obj_t pin_GPIO_EMC_31;
extern const mcu_pin_obj_t pin_GPIO_EMC_32;
extern const mcu_pin_obj_t pin_GPIO_EMC_33;
extern const mcu_pin_obj_t pin_GPIO_EMC_34;
extern const mcu_pin_obj_t pin_GPIO_EMC_35;
extern const mcu_pin_obj_t pin_GPIO_EMC_36;
extern const mcu_pin_obj_t pin_GPIO_EMC_37;
extern const mcu_pin_obj_t pin_GPIO_EMC_38;
extern const mcu_pin_obj_t pin_GPIO_EMC_39;
extern const mcu_pin_obj_t pin_GPIO_EMC_40;
extern const mcu_pin_obj_t pin_GPIO_EMC_41;
extern const mcu_pin_obj_t pin_GPIO_SD_B0_00;
extern const mcu_pin_obj_t pin_GPIO_SD_B0_01;
extern const mcu_pin_obj_t pin_GPIO_SD_B0_02;
extern const mcu_pin_obj_t pin_GPIO_SD_B0_03;
extern const mcu_pin_obj_t pin_GPIO_SD_B0_04;
extern const mcu_pin_obj_t pin_GPIO_SD_B0_05;
extern const mcu_pin_obj_t pin_GPIO_SD_B0_06;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_00;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_01;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_02;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_03;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_04;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_05;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_06;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_07;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_08;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_09;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_10;
extern const mcu_pin_obj_t pin_GPIO_SD_B1_11;
#endif // MICROPY_INCLUDED_MIMXRT10XX_PERIPHERALS_MIMXRT1021_PINS_H

2
ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c
View File

@ -71,7 +71,7 @@ const mcu_periph_obj_t mcu_spi_sck_list[8] = {
PERIPH_PIN(2, 2, kIOMUXC_LPSPI2_SCK_SELECT_INPUT, 1, &pin_GPIO_EMC_00),
PERIPH_PIN(3, 7, kIOMUXC_LPSPI3_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_B0_00),
PERIPH_PIN(3, 2, kIOMUXC_LPSPI3_SCK_SELECT_INPUT, 0, &pin_GPIO_AD_B1_15),
PERIPH_PIN(3, 2, kIOMUXC_LPSPI3_SCK_SELECT_INPUT, 1, &pin_GPIO_AD_B1_15),
PERIPH_PIN(4, 3, kIOMUXC_LPSPI4_SCK_SELECT_INPUT, 0, &pin_GPIO_B0_03),
PERIPH_PIN(4, 1, kIOMUXC_LPSPI4_SCK_SELECT_INPUT, 1, &pin_GPIO_B1_07),

2
ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h
View File

@ -70,6 +70,8 @@ extern LPUART_Type *mcu_uart_banks[];
#ifdef MIMXRT1011_SERIES
#include "MIMXRT1011/periph.h"
#elif defined(MIMXRT1021_SERIES)
#include "MIMXRT1021/periph.h"
#elif defined(MIMXRT1062_SERIES)
#include "MIMXRT1062/periph.h"
#endif

2
ports/mimxrt10xx/peripherals/mimxrt10xx/pins.h
View File

@ -68,6 +68,8 @@ typedef struct {
#ifdef MIMXRT1011_SERIES
#include "MIMXRT1011/pins.h"
#elif defined(MIMXRT1021_SERIES)
#include "MIMXRT1021/pins.h"
#elif defined(MIMXRT1062_SERIES)
#include "MIMXRT1062/pins.h"
#endif

2
ports/mimxrt10xx/reset.c
View File

@ -35,5 +35,5 @@ void reset(void) {
}
bool bootloader_available(void) {
return &_bootloader_dbl_tap >= 0;
return SNVS->LPGPR[0] >= 0;
}

2
ports/mimxrt10xx/reset.h
View File

@ -34,8 +34,6 @@
#define DBL_TAP_MAGIC 0xf01669ef // Randomly selected, adjusted to have first and last bit set
#define DBL_TAP_MAGIC_QUICK_BOOT 0xf02669ef
extern volatile uint32_t _bootloader_dbl_tap;
void reset_to_bootloader(void);
void reset(void);
bool bootloader_available(void);

2
ports/mimxrt10xx/sdk

@ -1 +1 @@
Subproject commit 2251c7b79343966a57a0f36d897873dd40b692b9
Subproject commit 4e7438e654f4a6b4f386b4bb9e817d74a0fbffc7

10
ports/mimxrt10xx/supervisor/internal_flash.c
View File

@ -166,11 +166,13 @@ void supervisor_flash_init(void) {
}
__enable_irq();
SCB_EnableDCache();
init_done = true;
}
static inline uint32_t lba2addr(uint32_t block) {
return ((uint32_t)__fatfs_flash_start_addr) + block * FILESYSTEM_BLOCK_SIZE;
return CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR + block * FILESYSTEM_BLOCK_SIZE;
}
uint32_t supervisor_flash_get_block_size(void) {
@ -178,7 +180,7 @@ uint32_t supervisor_flash_get_block_size(void) {
}
uint32_t supervisor_flash_get_block_count(void) {
return ((uint32_t) __fatfs_flash_length) / FILESYSTEM_BLOCK_SIZE;
return CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE;
}
void supervisor_flash_flush(void) {
@ -191,20 +193,20 @@ void supervisor_flash_flush(void) {
__disable_irq();
status = flexspi_nor_flash_erase_sector(FLEXSPI, sector_addr);
__enable_irq();
if (status != kStatus_Success) {
printf("Page erase failure %ld!\r\n", status);
return;
}
__enable_irq();
for (int i = 0; i < SECTOR_SIZE / FLASH_PAGE_SIZE; ++i) {
__disable_irq();
status = flexspi_nor_flash_page_program(FLEXSPI, sector_addr + i * FLASH_PAGE_SIZE, (void *)_flash_cache + i * FLASH_PAGE_SIZE);
__enable_irq();
if (status != kStatus_Success) {
printf("Page program failure %ld!\r\n", status);
return;
}
__enable_irq();
}
DCACHE_CleanInvalidateByRange(_flash_page_addr, SECTOR_SIZE);

201
ports/mimxrt10xx/supervisor/port.c
View File

@ -3,8 +3,8 @@
*
* The MIT License (MIT)
*
* Copyright (c) 2017 Scott Shawcroft for Adafruit Industries
* Copyright (c) 2017 Artur Pacholec
* Copyright (c) 2020 Scott Shawcroft for Adafruit Industries
* Copyright (c) 2020 Artur Pacholec
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -24,6 +24,12 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "boards/board.h"
#include "supervisor/port.h"
@ -54,16 +60,139 @@
#include "fsl_gpio.h"
#include "fsl_lpuart.h"
void mpu_init(void)
{
ARM_MPU_Disable();
// Device memories must be accessed in order.
#define DEVICE 2
// Normal memory can have accesses reorder and prefetched.
#define NORMAL 0
SCB_EnableDCache();
SCB_EnableICache();
// Prevents instruction access.
#define NO_EXECUTION 1
#define EXECUTION 0
// Shareable if the memory system manages coherency.
#define NOT_SHAREABLE 0
#define SHAREABLE 1
//
#define NOT_CACHEABLE 0
#define CACHEABLE 1
#define NOT_BUFFERABLE 0
#define BUFFERABLE 1
#define NO_SUBREGIONS 0
extern uint32_t _ld_flash_size;
extern uint8_t _ld_dtcm_bss_start;
extern uint8_t _ld_dtcm_bss_end;
extern uint8_t _ld_dtcm_data_destination;
extern uint8_t _ld_dtcm_data_size;
extern uint8_t _ld_dtcm_data_flash_copy;
extern uint8_t _ld_itcm_destination;
extern uint8_t _ld_itcm_size;
extern uint8_t _ld_itcm_flash_copy;
// This is called before RAM is setup! Be very careful what you do here.
void SystemInitHook(void) {
// asm("bkpt");
/* Disable I cache and D cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
{
SCB_DisableICache();
}
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
{
SCB_DisableDCache();
}
// Configure FlexRAM. The e is one block of ITCM (0b11) and DTCM (0b10). The rest is two OCRAM
// (0b01). We shift in zeroes for all unimplemented banks.
IOMUXC_GPR->GPR17 = (0xe5555555) >> (32 - 2 * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
// Switch from FlexRAM fuse config to the IOMUXC values.
IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(1);
// Let the core know the TCM sizes changed.
uint32_t current_gpr14 = IOMUXC_GPR->GPR14;
current_gpr14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK;
current_gpr14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(0x6);
current_gpr14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK;
current_gpr14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(0x6);
IOMUXC_GPR->GPR14 = current_gpr14;
/* Disable MPU */
ARM_MPU_Disable();
// Copy all of the code to run from ITCM.
memcpy(&_ld_itcm_destination, &_ld_itcm_flash_copy, (size_t) &_ld_itcm_size);
// Copy all of the data to run from DTCM.
memcpy(&_ld_dtcm_data_destination, &_ld_dtcm_data_flash_copy, (size_t) &_ld_dtcm_data_size);
// Clear DTCM bss.
memset(&_ld_dtcm_bss_start, 0, (size_t) (&_ld_dtcm_bss_end - &_ld_dtcm_bss_start));
// The first number in RBAR is the region number. When searching for a policy, the region with
// the highest number wins. If none match, then the default policy set at enable applies.
// This is an undocumented region and is likely more registers.
MPU->RBAR = ARM_MPU_RBAR(8, 0xC0000000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, DEVICE, NOT_SHAREABLE, NOT_CACHEABLE, NOT_BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512MB);
// This is the SEMC region where external RAM and 8+ flash would live. Disable for now, even though the EVKs have stuff here.
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(NO_EXECUTION, ARM_MPU_AP_NONE, DEVICE, NOT_SHAREABLE, NOT_CACHEABLE, NOT_BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_1GB);
// FlexSPI2 is 0x70000000
// This the first 1MB of flash is the bootloader and CircuitPython read-only data.
MPU->RBAR = ARM_MPU_RBAR(10, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_1MB);
// The remainder of flash is the fat filesystem which could have code on it too. Make sure that
// we set the region to the minimal size so that bad data doesn't get speculatively fetched.
// Thanks to Damien for the tip!
uint32_t region_size = ARM_MPU_REGION_SIZE_32B;
uint32_t filesystem_size = &_ld_filesystem_end - &_ld_filesystem_start;
while (filesystem_size > (1u << (region_size + 1))) {
region_size += 1;
}
// Mask out as much of the remainder as we can. For example on an 8MB flash, 7MB are for the
// filesystem. The region_size here must be a power of 2 so it is 8MB. Using the subregion mask
// we can ignore 1/8th size chunks. So, we ignore the last 1MB using the subregion.
uint32_t remainder = (1u << (region_size + 1)) - filesystem_size;
uint32_t subregion_size = (1u << (region_size + 1)) / 8;
uint16_t subregion_mask = 0xff00 >> (remainder / subregion_size);
MPU->RBAR = ARM_MPU_RBAR(11, 0x60100000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, (uint8_t) subregion_mask, region_size);
// This the ITCM. Set it to read-only because we've loaded everything already and it's easy to
// accidentally write the wrong value to 0x00000000 (aka NULL).
MPU->RBAR = ARM_MPU_RBAR(12, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_32KB);
// This the DTCM.
MPU->RBAR = ARM_MPU_RBAR(13, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_32KB);
// This is OCRAM.
MPU->RBAR = ARM_MPU_RBAR(14, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512KB);
// We steal 64k from FlexRAM for ITCM and DTCM so disable those memory regions here.
MPU->RBAR = ARM_MPU_RBAR(15, 0x20280000U);
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, 0x80, ARM_MPU_REGION_SIZE_512KB);
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
/* Enable I cache and D cache */
SCB_EnableDCache();
SCB_EnableICache();
}
safe_mode_t port_init(void) {
mpu_init();
clocks_init();
// Configure millisecond timer initialization.
@ -129,7 +258,7 @@ void reset_port(void) {
}
void reset_to_bootloader(void) {
_bootloader_dbl_tap = DBL_TAP_MAGIC;
SNVS->LPGPR[0] = DBL_TAP_MAGIC;
reset();
}
@ -137,23 +266,64 @@ void reset_cpu(void) {
reset();
}
extern uint32_t _heap_start, _estack;
extern uint32_t _ld_heap_start, _ld_heap_end, _ld_stack_top, _ld_stack_bottom;
uint32_t *port_stack_get_limit(void) {
return &_heap_start;
return &_ld_heap_start;
}
uint32_t *port_stack_get_top(void) {
return &_estack;
return &_ld_stack_top;
}
uint32_t *port_heap_get_bottom(void) {
return &_ld_heap_start;
}
// Get heap top address
uint32_t *port_heap_get_top(void) {
return &_ld_heap_end;
}
extern uint32_t __bss_end__;
// Place the word to save just after our BSS section that gets blanked.
void port_set_saved_word(uint32_t value) {
__bss_end__ = value;
SNVS->LPGPR[1] = value;
}
uint32_t port_get_saved_word(void) {
return __bss_end__;
return SNVS->LPGPR[1];
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
__attribute__((used)) void MemManage_Handler(void)
{
reset_into_safe_mode(MEM_MANAGE);
while (true) {
asm("nop;");
}
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
__attribute__((used)) void BusFault_Handler(void)
{
reset_into_safe_mode(MEM_MANAGE);
while (true) {
asm("nop;");
}
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
__attribute__((used)) void UsageFault_Handler(void)
{
reset_into_safe_mode(MEM_MANAGE);
while (true) {
asm("nop;");
}
}
/**
@ -166,3 +336,4 @@ __attribute__((used)) void HardFault_Handler(void)
asm("nop;");
}
}

4
py/map.c
View File

@ -33,6 +33,8 @@
#include "py/misc.h"
#include "py/runtime.h"
#include "supervisor/linker.h"
#if MICROPY_DEBUG_VERBOSE // print debugging info
#define DEBUG_PRINT (1)
#else // don't print debugging info
@ -143,7 +145,7 @@ STATIC void mp_map_rehash(mp_map_t *map) {
// - returns slot, with key non-null and value=MP_OBJ_NULL if it was added
// MP_MAP_LOOKUP_REMOVE_IF_FOUND behaviour:
// - returns NULL if not found, else the slot if was found in with key null and value non-null
mp_map_elem_t *mp_map_lookup(mp_map_t *map, mp_obj_t index, mp_map_lookup_kind_t lookup_kind) {
mp_map_elem_t *PLACE_IN_ITCM(mp_map_lookup)(mp_map_t *map, mp_obj_t index, mp_map_lookup_kind_t lookup_kind) {
// If the map is a fixed array then we must only be called for a lookup
assert(!map->is_fixed || lookup_kind == MP_MAP_LOOKUP);

3
py/mpstate.c
View File

@ -25,9 +25,10 @@
*/
#include "py/mpstate.h"
#include "supervisor/linker.h"
#if MICROPY_DYNAMIC_COMPILER
mp_dynamic_compiler_t mp_dynamic_compiler = {0};
#endif
mp_state_ctx_t mp_state_ctx;
mp_state_ctx_t PLACE_IN_DTCM_BSS(mp_state_ctx);

3
py/obj.c
View File

@ -38,6 +38,7 @@
#include "py/stackctrl.h"
#include "py/stream.h" // for mp_obj_print
#include "supervisor/linker.h"
#include "supervisor/shared/stack.h"
#include "supervisor/shared/translate.h"
@ -128,7 +129,7 @@ void mp_obj_print_exception(const mp_print_t *print, mp_obj_t exc) {
mp_print_str(print, "\n");
}
bool mp_obj_is_true(mp_obj_t arg) {
bool PLACE_IN_ITCM(mp_obj_is_true)(mp_obj_t arg) {
if (arg == mp_const_false) {
return 0;
} else if (arg == mp_const_true) {

5
py/objdict.c
View File

@ -31,6 +31,7 @@
#include "py/builtin.h"
#include "py/objtype.h"
#include "supervisor/linker.h"
#include "supervisor/shared/translate.h"
#define MP_OBJ_IS_DICT_TYPE(o) (MP_OBJ_IS_OBJ(o) && ((mp_obj_base_t*)MP_OBJ_TO_PTR(o))->type->make_new == dict_make_new)
@ -324,7 +325,7 @@ STATIC mp_obj_t dict_popitem(mp_obj_t self_in) {
}
STATIC MP_DEFINE_CONST_FUN_OBJ_1(dict_popitem_obj, dict_popitem);
STATIC mp_obj_t dict_update(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) {
STATIC mp_obj_t PLACE_IN_ITCM(dict_update)(size_t n_args, const mp_obj_t *args, mp_map_t *kwargs) {
mp_check_self(MP_OBJ_IS_DICT_TYPE(args[0]));
mp_obj_dict_t *self = MP_OBJ_TO_PTR(args[0]);
mp_ensure_not_fixed(self);
@ -590,7 +591,7 @@ size_t mp_obj_dict_len(mp_obj_t self_in) {
return self->map.used;
}
mp_obj_t mp_obj_dict_store(mp_obj_t self_in, mp_obj_t key, mp_obj_t value) {
mp_obj_t PLACE_IN_ITCM(mp_obj_dict_store)(mp_obj_t self_in, mp_obj_t key, mp_obj_t value) {
mp_check_self(MP_OBJ_IS_DICT_TYPE(self_in));
mp_obj_dict_t *self = MP_OBJ_TO_PTR(self_in);
mp_ensure_not_fixed(self);

4
py/objfun.c
View File

@ -34,6 +34,8 @@
#include "py/bc.h"
#include "py/stackctrl.h"
#include "supervisor/linker.h"
#if MICROPY_DEBUG_VERBOSE // print debugging info
#define DEBUG_PRINT (1)
#else // don't print debugging info
@ -249,7 +251,7 @@ mp_code_state_t *mp_obj_fun_bc_prepare_codestate(mp_obj_t self_in, size_t n_args
}
#endif
STATIC mp_obj_t fun_bc_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_obj_t *args) {
STATIC mp_obj_t PLACE_IN_ITCM(fun_bc_call)(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_obj_t *args) {
MP_STACK_CHECK();
DEBUG_printf("Input n_args: " UINT_FMT ", n_kw: " UINT_FMT "\n", n_args, n_kw);

4
py/qstr.c
View File

@ -33,6 +33,8 @@
#include "py/qstr.h"
#include "py/gc.h"
#include "supervisor/linker.h"
// NOTE: we are using linear arrays to store and search for qstr's (unique strings, interned strings)
// ultimately we will replace this with a static hash table of some kind
// also probably need to include the length in the string data, to allow null bytes in the string
@ -248,7 +250,7 @@ qstr qstr_from_strn(const char *str, size_t len) {
return q;
}
mp_uint_t qstr_hash(qstr q) {
mp_uint_t PLACE_IN_ITCM(qstr_hash)(qstr q) {
return Q_GET_HASH(find_qstr(q));
}

8
py/runtime.c
View File

@ -200,7 +200,7 @@ mp_obj_t mp_load_build_class(void) {
return MP_OBJ_FROM_PTR(&mp_builtin___build_class___obj);
}
void mp_store_name(qstr qst, mp_obj_t obj) {
void PLACE_IN_ITCM(mp_store_name)(qstr qst, mp_obj_t obj) {
DEBUG_OP_printf("store name %s <- %p\n", qstr_str(qst), obj);
mp_obj_dict_store(MP_OBJ_FROM_PTR(mp_locals_get()), MP_OBJ_NEW_QSTR(qst), obj);
}
@ -211,7 +211,7 @@ void mp_delete_name(qstr qst) {
mp_obj_dict_delete(MP_OBJ_FROM_PTR(mp_locals_get()), MP_OBJ_NEW_QSTR(qst));
}
void mp_store_global(qstr qst, mp_obj_t obj) {
void PLACE_IN_ITCM(mp_store_global)(qstr qst, mp_obj_t obj) {
DEBUG_OP_printf("store global %s <- %p\n", qstr_str(qst), obj);
mp_obj_dict_store(MP_OBJ_FROM_PTR(mp_globals_get()), MP_OBJ_NEW_QSTR(qst), obj);
}
@ -283,7 +283,7 @@ mp_obj_t mp_unary_op(mp_unary_op_t op, mp_obj_t arg) {
}
}
mp_obj_t mp_binary_op(mp_binary_op_t op, mp_obj_t lhs, mp_obj_t rhs) {
mp_obj_t PLACE_IN_ITCM(mp_binary_op)(mp_binary_op_t op, mp_obj_t lhs, mp_obj_t rhs) {
DEBUG_OP_printf("binary " UINT_FMT " %q %p %p\n", op, mp_binary_op_method_name[op], lhs, rhs);
// TODO correctly distinguish inplace operators for mutable objects
@ -641,7 +641,7 @@ mp_obj_t mp_call_method_n_kw(size_t n_args, size_t n_kw, const mp_obj_t *args) {
#if !MICROPY_STACKLESS
STATIC
#endif
void mp_call_prepare_args_n_kw_var(bool have_self, size_t n_args_n_kw, const mp_obj_t *args, mp_call_args_t *out_args) {
void PLACE_IN_ITCM(mp_call_prepare_args_n_kw_var)(bool have_self, size_t n_args_n_kw, const mp_obj_t *args, mp_call_args_t *out_args) {
mp_obj_t fun = *args++;
mp_obj_t self = MP_OBJ_NULL;
if (have_self) {

10
py/runtime.h
View File

@ -29,6 +29,8 @@
#include "py/mpstate.h"
#include "py/pystack.h"
#include "supervisor/linker.h"
typedef enum {
MP_VM_RETURN_NORMAL,
MP_VM_RETURN_YIELD,
@ -84,10 +86,10 @@ void mp_arg_parse_all_kw_array(size_t n_pos, size_t n_kw, const mp_obj_t *args,
NORETURN void mp_arg_error_terse_mismatch(void);
NORETURN void mp_arg_error_unimpl_kw(void);
static inline mp_obj_dict_t *mp_locals_get(void) { return MP_STATE_THREAD(dict_locals); }
static inline void mp_locals_set(mp_obj_dict_t *d) { MP_STATE_THREAD(dict_locals) = d; }
static inline mp_obj_dict_t *mp_globals_get(void) { return MP_STATE_THREAD(dict_globals); }
static inline void mp_globals_set(mp_obj_dict_t *d) { MP_STATE_THREAD(dict_globals) = d; }
static inline mp_obj_dict_t *PLACE_IN_ITCM(mp_locals_get)(void) { return MP_STATE_THREAD(dict_locals); }
static inline void PLACE_IN_ITCM(mp_locals_set)(mp_obj_dict_t *d) { MP_STATE_THREAD(dict_locals) = d; }
static inline mp_obj_dict_t *PLACE_IN_ITCM(mp_globals_get)(void) { return MP_STATE_THREAD(dict_globals); }
static inline void PLACE_IN_ITCM(mp_globals_set)(mp_obj_dict_t *d) { MP_STATE_THREAD(dict_globals) = d; }
mp_obj_t mp_load_name(qstr qst);
mp_obj_t mp_load_global(qstr qst);

4
py/vm.c
View File

@ -35,6 +35,8 @@
#include "py/bc0.h"
#include "py/bc.h"
#include "supervisor/linker.h"
#if 0
#define TRACE(ip) printf("sp=%d ", (int)(sp - &code_state->state[0] + 1)); mp_bytecode_print2(ip, 1, code_state->fun_bc->const_table);
#else
@ -116,7 +118,7 @@
// MP_VM_RETURN_NORMAL, sp valid, return value in *sp
// MP_VM_RETURN_YIELD, ip, sp valid, yielded value in *sp
// MP_VM_RETURN_EXCEPTION, exception in fastn[0]
mp_vm_return_kind_t mp_execute_bytecode(mp_code_state_t *code_state, volatile mp_obj_t inject_exc) {
mp_vm_return_kind_t PLACE_IN_ITCM(mp_execute_bytecode)(mp_code_state_t *code_state, volatile mp_obj_t inject_exc) {
#define SELECTIVE_EXC_IP (0)
#if SELECTIVE_EXC_IP
#define MARK_EXC_IP_SELECTIVE() { code_state->ip = ip; } /* stores ip 1 byte past last opcode */

4
py/vmentrytable.h
View File

@ -29,7 +29,9 @@
#pragma clang diagnostic ignored "-Winitializer-overrides"
#endif // __clang__
static const void *const entry_table[256] = {
#include "supervisor/linker.h"
static const void *const PLACE_IN_DTCM_DATA(entry_table[256]) = {
[0 ... 255] = &&entry_default,
[MP_BC_LOAD_CONST_FALSE] = &&entry_MP_BC_LOAD_CONST_FALSE,
[MP_BC_LOAD_CONST_NONE] = &&entry_MP_BC_LOAD_CONST_NONE,

42
supervisor/linker.h Executable file
View File

@ -0,0 +1,42 @@
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2020 Scott Shawcroft for Adafruit Industries
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// These macros are used to place code and data into different linking sections.
#ifndef MICROPY_INCLUDED_SUPERVISOR_LINKER_H
#define MICROPY_INCLUDED_SUPERVISOR_LINKER_H
#if defined(IMXRT10XX)
#define PLACE_IN_DTCM_DATA(name) name __attribute__((section(".dtcm_data." #name )))
#define PLACE_IN_DTCM_BSS(name) name __attribute__((section(".dtcm_bss." #name )))
#define PLACE_IN_ITCM(name) __attribute__((section(".itcm." #name ))) name
#else
#define PLACE_IN_DTCM_DATA(name) name
#define PLACE_IN_DTCM_BSS(name) name
#define PLACE_IN_ITCM(name) name
#endif
#endif // MICROPY_INCLUDED_SUPERVISOR_LINKER_H

6
supervisor/port.h
View File

@ -60,6 +60,12 @@ uint32_t *port_stack_get_limit(void);
// Get stack top address
uint32_t *port_stack_get_top(void);
// Get heap bottom address
uint32_t *port_heap_get_bottom(void);
// Get heap top address
uint32_t *port_heap_get_top(void);
// Save and retrieve a word from memory that is preserved over reset. Used for safe mode.
void port_set_saved_word(uint32_t);
uint32_t port_get_saved_word(void);

2
supervisor/shared/filesystem.c
View File

@ -75,7 +75,7 @@ static void make_sample_code_file(FATFS *fatfs) {
FIL fs;
UINT char_written = 0;
const byte buffer[] = "print('Hello World!')\n";
//Create or modify existing code.py file
//Create or modify existing code.py file
f_open(fatfs, &fs, "/code.py", FA_WRITE | FA_CREATE_ALWAYS);
f_write(&fs, buffer, sizeof(buffer) - 1, &char_written);
f_close(&fs);

7
supervisor/shared/memory.c
View File

@ -39,11 +39,14 @@ uint32_t* low_address;
uint32_t* high_address;
void memory_init(void) {
low_address = port_stack_get_limit();
high_address = port_stack_get_top();
low_address = port_heap_get_bottom();
high_address = port_heap_get_top();
}
void free_memory(supervisor_allocation* allocation) {
if (allocation == NULL) {
return;
}
int32_t index = 0;
bool found = false;
for (index = 0; index < CIRCUITPY_SUPERVISOR_ALLOC_COUNT; index++) {

3
supervisor/shared/safe_mode.c
View File

@ -157,6 +157,9 @@ void print_safe_mode_message(safe_mode_t reason) {
case FLASH_WRITE_FAIL:
serial_write_compressed(translate("Failed to write internal flash."));
break;
case MEM_MANAGE:
serial_write_compressed(translate("Invalid memory access."));
break;
default:
serial_write_compressed(translate("Unknown reason."));
break;

1
supervisor/shared/safe_mode.h
View File

@ -40,6 +40,7 @@ typedef enum {
PROGRAMMATIC_SAFE_MODE,
NORDIC_SOFT_DEVICE_ASSERT,
FLASH_WRITE_FAIL,
MEM_MANAGE,
} safe_mode_t;
safe_mode_t wait_for_safe_mode_reset(void);

7
supervisor/shared/stack.c
View File

@ -46,6 +46,10 @@ void allocate_stack(void) {
mp_uint_t c_size = (uint32_t) port_stack_get_top() - sp;
if (port_stack_get_top() != port_heap_get_top()) {
return;
}
stack_alloc = allocate_memory(c_size + next_stack_size + EXCEPTION_STACK_SIZE, true);
if (stack_alloc == NULL) {
stack_alloc = allocate_memory(c_size + CIRCUITPY_DEFAULT_STACK_SIZE + EXCEPTION_STACK_SIZE, true);
@ -71,6 +75,9 @@ void stack_init(void) {
}
void stack_resize(void) {
if (stack_alloc == NULL) {
return;
}
if (next_stack_size == current_stack_size) {
*stack_alloc->ptr = STACK_CANARY_VALUE;
return;

8
supervisor/shared/tick.c
View File

@ -25,11 +25,13 @@
*/
#include "supervisor/shared/tick.h"
#include "supervisor/linker.h"
#include "supervisor/filesystem.h"
#include "supervisor/shared/autoreload.h"
static volatile uint64_t ticks_ms;
static volatile uint32_t background_ticks_ms32;
static volatile uint64_t PLACE_IN_DTCM_BSS(ticks_ms);
static volatile uint32_t PLACE_IN_DTCM_BSS(background_ticks_ms32);
#if CIRCUITPY_GAMEPAD
#include "shared-module/gamepad/__init__.h"
@ -77,7 +79,7 @@ uint32_t supervisor_ticks_ms32() {
extern void run_background_tasks(void);
void supervisor_run_background_tasks_if_tick() {
void PLACE_IN_ITCM(supervisor_run_background_tasks_if_tick)() {
uint32_t now32 = ticks_ms;
if (now32 == background_ticks_ms32) {

3
tools/build_board_info.py
View File

@ -18,6 +18,7 @@ BIN = ('bin',)
UF2 = ('uf2',)
BIN_UF2 = ('bin', 'uf2')
HEX = ('hex',)
HEX_UF2 = ('hex', 'uf2')
SPK = ('spk',)
# Default extensions
@ -26,7 +27,7 @@ extension_by_port = {
"atmel-samd": UF2,
"stm32f4": BIN,
"cxd56": SPK,
"mimxrt10xx": UF2,
"mimxrt10xx": HEX_UF2,
}
# Per board overrides