This was added by mistake in 8f68e26f79 when
adding support for G4 MCUs, which does not using this get_bank() function.
FLASH_OPTR_DBANK is only defined on G4 and L4 MCUs, so on H7 this
FLASH_BANK_2 code was being wrongly excluded.
Signed-off-by: Damien George <damien@micropython.org>
This commit adds support for the STM32G4 series of MCUs, and a board
definition for NUCLEO_G474RE. This board has the REPL on LPUART1 which is
connected to the on-board ST-link USB-UART.
This commit is based upon prior work of @dpgeorge and @koendv.
MCU support for the STM32H7A3 and B3 families MCUs:
- STM32H7A3xx
- STM32H7A3xxQ (SMPS)
- STM32H7B3xx
- STM32H7B3xxQ (SMPS)
Support has been added for the STM32H7B3I_DK board.
Signed-off-by: Jan Staal <info@janstaal.com>
This is needed to moderate concurrent access to the internal flash, as
while an erase/write is in progress execution will stall on the wireless
core due to the bus being locked.
This implements Figure 10 from AN5289 Rev 3.
Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This commit makes the low-level flash C functions usable by code other than
flashbdev.c (eg by mboot). Changes in this commit are:
- flash_erase() and flash_write() now return an errno error code, a
negative value on error.
- flash_erase() now automatically locks the flash, as well as unlocking it.
- flash_write() now automatically unlocks the flash, as well as locking it.
- flashbdev.c is modified for the above changes.
Signed-off-by: Damien George <damien@micropython.org>
This new series of MCUs is similar to the L4 series with an additional
Cortex-M0 coprocessor. The firmware for the wireless stack must be managed
separately and MicroPython does not currently interface to it. Supported
features so far include: RTC, UART, USB, internal flash filesystem.
The CMSIS files for the STM32 range provide macros to distinguish between
the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer
to use these instead of custom ones.
This is to keep the top-level directory clean, to make it clear what is
core and what is a port, and to allow the repository to grow with new ports
in a sustainable way.
