The Wio Terminal includes a RealTek RTL8720D as a companion to the main chip to provide WiFi and Bluetooth capabilities via eRPC over a UART connection. The WIO Terminal schematic labels some pins as the RXD/TXD for the UART, and that was captured in the board definition for CircuitPython. However, these pins may be used for logging in another mode, but they are not the main pins used to communicate with the RTL chip. The correct configuration is RX on PC24/pad 2 and TX on PB24/pad 0 of SERCOM 0. The comments on the pin definitions now reflect this situation, for anyone trying to get the WiFi/BLE to work on the Wio Terminal.
PicoDVI in CP support 640x480 and 800x480 on Feather DVI, Pico and
Pico W. 1 and 2 bit grayscale are full resolution. 8 and 16 bit
color are half resolution.
Memory layout is modified to give the top most 4k of ram to the
second core. Its MPU is used to prevent flash access after startup.
The port saved word is moved to a watchdog scratch register so that
it doesn't get overwritten by other things in RAM.
Right align status bar and scroll area. This normally gives a few
pixels of padding on the left hand side and improves the odds it is
readable in a case. Fixes#7562
Fixes c stack checking. The length was correct but the top was being
set to the current stack pointer instead of the correct top.
Fixes#7643
This makes Bitmap subscr raise IndexError instead of ValueError
when the index arguments are wrong.
Doing a squash merge to avoid having the `slc_cli_linux` .zip files in the history. They were added in one commit and removed and replaced with a submodule in another.
* Initial commit for xg24
* Fix SLC issue
* Fix SLC extract fail
* Change board's name
* Correct spelling of code
Build immediately after slc generate
* Remove VID and PID
* Change creator and creation id
* Apply new creator_id and creation_id
* Update makefile, error message, mcu_processor function
* Update mpconfigboard.mk
* Update Board extensions, PORT_DEPS
* Update makefile
* Add exclude_patterns
* Show java, jinja2 version
* Show path for debugging CI
* Add requirements-dev for slc
* Add PATH slc_cli
* Update background function
* Add jinja2 PATH
* Show PATH
* Update jinja2 path
* Update jinja2 path
* Update jinja2 path
* Update jinja2 path
* Change slc folder
* Change markupsafe folder
* Add symbolic link for slc
* Update makefile
* Update makefile
* Update MX25R3235F.toml from submodule nvm.toml
* alphabetize the list
* Remove slc_cli_linux folder
* Update slc_cli submodule
---------
Co-authored-by: Chat Nguyen <cvnguyen@silabs.com>
Co-authored-by: silabs-ChatNguyen <chat.nguyen@silabs.com>
Co-authored-by: silabs-ChatNguyen <126220343+silabs-ChatNguyen@users.noreply.github.com>
Previous pins definition stated that the UART1 RTS and CTS were not connected. They are connected and can currently be used via A1 and PWM0 respectively. To make things a little clearer, enabling the RTS1/CTS1.
In #7497 port_background_task was renamed to port_background_tick
but the actual call site wasn't changed. This meant that it was
no longer called!
Rename more functions from task to tick to make it clearer which is
which.
Fixes polling thread looping forever hangs preventing new connections.
Don't lose listening sockets on mp resets and re-init.
Keep better separation of "system" and "user" sockets.
Track socket states to prevent re-use of sockets before closed.
Close REST socket when transaction completes. No post-init.
Remove unnecessary state flags.
In contrast to MidiTrack, this can be controlled from Python code,
turning notes on/off as desired.
Not tested on real HW yet, just the acceptance test based on checking
which notes it thinks are held internally.
