The SAMD21 implementation is an adaption of @jimmo's code for STM32Lxx.
The only changes are the addresses and names of the port registers and the
timing parameters.
SAMD21: The precision is about +/-25ns at 48MHz clock frequency. The first
two cycles are about 40-60 ns longer than set. But still good enough to
drive a neopixel device.
SAMD51: The precision is about +/-30ns at 120MHz clock frequency. Good
enough to drive a neopixel device.
And use mp_hal_ticks_us() for SAM21's mp_hal_ticks_cpu(). The SAMD21 has
no CYCCNT register, and the SysTick register has only a 1 ms span (== 48000
count range).
Clock settings:
- GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51).
- GCLK1: 32768 Hz for driving the PLL.
- GCLK2: 48 MHz for tzhe peripheral clock.
- GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer.
- GCLK8: 1 kHz for WDT (SAMD21 only).
If a 32 kHz crystal is present, it will be used as clock source. Otherwise
the DFLL48M in open-loop mode is used.
GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz. The specified
range is 96 MHz - 120 MHz.