Commit Graph

9 Commits

Author SHA1 Message Date
iabdalkader 3320ec44ed stm32/pyb_can: Add support for CAN FD extended frame ID. 2022-04-02 22:37:45 +11:00
iabdalkader ff287d085f stm32/pyb_can: Enable CAN FD frame support and BRS.
- Enable CAN FD frame support and BRS.
- Optimize the message RAM usage per FDCAN instance.
- Document the usage and different sections of the Message RAM.
2022-04-02 22:37:27 +11:00
Herwin Grobben 517e82eb6b stm32/fdcan: Fix naming with regards to G4 series. 2022-01-27 23:06:13 +11:00
Herwin Grobben 160e4d9a6d stm32/fdcan: Fix FIFO1 usage and handling of error interrupts.
The original code used a independent state with regards to the interrupt.
During heavy bus error conditions the internal state could become
out-of-sync with the interrupts.

Further explanation: during the development of an application using CAN
communication, a interrupt-run-away was found in some situations.  It was
found that the error interrupt triggered (Warning, Passive or Bus-Off, all
triggered it) the run-away.  The only recovery was a reset.

Two problems were found:
- the error interrupt is enabled but not cleared in the interrupt routine;
- an internal variable 'State' that was used to track the message received
  state (empty, new, full, overflow) that was not directly related to
  interrupt that indicated the state.

In this commit these issues are fixed by adding more values for the
interrupt reason (warning, passive, bus off) and clearing the error
interrupts, and making the internal state directly dependent on the
interrupt state for received messages.

Furthermore, introducing the FIFO1 in the CAN receive stage, another issue
existed.  Even if the messages are received into the FIFO1 (by selecting
message filtering for FIFO0 and FIFO1), the interrupt firing was indicating
FIFO0 Rx.  The configuration of the interrupts for this is now also fixed.
The CAN peripheral has 2 interrupt lines going into the NVIC controller.
The assignment of the interrupt reasons to these 2 interrupt lines was
missing.  Now the reception of FIFO1 messages triggers the second interrupt
line.  Other interrupts (Rx FIFO0 and bus error) are assigned to the first
interrupt line.

Tested on a Nucleo-G474, and also checked the HAL function to work with the
H7 family.
2022-01-27 23:01:08 +11:00
iabdalkader d07073f4e2 stm32/fdcan: Support maximum timeout of HAL_MAX_DELAY in can_receive. 2020-07-09 00:38:40 +10:00
iabdalkader 63b2eb27d4 stm32/fdcan: Use FDCAN_RXFxS_FxFL instead of hard-coded value. 2020-07-09 00:38:33 +10:00
iabdalkader 8594389fe7 stm32/fdcan: Use the right FIFO to calc element address in can_receive. 2020-07-09 00:37:50 +10:00
Damien George 69661f3343 all: Reformat C and Python source code with tools/codeformat.py.
This is run with uncrustify 0.70.1, and black 19.10b0.
2020-02-28 10:33:03 +11:00
iabdalkader f7a07b3605 stm32: Add support for FDCAN peripheral, exposed as pyb.CAN.
The new fdcan.c file provides the low-level C interface to the FDCAN
peripheral, and pyb_can.c is updated to support both traditional CAN and
FDCAN, depending on the MCU being compiled for.
2019-09-23 17:00:54 +10:00